JP3163761B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device having a capacitor. Variations can be reduced.

[0002]

2. Description of the Related Art Hitherto, capacitors shown in FIGS. 8 and 9 have been proposed as capacitors for integrated circuit devices.

In FIG. 8, one electrode layer 3 made of metal is formed on an insulating film 2 covering the surface of a semiconductor substrate 1 and an insulating film 4 is formed so as to cover the electrode layer 3. The other electrode layer 5 made of metal is formed on the electrode layer 4 so as to face the electrode layer 3. The capacitor is connected to the electrode layers 3, 5
A configuration in which an insulating film 4 is disposed as a dielectric between them.

The capacitor shown in FIG. 9 is characterized in that the insulating film 4 is formed by laminating a first deposited insulating film 4a, a coating insulating film 4b such as SOG (spin-on glass) and a second deposited insulating film 4c. Except for this, the configuration is the same as that of FIG.

[0005]

In the capacitor shown in FIG. 8 or 9, since the electrode layers 3 and 5 are made of metal,
Low series resistance and excellent frequency characteristics.

However, in the capacitor of FIG. 8, since the insulating film 4 also serves as an interlayer insulating film between the upper and lower wiring layers,
It is formed quite thick. Therefore, there is a problem that the capacitance per unit area decreases.

Further, in the capacitor of FIG. 9, the surface is flattened by utilizing the fluidity of the coating insulating film 4b such as SOG in accordance with the high integration. The thickness of the insulating film 4 becomes uneven between the substrates. Therefore,
The problem is that the capacitance varies considerably within or between the substrates.

An object of the present invention is to increase the capacitance per unit area and reduce the variation in capacitance in an integrated circuit device having a capacitor.

[0009]

According to the present invention, there is provided an integrated circuit device having a substrate on which an integrated circuit is formed, and a capacitor formed on an insulating surface of the substrate and connected to the integrated circuit. The capacitor is one of an electrode layer formed on the insulating surface and a first insulating film formed on the insulating surface so as to cover the one electrode layer; One having a hole corresponding to a part of the electrode layer, and an end face of the first insulating film along an inner wall of the hole.
And increase the size of the hole upwards
A second insulating film formed as described above and the one of the ones in the hole.
A third insulating film formed so as to cover the electrode layer and the second insulating film, and the other electrode layer formed so as to face the one electrode layer via the third insulating film. It is characterized by comprising.

[0010]

According to the structure of the present invention, the hole of the first insulating film is
A second insulating film is formed along the inner wall and a first insulating film is formed.
The first electrode layer and the second insulating film are
Since the third insulating film is formed and the third insulating film is used as a dielectric of the capacitor, the third insulating film is formed to be thin and uniform even if the first insulating film is also used as an interlayer insulating film. can do. In addition, the size of the first insulating film hole is increased
The second insulating film was formed so as to increase toward
As the step coverage of the third insulating film is improved,
Thus, the electric field concentration is reduced at the edge of the capacitor.

[0011]

1 to 4 show a method of manufacturing an integrated circuit device according to an embodiment of the present invention. Steps (1) to (4) corresponding to the respective drawings will be sequentially described.

(1) An Al layer and a WSi (tungsten silicide) layer are sequentially deposited on the insulating film 12 such as silicon oxide formed on the surface of the semiconductor substrate 10 such as silicon by sputtering or the like. By patterning, an electrode layer 16A composed of the Al layer 14A and the WSi layer 15A and a wiring layer 16B composed of the Al layer 14B and the WSi layer 15B are formed. Then, on the upper surface of the substrate, an insulating film 18 made of silicon oxide is formed by a CVD (chemical vapor deposition) method or the like so as to cover the electrode layer 16A and the wiring layer 16B. To form an insulating film 20 made of SOG or the like. The insulating film 18 is formed to a thickness that can prevent impurities in the insulating film 20 from reaching the electrode layer 16A, the wiring layer 16B, and the like.

After forming the insulating film 20, on the upper surface of the substrate,
A resist layer 22 is formed to cover the insulating film 20. Then, holes 22A corresponding to a desired capacitor formation pattern are formed in the resist layer 22 by photolithography.

(2) Next, a hole 23A corresponding to the hole 22A is formed in the lamination of the insulating films 18 and 20 by selective etching using the resist layer 22 as a mask, and the central portion of the electrode layer 16A is exposed. The electrode layer 1 is formed on the upper surface of the substrate.
An insulating film 24 of silicon oxide or the like is formed by a CVD method or the like covering the exposed portion of 6A and the insulating film 20. The insulating film 24 is formed by an etch-back process described later.
It is used to change the shape of the hole 23A of the 0 stack.

(3) Next, the insulating film 24 is etched back by anisotropic etching so that the insulating film 24 is formed along the inner wall 24A of the laminated hole 23A of the insulating films 18 and 20.
Is removed so that remains. As a result, the hole 23A has a shape such that the hole size increases upward due to the remaining portion 24A of the insulating film 24.

Thereafter, an insulating film 2 made of silicon oxide or the like is formed on the upper surface of the substrate by a CVD method so as to cover the exposed portion of the electrode layer 16A, the remaining portion 24A of the insulating film 24, and the insulating film 20.
6 is formed so as to obtain a required interlayer film thickness.

(4) Next, a part of the insulating films 18, 20, and 26 is removed by selective etching using the resist layer as a mask to form a connection hole corresponding to a part of the wiring layer 16B. Then, on the upper surface of the substrate, a metal such as Al or an Al alloy is applied and patterned to form an electrode layer 16A.
Is formed, and a wiring layer 28B connected to the wiring layer 16B is formed. As a result, a capacitor having a configuration in which the insulating film 26 is disposed as a dielectric between the electrode layers 16A and 28A is obtained.

In such a capacitor, one electrode layer (16A) is formed in the hole of the first insulating film (18, 20 ).
And a third insulating film (2 ) covering the second insulating film (24A).
Since 6) can be formed thin, the capacitance per unit area can be increased. Also, the third
Can be formed to a uniform thickness within the substrate or between the substrates, so that variation in capacitance can be reduced. Further, the first insulating film is a deposited insulating film.
18 and a coating insulating film 20 is laminated on
The third insulating film (24A, 26) is formed of the first insulating film (1
Along the inner wall of the hole of (8, 20).
Because of the heat treatment after forming the connection hole,
A large amount of gas is released from the coating insulating film 20 to form the electrode layer 28A.
Can be suppressed.

FIG. 5 shows a modification of the capacitor, in which the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals. The difference between the capacitor of FIG. 5 and that of FIGS.
The first insulating film 30 has a single-layer structure of a deposited insulating film such as silicon oxide.

In the capacitor shown in FIG. 4 or FIG. 5, the insulating film 24 may be omitted as shown in FIG. In such a case, the step coverage of the insulating film 26 is deteriorated at the step S of the capacitor forming hole, so that the breakdown voltage may be deteriorated. However, FIG. 4 or FIG.
When the remaining portion 24A of the insulating film 24 is disposed in the capacitor forming hole to gradually increase the hole size upward as shown in FIG. 7, the steepness of the step is alleviated and the electric field near the step is reduced. Concentration is eased. Therefore, a thin film can be used as the insulating film 26, and deterioration of the withstand voltage can be prevented.

[0021]

In the capacitor of FIG. 4 or FIG. 5, the electrode layer 16A may have a single-layer structure of the Al layer 14A as shown in FIG. By doing so, the Al layer 14A
In this case, Al hillocks A may be generated to damage the insulating film 26, resulting in deterioration of withstand voltage and short-circuiting of the electrode layers 14A and 28A. However, when the lower electrode layer 16A has a laminated structure of an Al layer and a WSi layer as shown in FIG.
Hillock generation can be suppressed. Therefore, it is possible to prevent the withstand voltage deterioration and the electrode short-circuit, and to use a thin film as the insulating film 26.

In the above embodiment, the Al layer 14A
Alternatively, an Al alloy layer may be used. Further, instead of the WSi layer, a refractory metal such as W or Ti may be used, or a refractory metal silicide different from WSi may be used.

[0024]

As described above, according to the present invention, the first
When the second insulating film is formed along the inner wall of the hole of the insulating film
In both cases, one electrode layer and the second insulating layer are formed in the holes of the first insulating film.
Since the third insulating film is formed to be thin and uniform over the edge film and used as a dielectric of the capacitor, the capacitance per unit area can be increased and the variation in capacitance can be reduced. It is obtained.

Further, the size of the hole in the first insulating film is increased
Since the second insulating film was formed so as to increase toward
The step coverage of the third insulating film is improved, and the electric field concentration is reduced at the edge of the capacitor. Therefore, key
The breakdown voltage of the capacitor is improved, and the capacitance can be increased by reducing the thickness of the third insulating film.

Further, since the lower electrode layer is formed by laminating a refractory metal or its silicide on an Al or Al alloy layer, the generation of Al hillocks in the lower electrode layer is suppressed, and the third insulating film is formed. Damage is prevented. Therefore, the capacity
The withstand voltage of the insulator is improved, and the capacitance can be increased by reducing the thickness of the third insulating film.

[Brief description of the drawings]

FIG. 1

FIG. 4 is a cross-sectional view of a substrate showing a method of manufacturing an integrated circuit device according to one embodiment of the present invention.

FIG. 5 ~

FIG. 7 is a sectional view showing a modification of the capacitor of the integrated circuit device.

FIG. 8 and

FIG. 9 is a cross-sectional view of a substrate showing a capacitor of a conventional integrated circuit device.

[Explanation of symbols]

10: semiconductor substrate, 12, 18, 20, 24, 26, 3
0: insulating film, 14A, 14B: Al layer, 15A, 15
B: WSi layer, 16A, 28A: electrode layer, 16B, 28
B: Wiring layer.

Claims (3)

(57) [Claims] 1. An integrated circuit device comprising: a substrate on which an integrated circuit is formed; and a capacitor formed on an insulating surface of the substrate and connected to the integrated circuit. One electrode layer formed on the surface, and a first insulating film formed on the insulating surface so as to cover the one electrode layer and correspond to a part of the one electrode layer With a hole and on the inner wall of this hole
Along the end surface of the first insulating film and the size of the hole.
A second gap formed to increase the
An edge membrane, the one electrode layer and the second insulator in the hole;
A third insulating film formed to cover the edge film, and the other electrode layer formed to face the one electrode layer via the third insulating film. Integrated circuit device. 2. The method according to claim 1, wherein the first insulating film is applied to a deposited insulating film.
The second and third insulating layers are formed by laminating insulating films.
The integrated circuit device according to claim 1 , wherein a film covers an end surface of the stack along an inner wall of the hole . 3. The one electrode layer comprises: a first layer made of Al or an Al alloy; and a second layer made of a refractory metal or a silicide thereof formed over an upper surface of the first layer. 2. The integrated circuit device according to claim 1, wherein the integrated circuit device comprises: