JPH05297830A - Active matrix liquid crystal driving method and circuit therefor - Google Patents

Abstract

(57) [Abstract] [Purpose] To correct the offset voltage of the voltage lower that composes the sample and hold circuit to increase the number of gray levels that can be displayed. [Structure] The analog switches SA, SB and SD are turned off and the analog switches SC and SE are turned on to set the potential of the other end of the capacitor C1 to VR + VOFF. In this state, the analog switch SA is turned on for a predetermined time and one end of the capacitor C1 is turned on. The potential is set to VI, then the analog switch S
C and SE are turned off and analog switches SB and SD are turned on to set the potentials at the input end and output end of the voltage follower OP to VI-VOFF and VI, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal driving method and circuit for multi-gradation display.

[0002]

2. Description of the Related Art In principle, an active matrix driving type liquid crystal display device using a thin film transistor (TFT) is capable of high quality display, and replaces a CRT display device with a high quality and high definition color display device. Is expected to become mainstream.

FIG. 11 shows a conventional active matrix liquid crystal drive circuit for multi-gradation display. For simplification of description, the liquid crystal display panel 10 is shown as a monochrome display of 4 × 4 pixels in FIG.

The data lines X1 to X1 of the liquid crystal display panel 10
The output end of the data driver 20A is connected to X4,
The output ends of the scan driver 30 are connected to the scan lines Y1 to Y4 of the liquid crystal display panel 10. The data driver 20A and the scan driver 30 are controlled by the control circuit 40A. The control circuit 40A has various control signals T1 to T3, CK1 to CK3, and AP based on the external horizontal synchronization signal HS, vertical synchronization signal VS, and clock CK.
To generate.

In the liquid crystal display panel 10, as shown in FIG. 12, one end electrodes of liquid crystal pixels Cij (i = 1 to 4, j = 1 to 4) are commonly used, and the other end electrodes thereof are thin film transistors Qij.
Is connected to the data line Xj via. The gate of the thin film transistor Qij is connected to the scan line Yi.

In FIG. 11, the data driver 20A
Includes a shift register 21 and four two-stage sample hold circuits SH1 to SH4. The shift register 21 receives the initial pulse T1 generated at the falling timing of the horizontal synchronizing signal HS as shown in FIG. 13 at the serial data input terminal, and receives this at the clock CK.
Are shifted by the clock CK1 passed through the buffer gate, and sample pulses SP1 to SP4 are output from each bit.

Two-stage sample hold circuits SH1 to SH
4 has the same configuration as each other, and the sample and hold circuit in the preceding stage is a voltage follower OPAi (i = 1 to 4),
It is composed of a capacitor CAi and an analog switch SAi, and the sample-hold circuit in the subsequent stage is a voltage follower OPBi, a capacitor CBi, and an analog switch Si.
It consists of Bi. The analog switches SA1 to SA4 are
One end thereof is commonly connected to the output end of the AC conversion / amplification circuit 50 and controlled by the sample pulses SP1 to SP4, respectively. The analog switches SB1 to SB4 are
As shown in FIG. 13, a sample pulse T generated next to the sample pulse SP4 and having the same cycle as the horizontal synchronizing signal HS is generated.
On / off control is performed by 2. Voltage Follower OP
The output terminals of B1 to OPB4 are respectively the liquid crystal display panel 1
0 data lines X1 to X4.

The scan driver 30 includes a buffer gate 31.
To 34 and a shift register 35, the buffer gate 31 to the output end of each bit of the shift register 35.
34 input terminals are connected. Buffer gate 31-
The output terminals of 34 are connected to the scan lines Y1 to Y4 of the liquid crystal display panel 10, respectively. Shift register 35
As shown in FIG. 13, an initial pulse T3 having the same cycle as the vertical synchronizing signal VS is supplied to the serial data input terminal, and this is shifted by the clock CK2 having the same cycle as the horizontal synchronizing signal HS.

The AC converting / amplifying circuit 50 uses a horizontal synchronizing signal H.
AC signal A generated by passing S through a T flip-flop
Based on P, an analog AC video signal VGA in which the polarity of the analog video signal VG is inverted is generated for each line.

In the above structure, the sample pulse SP1
To SP4 are sequentially turned on one by one for a certain period of time, and the analog AC video signal VGA is sequentially written to the capacitors CA1 to CA4. The voltage written in the capacitors CA1 to CA4 is written in the capacitors CB1 to CB4 by turning on the analog switches SB1 to SB4 at the same time for a certain time with the sample pulse T2 and held for 1H (one cycle of the horizontal synchronizing signal). To be done. During this period, the analog AC video signal VGA for the next one line is written in the capacitors CA1 to CA4 in the same manner as described above. First, the thin film transistors Q11 to Q14 are turned on, and the thin film transistors Q21 to Q21.
Q44 is turned off, and liquid crystal pixels C11 to C14 in the first row
The output voltages of the voltage followers OPB1 to OPB4 are written in. In the same manner, the display data is written on the liquid crystal display panel 10 line by line.

FIG. 14 shows a main part of another active matrix liquid crystal drive circuit. While the circuit of FIG. 11 uses two cascaded sample and hold circuits SH1 to SH4, this circuit has two parallel sample and hold circuits SG.
1 to SG4 are used.

Sample hold circuit SGi (i = 1 to 1
4) includes analog switches SAi, SBi, SCi and SDi, capacitors CAi and CBi, and a voltage follower OPi.

The sample hold circuit SGi is controlled by the control signal from the selector 22 as follows.

That is, first, the analog switch SA1
-SA4, SB1 to SB4 and SC1 to SC4 are turned off, analog switches SD1 to SD4 are turned on, and the voltage across the terminals of the capacitors CB1 to CB4 is changed to the data lines X1 to X1 via the voltage followers OP1 to OP4, respectively. Applied to X4.

In this state, the analog switches SA1 to S1
The A4s are turned on one by one in this order, and the analog AC video signal VGA is written in the capacitors CA1 to CA4. Next, when the analog switches SA1 to SA4 are both off, the analog switches SD1 to SD4 are turned off at the same time, and then the analog switches SC1 to SC4 are turned on at the same time, so that the voltage across the terminals of the capacitors CA1 to CA4 is reduced. It is applied to the data lines X1 to X4 for 1H via OP1 to OP4.

Next, the analog switches SB1 to SB4 are turned on one by one in this order, and the analog AC video signal V
GA is written in the capacitors CB1 to CB4. Next, when the analog switches SB1 to SB4 are both off, the analog switches SC1 to SC4 are turned off at the same time, and then the analog switches SD1 to SD4 are turned on at the same time, so that the voltage across the terminals of the capacitors CB1 to CB4 is controlled by the voltage control. It is applied to the data lines X1 to X4 for 1H via OP1 to OP4.

The same processing is performed thereafter.

[0018]

In order to replace a high quality CRT display device with a liquid crystal display device, R (red), G
It is necessary to display 256 gradations for each of (green) and B (blue). Figure 1 shows the transmissivity of liquid crystal pixels with respect to the drive voltage.
5, the liquid crystal pixel applied voltage is about 2 to 6 V for the transmittance of 0 to 100%. Therefore, the voltage of one gradation is (6-2) / 256V = 15 mV.
Therefore, it is necessary to make the error of the driving voltage 15 mV or less.

There are two main causes of the error in the drive voltage. One of them is that the leakage of current from the control input terminal of the analog switch changes the voltage between the terminals of the capacitor in the sample hold circuit (charge offset). ).

Another cause is due to the offset voltage of the voltage follower of the sample hold circuit, which is due to the variation and instability of the threshold voltage of the pair of operating MOS transistors of the differential amplifier circuit.

There are many known correction methods for the former drive voltage error due to charge offset, and the error can be reduced to a practical level. On the other hand, it is difficult to correct the latter drive voltage error due to the offset voltage. This error is ± 100m
There is also about V, so that 16 gradation display is the limit.

In view of the above problems, an object of the present invention is to provide an active matrix liquid crystal driving method capable of increasing the number of gray scales that can be displayed by correcting the offset voltage of the voltage lower forming the sample and hold circuit. And to provide a circuit.

[0023]

A method and a circuit for driving an active matrix liquid crystal according to the present invention will be described with reference to the reference numerals of corresponding constituent elements in the embodiments.

In the active matrix liquid crystal driving method of the first invention, for example, as shown in FIGS. 1 and 2, the output potential of the sample hold circuit SHA is applied to the data line X of the liquid crystal display panel to perform multi-gradation display, and the sample is displayed. The hold circuit SHA turns on the sampling switch SA for a predetermined time, samples the input potential VI at one end of the first capacitor C1, and then outputs the potential at one end of the capacitor C1 via a voltage follower OP.

The feature of the first invention is that a constant potential VR is applied to the input end of the voltage follower OP, the output potential VR + VOFF of the voltage follower OP is stored in the other end of the capacitor C1, and sampling is performed in this state. Switch S
A is turned on for a predetermined time to store the input potential VI at one end of the capacitor C1 and the constant potential V is stored at the other end of the capacitor C1.
By applying R, the floating potential at one end of the capacitor C1 is set to VI-VOFF, and the one end potential VI-VOFF of the capacitor C1 is applied to the input end of the voltage follower OP to set the output potential of the voltage follower OP to VI. ..

In the active matrix liquid crystal drive circuit of the second invention, as shown in FIGS. 1 and 2, for example, the output voltage of the sample hold circuit SHA controlled by the switch control circuit is applied to the data line X of the liquid crystal display panel. Multi-gradation display.

The sample-hold circuit SHA has a first switch element SA whose one end is an input end of the sample-hold circuit SHA, a second switch element SB whose one end is connected to the other end of the first switch element SA, and an input. A voltage follower OP whose end is connected to the other end of the second switch element SB and whose output end is the output end of the sample hold circuit SHA;
Third end whose one end is connected to the input end of the voltage follower OP
A switch element SC, a fourth switch element SD having one end connected to the other end of the third switch element SC and having a constant potential VR applied thereto, and one end connected to the other end of the fourth switch element SD and the other end having a voltage. A fifth switch element SE connected to the output end of the follower OP and one end of the first switch element SA
And a first capacitor C1 having the other end connected to the other end of the fourth switch element SD.

Further, the switch control circuit includes first and second switch control circuits.
And the fourth switch elements SA, SB and SD are turned off, the third and fifth switch elements SC and SE are turned on, and the potential at the other end of the capacitor C1 is set to VR + VOFF. In this state, the first switch element SA is set to a predetermined value. It is turned on for a period of time to set the potential at one end of the capacitor C1 to VI, then the third and fifth switch elements SC and SE are turned off, and the second and fourth switch elements are turned off.
By turning on the switch elements SB and SD of the voltage follower OP, the potentials at the input end and the output end of the voltage follower OP are respectively set to VI-V.
Set to OFF and VI.

In the active matrix liquid crystal driving method of the third invention, the output potential of the sample hold circuit SHB is applied to the data line X of the liquid crystal display panel as shown in FIGS. 9 and 10, and the sample hold circuit SHB is applied.
Outputs the potential at one end of the first capacitor C1 via the voltage follower OP after turning on the sampling switch SA for a predetermined time to sample the input potential VI at one end of the first capacitor C1.

The feature of the third invention is that the first capacitor C
The other end of 1 and one end of the second capacitor C2 are both set to the second constant potential VR2, for example, the ground level, and the first constant potential VR1 is applied to the input end of the voltage follower OP to set the output potential VR1 + VOFF of the voltage follower OP. It is stored in one end of the second capacitor C2, and in this state, the sampling switch SA is turned on for a predetermined time and the first capacitor C2 is stored.
The input potential VI is stored at one end of the first capacitor C1, the other end of the first capacitor C1 and one end of the second capacitor C2 are set to the floating state of the same potential, and the first constant potential VR1 is applied to the other end of the second capacitor C2. The first capacitor C
The floating potential at one end of 1 is VI-VOFF,
The voltage VI-VOFF at one end of the first capacitor C1 is applied to the input end of the voltage follower OP to apply the voltage follower O.
The output potential of P is VI.

In the active matrix liquid crystal drive circuit of the fourth invention, as shown in FIGS. 9 and 10, for example, the output voltage of the sample hold circuit SHB controlled by the switch control circuit is applied to the data line X of the liquid crystal display panel. Multi-gradation display.

The sample-hold circuit SHB has one end that is the input end of the sample-hold circuit SHB, the first switch element SA, one end that is connected to the other end of the first switch element SA, and the other input. A voltage follower OP whose end is connected to the other end of the second switch element SB and whose output end is the output end of the sample hold circuit SHB;
Third end whose one end is connected to the input end of the voltage follower OP
A switch element SC, a fourth switch element SD having one end connected to the other end of the third switch element SC and to which the first constant potential VR1 is applied, and one end connected to the other end of the fourth switch element SD and the other end. Is a fifth switch element SE connected to the output end of the voltage follower OP, a first capacitor C1 having one end connected to the other end of the first switch element SA, and one end connected to the other end of the first capacitor C1 And a second capacitor C2 having the other end connected to the other end of the fourth switch element SD
And a sixth switch element SF having one end connected to the other end of the first capacitor C1 and the other end to which a second constant potential VR2, for example, a ground level is applied.

The switch control circuit includes the first and second switch control circuits.
And the fourth switching elements SA, SB and SD are turned off, and the third, fifth and sixth switching elements SC, SE and SF
Is turned on to set the potential at the other end of the second capacitor C2 to VR1.
+ VOFF, and in this state, the first switch element SA is turned on for a predetermined time to set the potential at one end of the first capacitor C1 to V
I, and then the third, fifth and sixth switch elements SC,
SE and SF are turned off, and the second and fourth switch elements S
B and SD are turned on, and the potentials at the input end and the output end of the voltage follower OP are set to VI-VOFF and VI, respectively.

According to the first to fourth aspects of the invention, the output voltage of the voltage follower OP forming the sample and hold circuit is corrected so as to cancel the offset voltage VOFF, so that the number of gray scales that can be displayed is reduced. Can be large.

The time constant when the input potential VI is sampled by the first capacitor C1 of the third and fourth inventions is as follows: the on resistance of the first switch element SA and the on resistance of the sixth switch element SF. It is determined by the capacitance of the first capacitor C1. On the other hand, the time constant when the input potential VI is sampled by the capacitor C1 of the first invention and the second invention is the ON resistance of the first switch element SA and the fifth constant.
It is determined by the ON resistance of the switch element SE, the capacitance of the capacitor C1, and the outputtable current of the voltage follower OP.

If the output possible current of the voltage follower OP is increased to reduce the time constant, the power consumption of the voltage follower OP increases, so that the output possible current of the voltage follower OP cannot be increased so much. on the other hand,
It is not difficult to reduce the on resistance of the switch element.

Therefore, according to the third and fourth aspects of the present invention, the sampling time of the sample and hold circuit can be further shortened and a higher speed video signal can be dealt with.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows a sample hold circuit SHA used in a data driver of an active matrix liquid crystal drive circuit of the first embodiment. The sample-hold circuit SHA has its input end and output end serving as one end of the analog switch SA and the output end of the voltage follower OP. The other end of the analog switch SA
It is connected to one end of the analog switch SB and one end of the capacitor C1. The other end of the analog switch SB is connected to the input end of the voltage follower OP and the analog switch SC.
Is connected to one end of. The other end of the analog switch SC is connected to one end of the analog switch SD and the positive end of the constant voltage source E. The negative terminal of the constant voltage source E is connected to the ground line. The other end of the analog switch SD is connected to the other end of the capacitor C1 and one end of the analog switch SE, and the other end of the analog switch SE is connected to the output end of the voltage follower OP.

An example of the operation of the sample hold circuit SHA configured as described above will be described with reference to FIG.

(T1) First, the analog switches SA and S
B, SC, SD and SE are all turned off.

(T2) Next, the analog switches SC and SE are turned on, the potential VC at the input end of the voltage follower OP becomes the constant potential VR, the output potential VO of the voltage follower OP and the capacitor C1 and the analog switch SE.
The potential VB of the connection line between and becomes both VR + VOFF.

(T3) Next, the analog switch SA is turned on for a predetermined time, and the potential VA of the connection line between the analog switch SA and the analog switch SB becomes the input potential VI.

(T4) Next, the analog switch SE is turned off, and the potential VB becomes a floating state.

(T5) Next, the analog switch SC is turned off and the analog switch SD is turned on. As a result, the potential VB is lowered by the offset voltage VOFF to become the constant potential VR, so that the potential V in the floating state is
A is also reduced by the offset voltage VOFF to be VI-VOF.
It becomes F.

(T6) Next, the analog switch SB is turned on, the potential VC becomes VI-VOFF which is the same as the potential VA, and the output potential VO becomes (VI-VOFF) + VOFF =
It becomes VI.

In this way, the output potential VO of the voltage follower OP is automatically corrected to cancel the offset voltage VOFF and becomes equal to the input potential VI.

FIG. 3 shows the sample hold circuit SH of FIG.
1 shows an active matrix liquid crystal drive circuit to which A is applied. FIG. 4 shows a main circuit of the data driver 20B shown in FIG. The same components as those in FIG. 11 are designated by the same reference numerals and the description thereof will be omitted.

As the data driver 20B, instead of the two-stage sample hold circuit SHi (i = 1 to 4) of FIG. 11, a sample hold circuit SH1i and a sample hold circuit SH2i are connected in cascade. The sample hold circuits SH1i and SH2i are both shown in FIG.
The sample hold circuit SH has the same configuration.

As shown in FIG. 4, the sample hold circuit S
H1i analog switches SAi, S1i, S3i, S
2i, S4i, the capacitor CAi, and the voltage follower OP1i are respectively the sample hold circuit SH of FIG.
Corresponding to the analog switches SA, SB, SC, SD, SE, the capacitor C1 and the voltage follower OP. Similarly, the analog switches SBi, S5i, S7i, S6i, S8i, the capacitor CBi, and the voltage follower OP2i of the sample hold circuit SH2i are analog switches SA, SB, SC, SD, SE, and SE of the sample hold circuit SH of FIG. 1, respectively. It corresponds to the capacitor C1 and the voltage follower OP. The constant potential line VR in FIG. 4 may be a ground line.

As in the case of FIG. 11, the analog switches SA1 to SA4 are on / off controlled by the sample pulses SP1 to SP4 from the shift register 21, respectively, and the analog switches SB1 to SB4 are all controlled by the control circuit 4.
It is controlled by the sample pulse T2 from 0B.

Sample and hold circuits SH11 to SH14
The data driver 20B includes a switch control circuit 23 in order to control other analog switches of SH21 to SH24. The switch control circuit 23 generates control pulses T4 to T11 as shown in FIG. 5 based on the control signal from the control circuit 40A. Control pulse T4
The period from T11 to T11 is the same as that of the horizontal synchronizing signal HS.

Sample hold circuits SH11 to SH14
And SH21 to SH24 are controlled in the same sequence as in FIG. Analog switches S11 to S14
Are both on / off controlled by a control pulse T4, and the analog switches S21 to S24 are both on / off controlled by a control pulse T5.
The analog switches S31 to S34 are turned on / off by the control pulse T6, and the analog switches S41 to S44 are turned on / off by the control pulse T7. Further, the analog switches S51 to S54 are both on / off controlled by the control pulse T8, the analog switches S61 to S64 are both on / off controlled by the control pulse T9, and the analog switches S71 to S74 are both on / off by the control pulse T10. The analog switches S81 to S84 are controlled to be turned on / off by the control pulse T11.

Next, the operation of the first embodiment constructed as described above will be explained.

First, the sample hold circuits SH11 to SH
At the same time for H14, the operations of (t1) and (t2) are performed. Next, the sample pulses SP1 to SP4 are sequentially turned on one by one for a predetermined time, and the analog AC video signal VGA is sequentially written to the capacitors CA1 to CA4. Next, the operations (t4), (t5), and (t6) are performed, and the corrected voltages written in the capacitors CA1 to CA4 are voltage followers OP11 to OP14.
Is output from.

Next, the sample hold circuits SH21 to SH21.
At the same time, the operations of (t1) and (t2) are performed on H24. Next, the analog switches SB1 to SB4
Are simultaneously turned on for a certain time by sample pulse T2,
The voltages written in the capacitors CA1 to CA4 are written in the capacitors CB1 to CB4. Next, the above (t
4), (t5) and (t6) are performed, and the voltages written and corrected in the capacitors CA1 to CA4 are output from the voltage followers OP21 to OP24 for 1H (one cycle of the horizontal synchronizing signal). .. During this period, the analog AC video signal VGA for the next one line is written in the capacitors CA1 to CA4 in the same manner as described above.

The above operation is repeated in parallel with the operation of the scan driver 30 to display an image on the liquid crystal display panel 10.

The constant potential VR may be at the ground level. In this case, the constant voltage source E becomes unnecessary.

[Second Embodiment] FIG. 6 shows an active matrix liquid crystal drive circuit of the second embodiment. FIG. 7 shows FIG.
The main circuit of the data driver 20C is shown. The same components as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

The data driver 20C includes a sample hold circuit SH1i and a sample hold circuit SH2i.
The difference from the first embodiment is that (i = 1 to 4) are connected in parallel. That is, the sample hold circuit SH
1i and both input ends of the sample hold circuit SH2i are commonly connected to the output end of the AC conversion / amplification circuit 50, and the output end of the sample hold circuit SH1i is an analog switch SW.
1i is connected to the data line Xi, and the output terminal of the sample hold circuit SH2i has an analog switch SW2.
It is connected to the data line Xi via i.

Sample hold circuits SH11 to SH14
And the data driver 20C for controlling the analog switches of SH21 to SH24.
4 is equipped. The switch control circuit 24 is the control circuit 4
Based on the control signal from 0B and the sample pulses SP1 to SP4 from the shift register 21, the sample pulses SP11 to SP14 and the control pulses T4 to T7 whose cycle is twice the cycle of the horizontal synchronizing signal HS as shown in FIG. , Sample pulses SP21 to SP24 and control pulses T8 to T
11 is generated.

Next, the operation of the second embodiment constructed as described above will be explained.

Next, the sample pulses SP11 to SP14 at the same timing as the sample pulses SP1 to SP4 are sequentially turned on one by one for a predetermined time, and the analog AC video signal VGA is sequentially written to the capacitors CA1 to CA4. Next, the operations (t4), (t5), and (t6) are performed, and the voltages written and corrected in the capacitors CA1 to CA4 are output from the voltage followers OP11 to OP14. At the start of this output, the analog switches SW21 to SW24 are turned off, and the analog switch S
W11-SW14 are turned on, voltage follower O
Data line X while the output voltage of P11 to OP14 is 1H
1 to X4.

Next, the sample hold circuits SH21 to SH21.
At the same time, the operations of (t1) and (t2) are performed on H24. Next, the sample pulses SP21 to SP24 having the same timing as the sample pulses SP1 to SP4 are sequentially turned on one by one for a certain period of time, and the analog AC video signal VGA is sequentially written to the capacitors CB1 to CB4. Next, the operations (t4), (t5), and (t6) are performed, and the corrected voltages written in the capacitors CB1 to CB4 are voltage followers OP21 to OP24.
Is output from. At the time of starting the output, the analog switches SW11 to SW14 are turned off, the analog switches SW21 to SW24 are turned on, and the output voltage of the voltage followers OP21 to OP24 becomes 1H after the above 1H.
During this period, the data lines X1 to X4 are applied.

The above operation is repeated in parallel with the operation of the scan driver 30 to display an image on the liquid crystal display panel 10.

[Third Embodiment] FIG. 9 shows a sample hold circuit SHB used in a data driver of the third embodiment. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this sample hold circuit SHB, the capacitor C2 is connected between the capacitor C1 and the analog switch SD, one end of the analog switch SF is connected to the connection portion of the capacitors C1 and C2, and the other end of the analog switch SF is connected. Is connected to the ground line as a constant potential line. The other points are the same as those of the sample hold circuit SHA of FIG.

Next, an example of the operation of the sample hold circuit SHB configured as described above will be described with reference to FIG.

(T1) First, the analog switches SA and S
B, SC, SD, SE and SF are all turned off.

(T2) Next, the analog switches SC and S
When E and SF are turned on, the potential VC at the input end of the voltage follower OP becomes the constant potential VR, and the voltage follower O
The output potential VO of P and the potential VB of the connection line between the capacitor C2 and the analog switch SE are both VR + VOFF.

(T3) Next, the analog switch SA is turned on for a predetermined time, and the potential VA of the connection line between the analog switch SA and the analog switch SB becomes the input potential VI.

(T4) Next, the analog switches SE and SF are turned off, and the potentials VB and VE are brought into a floating state.

(T5) Next, the analog switch SC is turned off, the analog switch SD is turned on, and the potential V
Since B decreases by the offset voltage VOFF to become the constant potential VR, the potential VA in the floating state also decreases by the offset voltage VOFF and becomes VI-VOFF.

(T6) Next, the analog switch SB is turned on, the potential VC becomes VI-VOFF which is the same as the potential VA, and the output potential VO becomes (VI-VOFF) + VOFF =
It becomes VI.

In this way, the output potential VO of the voltage follower OP is automatically corrected to cancel the offset voltage VOFF and becomes equal to the input potential VI.

The time constant when the input potential VI is sampled by the capacitor C1 is determined by the ON resistance of the analog switch SA, the ON resistance of the analog switch SF, and the capacitance of the capacitor C1. On the other hand, the time constant in the case of FIG.
It is determined by the on-resistance of the analog switch SE, the capacitance of the capacitor C1, and the outputtable current of the voltage follower OP. If the output possible current of the voltage follower OP is increased to reduce the time constant, the power consumption of the voltage follower OP increases,
The output current of the voltage follower OP cannot be increased so much. On the other hand, it is not difficult to reduce the on resistance of the analog switch.

Therefore, if the sample hold circuit SHB of the third embodiment is applied to the data driver, the sampling time can be further shortened and a higher speed video signal can be dealt with.

[0078]

As described above, according to the first to fourth aspects of the present invention, the output voltage of the voltage follower forming the sample and hold circuit is corrected so as to cancel the offset voltage, so that the displayable floor It has an excellent effect that the number of adjustments can be increased, and contributes to a high image quality of the liquid crystal display device.

Further, according to the third and fourth inventions, there is an effect that the sampling time of the sample and hold circuit can be further shortened and a higher speed video signal can be dealt with.

[Brief description of drawings]

FIG. 1 is a sample and hold circuit diagram used in a data driver according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the circuit of FIG.

FIG. 3 is a diagram of an active matrix liquid crystal drive circuit according to a first embodiment of the present invention.

FIG. 4 is a circuit diagram of a main part of the data driver of FIG.

5 is a time chart showing the operation of the circuit of FIG.

FIG. 6 is an active matrix liquid crystal drive circuit diagram of a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part of the data driver of FIG.

FIG. 8 is a time chart showing the operation of the circuit of FIG.

FIG. 9 is a sample and hold circuit diagram used in a data driver of a third embodiment of the present invention.

FIG. 10 is a time chart showing the operation of the circuit of FIG.

FIG. 11 is a conventional active matrix liquid crystal drive circuit diagram.

12 is a circuit diagram of the liquid crystal display panel of FIG.

FIG. 13 is a time chart showing the operation of the circuit of FIG.

FIG. 14 is a diagram showing a main part of another conventional active matrix liquid crystal drive circuit.

FIG. 15 is a diagram showing the transmittance of a liquid crystal pixel with respect to a drive voltage.

[Explanation of symbols]

10 liquid crystal display panel 20A to 20C data driver 21 shift register 22 selector 23, 24 switch control circuit 30 scan driver 31 to 34 buffer gate 35 shift register 40A to 40C control circuit 50 AC conversion / amplification circuit SHA, SHB, SH11 to SH14, SH21-SH
24 Sample and hold circuit OP, OP11 to OP14, OP21 to OP24 Voltage follower E Constant voltage source

Claims (4)

[Claims] 1. In an active matrix liquid crystal driving method for applying an output potential of a sample hold circuit (SHA) to a data line (X) of a liquid crystal display panel to perform multi-gradation display, the sample hold circuit comprises a sampling switch (SA). ) Is turned on for a predetermined time and the capacitor (C
After sampling the input potential VI at one end of 1), the potential at one end of the capacitor is output via a voltage follower (OP), and a constant potential VR is applied to the input end of the voltage follower to apply a constant potential VR to the voltage follower. The output potential VR + VOFF is stored in the other end of the capacitor, the sampling switch is turned on for a predetermined time in this state to store the input potential VI in one end of the capacitor, and the constant potential VR is stored in the other end of the capacitor. By applying the floating potential at one end of the capacitor to VI-VO
An active matrix liquid crystal driving method, wherein FF is used, and one end potential VI-VOFF of the capacitor is applied to the input end of the voltage follower to set the output potential of the voltage follower as VI. 2. A data line (X) of a liquid crystal display panel.
In addition, in the active matrix liquid crystal drive circuit for applying the output voltage of the sample hold circuit (SHA) controlled by the switch control circuit to perform multi-gradation display, one end of the sample hold circuit is an input end of the sample hold circuit. A first switch element (SA), a second switch element (SB) having one end connected to the other end of the first switch element, an input end connected to the other end of the second switch element, and an output end A voltage follower (OP) which is an output end of the sample hold circuit, a third switch element (SC) whose one end is connected to an input end of the voltage follower, and one end which is connected to the other end of the third switch element. A fourth switch element (SD) which is connected and to which a constant potential VR is applied, and one end of which is connected to the other end of the fourth switch element and the other end of which is the output end of the voltage follower A connection has been fifth switching element (SE), one end and the other end is connected to the other end of the first switching element is connected to the other end of the fourth switching element capacitor (C1)
And the switch control circuit turns off the first, second and fourth switch elements and turns on the third and fifth switch elements to set the potential at the other end of the capacitor to VR + VOFF, In this state, the first switch element is turned on for a predetermined time to set the potential at one end of the capacitor to VI, then the third and fifth switch elements are turned off, and the second and fourth switch elements are turned on. The potentials at the input end and the output end of the voltage follower are set to VI-VOFF and VI, respectively, and the active matrix liquid crystal drive circuit. 3. An active matrix liquid crystal driving method for applying an output potential of a sample hold circuit (SHB) to a data line (X) of a liquid crystal display panel to perform multi-gradation display, wherein the sample hold circuit comprises a sampling switch (SA). ) Is turned on for a predetermined time to sample the input potential VI at one end of the first capacitor (C1) and then the potential at one end of the first capacitor (C1) is set to the voltage follower (O).
P), the other end of the first capacitor and the one end of the second capacitor (C2) are both set to the second constant potential VR2, and the first constant potential VR1 is applied to the input end of the voltage follower. The output potential VR1 + VOFF of the voltage follower is stored in one end of the second capacitor, and in this state, the sampling switch is turned on for a predetermined time to store the input potential VI in one end of the first capacitor. The other end of the second capacitor and one end of the second capacitor are set to the floating state of the same potential, and the first constant potential VR1 is applied to the other end of the second capacitor to set the floating potential of one end of the first capacitor to VI-VOFF. , The one end potential VI-VOFF of the first capacitor is applied to the input end of the voltage follower to set the output potential of the voltage follower to VI. Active matrix liquid crystal driving method comprising and. 4. A data line (X) of a liquid crystal display panel.
In addition, in the active matrix liquid crystal drive circuit for applying the output voltage of the sample hold circuit (SHB) controlled by the switch control circuit to perform multi-gradation display, one end of the sample hold circuit is an input end of the sample hold circuit. A first switch element (SA), a second switch element (SB) having one end connected to the other end of the first switch element, an input end connected to the other end of the second switch element, and an output end A voltage follower (OP) which is an output end of the sample hold circuit, a third switch element (SC) whose one end is connected to an input end of the voltage follower, and one end which is connected to the other end of the third switch element. A fourth switch element (SD) which is connected and to which the first constant potential VR1 is applied, one end of which is connected to the other end of the fourth switch element and the other end of which is the output of the voltage follower. A fifth switch element (SE) connected to the end, a first capacitor (C1) having one end connected to the other end of the first switch element, and one end connected to the other end of the first capacitor Is the fourth
The second capacitor (C
2), one end of which is connected to the other end of the first capacitor and the other end of which is the second
A sixth switch element (SF) to which a constant potential VR2 is applied, and the switch control circuit turns off the first, second and fourth switch elements and outputs the third, fifth and sixth switch elements. The switch element is turned on to set the potential of the other end of the second capacitor to VR1 +.
VOFF, and in this state, the first switch element is turned on for a predetermined time to set the potential at one end of the first capacitor to VI, and then the third, fifth and sixth switch elements are turned off and the second and The fourth switch element is turned on to set the potentials at the input end and the output end of the voltage follower to VI-
An active matrix liquid crystal drive circuit, characterized in that VOFF and VI are set.