JPH05283540A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05283540A JPH05283540A JP4160292A JP4160292A JPH05283540A JP H05283540 A JPH05283540 A JP H05283540A JP 4160292 A JP4160292 A JP 4160292A JP 4160292 A JP4160292 A JP 4160292A JP H05283540 A JPH05283540 A JP H05283540A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- wiring conductor
- semiconductor device
- conductor film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000004020 conductor Substances 0.000 claims abstract description 46
- 230000001681 protective effect Effects 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000011347 resin Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract 5
- 238000005336 cracking Methods 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、樹脂封止型の半導体装
置に利用され、特に、コーナー隣接領域に配置される配
線用導体膜の耐応力性を向上させた構造を有する半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of resin encapsulation type, and more particularly to a semiconductor device having a structure in which stress resistance of a conductor film for wiring arranged in a corner adjacent region is improved.
【0002】[0002]
【従来の技術】図5は従来のこの種の半導体装置の一例
の要部を示す平面図、および図6のそのC−C′拡大断
面図である。2. Description of the Related Art FIG. 5 is a plan view showing an essential part of an example of a conventional semiconductor device of this type, and an enlarged sectional view taken along line CC 'of FIG.
【0003】半導体基板10の一主面に半導体素子領域
11が形成され、第一層間絶縁膜21を介してアルミニ
ウムなどの半導体装置の内部配線用導体膜12および半
導体装置周辺部の第一配線用導体膜13を形成し、次に
第二層間絶縁膜22を介してアルミニウムなどの半導体
周辺部の第二配線用導体膜14をボンディングパッド部
18を含めて形成し、リンシリケートガラスおよびシリ
コンナイトライド膜などの保護用絶縁膜23で覆った
後、ボンディングパッド部18のみをエッチングして露
出させる構造となっていた。A semiconductor element region 11 is formed on one main surface of a semiconductor substrate 10, and a conductor film 12 for internal wiring of a semiconductor device such as aluminum and a first wiring in the peripheral portion of the semiconductor device are formed via a first interlayer insulating film 21. Forming a conductive film 13 for wiring, and then forming a conductive film 14 for a second wiring in the peripheral portion of the semiconductor such as aluminum, including a bonding pad part 18, with a second interlayer insulating film 22 interposed therebetween. After being covered with a protective insulating film 23 such as a ride film, only the bonding pad portion 18 is etched and exposed.
【0004】そして、最後に樹脂封止されて半導体装置
とされていた。Finally, the semiconductor device is resin-sealed.
【0005】[0005]
【発明が解決しようとする課題】このような従来の半導
体装置は、例えば、+150℃〜−65℃の温度サイク
ル試験を行った場合、樹脂の伸び縮みにより応力が発生
し、図5中の矢印に示すように半導体装置周辺部の第二
配線用導体膜14に大きな応力が加わる。In such a conventional semiconductor device, for example, when a temperature cycle test of + 150 ° C. to −65 ° C. is performed, stress is generated due to expansion and contraction of the resin, and an arrow in FIG. As shown in, a large stress is applied to the second wiring conductor film 14 around the semiconductor device.
【0006】このとき、近年における大チップの樹脂封
止化に伴い、チップ寸法が15mm□を越えるような大
チップを樹脂封止し、前記温度サイクル試験を行った場
合、前述した応力により半導体装置周辺部の第二配線用
導体膜14を囲む保護用絶縁膜23にクラックが発生し
たり、さらには図7のアルミスライドのモデル図に示す
ように、半導体装置のコーナー領域24よりコーナー隣
接領域25において配線の移動幅が大きいという傾向を
有し、コーナー隣接領域25において半導体装置周辺部
の保護用絶縁膜23のクラックの発生、および第二配線
用導体膜14のずれ(移動)26が発生し、配線の信頼
性を低下させる欠点があった。At this time, with the recent resin encapsulation of large chips, when a large chip having a chip size of more than 15 mm □ is resin-encapsulated and the temperature cycle test is performed, the semiconductor device is subjected to the above-mentioned stress. A crack is generated in the protective insulating film 23 surrounding the second wiring conductor film 14 in the peripheral portion, and further, as shown in the model diagram of the aluminum slide in FIG. Has a tendency that the movement width of the wiring is large, cracks in the protective insulating film 23 in the peripheral portion of the semiconductor device in the corner adjacent region 25, and displacement (movement) 26 of the second wiring conductor film 14 occur. However, there is a drawback that reduces the reliability of the wiring.
【0007】本発明の目的は、前記の欠点を除去するこ
とにより、封止樹脂の応力による保護用絶縁膜のクラッ
ク、および配線用導体膜のずれの発生を防止した、高信
頼性の半導体装置を提供することにある。An object of the present invention is to achieve a highly reliable semiconductor device which eliminates the above-mentioned drawbacks to prevent cracks in the protective insulating film and shifts in the wiring conductor film due to the stress of the sealing resin. To provide.
【0008】[0008]
【課題を解決するための手段】本発明は、保護用絶縁膜
と、この保護用絶縁膜の下面に接して設けられた配線用
導体膜と、この配線用導体膜の下面に接して設けられた
層間絶縁膜とを有する半導体装置において、前記半導体
装置の少なくともコーナー領域に隣接する領域に設けら
れた前記保護用絶縁膜、前記配線用導体膜および前記層
間絶縁膜はそれらの上面に設けられた凹凸部を有するこ
とを特徴とする。According to the present invention, there is provided a protective insulating film, a wiring conductor film provided in contact with the lower surface of the protective insulating film, and a lower surface of the wiring conductor film. In a semiconductor device having an interlayer insulating film, the protective insulating film, the wiring conductor film, and the interlayer insulating film provided in a region adjacent to at least a corner region of the semiconductor device are provided on their upper surfaces. It is characterized by having an uneven portion.
【0009】また、本発明は、前記凹凸部は前記層間絶
縁膜の上面に設けられた凹部にならうものであることが
好ましい。Further, according to the present invention, it is preferable that the concave-convex portion follows a concave portion provided on the upper surface of the interlayer insulating film.
【0010】[0010]
【作用】本発明の半導体装置は、半導体装置の各辺に沿
ってその周辺部に配置される配線用導体膜のコーナー領
域より各辺の中心方向にのびかつコーナー領域に隣接す
る領域に配置された、前記配線用導体膜下の層間絶縁膜
に凹部として例えばスリットまたは下まで貫通しない複
数個のウェルを設け、配線用導体膜および保護用絶縁膜
に凹凸形状を持たせた構造を有している。According to the semiconductor device of the present invention, the semiconductor device is arranged along each side of the semiconductor device in a region extending from the corner region of the conductor film for wiring arranged in the periphery thereof toward the center of each side and adjacent to the corner region. In addition, the interlayer insulating film below the wiring conductor film has a structure in which, for example, slits or a plurality of wells that do not penetrate to the bottom are provided as recesses, and the wiring conductor film and the protective insulating film have uneven shapes. There is.
【0011】従って、封止樹脂による応力を、従来は前
記配線用導体膜エッジの凸部のみで受けていたのに対
し、複数の凸部で分散して受けることになり、耐応力性
が向上し、保護用絶縁膜のクラックの発生、ならびにコ
ーナー隣接領域における前記配線用導体膜のずれの発生
を防止することが可能となる。Therefore, the stress due to the sealing resin is conventionally received only by the convex portion of the wiring conductor film edge, but it is received by the plurality of convex portions in a dispersed manner, and the stress resistance is improved. However, it is possible to prevent the generation of cracks in the protective insulating film and the displacement of the wiring conductor film in the area adjacent to the corner.
【0012】[0012]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0013】図1は本発明の第一実施例の要部を示す平
面図、および図2はそのA−A′拡大断面図である。FIG. 1 is a plan view showing an essential part of a first embodiment of the present invention, and FIG. 2 is an enlarged sectional view taken along the line AA '.
【0014】本第一実施例は、保護用絶縁膜23と、こ
の保護用絶縁膜23の下面に接して設けられた第二配線
用導体膜14と、この第二配線用導体膜14の下面に接
して設けられた第二層間絶縁膜22と、第一配線用導体
膜13と、第一層間絶縁膜21、フィールド酸化膜20
と、半導体基板10とを有する半導体装置において、本
発明の特徴とするところの、前記半導体装置のコーナー
領域24に隣接するコーナー隣接領域25を含んで設け
られた、保護用絶縁膜23、第二配線用導体膜14、お
よび第二層間絶縁膜22は、第二層間絶縁膜22の上面
に設けられた凹部としての複数のスリット27にならう
複数の凹凸部を有している。In the first embodiment, the protective insulating film 23, the second wiring conductor film 14 provided in contact with the lower surface of the protective insulating film 23, and the lower surface of the second wiring conductor film 14 are provided. Second interlayer insulating film 22, first wiring conductor film 13, first interlayer insulating film 21, field oxide film 20
And a semiconductor substrate 10. In a semiconductor device having a semiconductor substrate 10, a protective insulating film 23, which is provided as a feature of the present invention, including a corner adjacent region 25 adjacent to the corner region 24 of the semiconductor device, The wiring conductor film 14 and the second interlayer insulating film 22 have a plurality of concave and convex portions that follow the slits 27 as concave portions provided on the upper surface of the second interlayer insulating film 22.
【0015】次に、本第一実施例の製造方法の概要につ
いて説明する。Next, an outline of the manufacturing method of the first embodiment will be described.
【0016】まず、半導体基板10の一主面に、例えば
膜厚1.0μmのフィールド酸化膜20および半導体素
子領域11を形成し、次に、例えば膜厚1.0μmのリ
ンシリケートガラス膜などの第一層間絶縁膜21を形成
し、次に、例えば膜厚0.5μmのアルミニウムなどの
内部配線用導体膜12および半導体装置周辺部の第一配
線用導体膜13を形成する。First, a field oxide film 20 and a semiconductor element region 11 having a film thickness of 1.0 μm, for example, are formed on one main surface of the semiconductor substrate 10, and then a phosphosilicate glass film having a film thickness of 1.0 μm, for example. The first interlayer insulating film 21 is formed, and then the conductor film 12 for internal wiring such as aluminum having a film thickness of 0.5 μm and the conductor film 13 for first wiring around the semiconductor device are formed.
【0017】次に、例えば膜厚1.2μmのプラズマ酸
化膜などの第二層間絶縁膜22を成長した後、スルーホ
ール16を形成する。次に、第二層間絶縁膜22にスリ
ット27を形成する。Next, after growing a second interlayer insulating film 22 such as a plasma oxide film having a thickness of 1.2 μm, a through hole 16 is formed. Next, the slit 27 is formed in the second interlayer insulating film 22.
【0018】この第二層間絶縁膜22へのスリット27
の形成にあたっては、スルーホール16形成後、後に形
成する半導体装置周辺部の第二配線用導体膜14の部分
に第二層間絶縁膜22のスリット27形成のためのホト
レジストパターンを形成し、次に、リアクティブイオン
エッチなどを用いて0.5〜0.6μmのエッチング除
去を行い、残膜厚が0.7〜0.6μmになるように形
成する。次に、ホトレジストパターンを除去し得られる
ものである。A slit 27 is formed in the second interlayer insulating film 22.
In forming the through holes 16, after forming the through holes 16, a photoresist pattern for forming the slits 27 of the second interlayer insulating film 22 is formed in a portion of the second wiring conductor film 14 in the peripheral portion of the semiconductor device which will be formed later. Etching removal is performed by reactive ion etching to a thickness of 0.5 to 0.6 μm to form a residual film thickness of 0.7 to 0.6 μm. Then, the photoresist pattern is removed.
【0019】次に、例えば膜厚1.0μmのアルミニウ
ムなどの半導体装置周辺部の第二配線用導体膜14を形
成し、例えば膜厚1.0μmのリンシリケートガラスお
よびシリコンナイトライド膜などの保護用絶縁膜23で
覆った後、ボンディングパッド部18のみをエッチング
して露出させることにより所望の構造が得られる。Next, a conductor film 14 for the second wiring such as aluminum having a film thickness of 1.0 μm in the peripheral portion of the semiconductor device is formed to protect the phosphosilicate glass and the silicon nitride film having a film thickness of 1.0 μm. After covering with the insulating film for use 23, only the bonding pad portion 18 is etched and exposed to obtain a desired structure.
【0020】近年、大チップのモールド化が進み、図7
のアルミスライドのモデル図が示すように半導体装置の
コーナー隣接領域25において配線用導体膜のずれが顕
著に発生し、その対策が必要となってきた。そこで、本
実施例のように、半導体装置のコーナー隣接領域25の
第二配線用導体膜14の下の第二層間絶縁膜22に、例
えばスリット幅5μm、スリット間隔10μmの層間絶
縁膜のスリットを複数設け、コーナー領域隣接部25の
第二配線用導体膜14および保護用絶縁膜23に複数の
凹凸形状を持たせることにより、従来、樹脂による応力
を半導体装置周辺部の第二配線用導体膜14のエッジの
凸部のみで受けていたものを、前記複数の凸部に分散し
て受けることにより耐応力性が向上し、保護用絶縁膜2
3のクラックの発生を防止することができ、半導体装置
のコーナー隣接領域25の第二配線用導体膜14のずれ
26の発生も防止できる。In recent years, molding of large chips has progressed, and FIG.
As shown in the aluminum slide model diagram, the wiring conductor film is significantly displaced in the corner adjacent region 25 of the semiconductor device, and a countermeasure against it has been required. Therefore, as in this embodiment, for example, a slit of an interlayer insulating film having a slit width of 5 μm and a slit interval of 10 μm is formed in the second interlayer insulating film 22 below the second wiring conductor film 14 in the corner adjacent region 25 of the semiconductor device. By providing a plurality of concave and convex shapes in the second wiring conductor film 14 and the protective insulating film 23 in the corner area adjacent portion 25, the stress due to the resin is conventionally applied to the second wiring conductor film in the peripheral portion of the semiconductor device. What is received only by the convex portions of the edges of 14 is dispersed and received by the plural convex portions, so that the stress resistance is improved and the protective insulating film 2
It is possible to prevent the occurrence of cracks in No. 3 and to prevent the occurrence of misalignment 26 of the second wiring conductor film 14 in the corner adjacent region 25 of the semiconductor device.
【0021】以上、2層配線構造の半導体装置のコーナ
ー領域隣接部を例にとり説明したが、単層品および3層
品以上でも前述した同様の問題点が発生し、半導体装置
のコーナー隣接領域に配置される保護用絶縁膜、最上層
の配線用導体膜および前記最上層の配線用導体膜下の層
間絶縁膜にも本発明を同様に適用することができる。The above description has been made with reference to the corner area adjoining portion of the semiconductor device having the two-layer wiring structure. The present invention can be similarly applied to the protective insulating film, the uppermost wiring conductor film, and the interlayer insulating film below the uppermost wiring conductor film that are arranged.
【0022】図3は本発明の第二実施例の要部を示す平
面図、および図4はそのB−B′拡大断面図である。FIG. 3 is a plan view showing an essential part of the second embodiment of the present invention, and FIG. 4 is an enlarged sectional view taken along the line BB '.
【0023】本第二実施例は、図1および図2に示した
第一実施例において、本発明の特徴とするところの、凹
部としてスリットの代わりに、例えば10μm×10μ
mの大きさの層間絶縁膜の下まで貫通しないウエル28
を複数個設けたものであり、スリット同様の耐応力性が
得られる。The second embodiment is similar to the first embodiment shown in FIGS. 1 and 2 in that instead of slits, which are the features of the present invention, instead of slits, for example, 10 μm × 10 μm.
Well 28 that does not penetrate below the interlayer insulating film of size m
Since a plurality of slits are provided, the same stress resistance as the slit can be obtained.
【0024】[0024]
【発明の効果】以上説明したように、本発明は、半導体
基板上周辺部のコーナー隣接領域に絶縁膜を介して形成
される配線用導体膜下の絶縁膜に、凹部として例えばス
リットまたは下まで貫通しない複数個のウエルを設け
て、凹凸の形状を配線用導体膜および保護用絶縁膜に設
けることにより、樹脂による応力をその複数の凸部に分
散して受けることで耐応力性が向上し、配線用導体膜を
とりまく保護用絶縁膜にクラックの発生および配線用導
体膜のずれの発生が防止でき、配線の信頼性を著しく向
上できる優れた効果がある。As described above, according to the present invention, the insulating film below the conductor film for wiring formed in the corner adjacent region of the peripheral portion of the semiconductor substrate via the insulating film is used as a recess, for example, as a slit or to the bottom. By providing a plurality of wells that do not penetrate and providing uneven shapes on the wiring conductor film and the protective insulating film, the stress due to the resin is dispersed and received by the plurality of protrusions, which improves the stress resistance. Further, it is possible to prevent the occurrence of cracks in the protective insulating film surrounding the conductor film for wiring and the shift of the conductor film for wiring, and it is possible to remarkably improve the reliability of the wiring.
【図1】本発明の第一実施例の要部を示す平面図。FIG. 1 is a plan view showing a main part of a first embodiment of the present invention.
【図2】図1のA−A′拡大断面図。FIG. 2 is an enlarged sectional view taken along the line AA ′ of FIG.
【図3】本発明の第二実施例の要部を示す平面図。FIG. 3 is a plan view showing a main part of a second embodiment of the present invention.
【図4】図3のB−B′拡大断面図。FIG. 4 is an enlarged cross-sectional view taken along the line BB ′ of FIG.
【図5】従来例の要部を示す平面図。FIG. 5 is a plan view showing a main part of a conventional example.
【図6】図5のC−C′拡大断面図。6 is an enlarged sectional view taken along the line CC ′ of FIG.
【図7】アルミスライドのモデル図。FIG. 7 is a model diagram of an aluminum slide.
10 半導体基板 11 半導体素子領域 12 内部配線用導体膜 13 第一配線用導体膜 14 第二配線用導体膜 16 スルーホール 17 コンタクトホール 18 ボンディングパッド部 20 フィールド酸化膜 21 第一層間絶縁膜 22 第二層間絶縁膜 23 保護用絶縁膜 24 コーナー領域 25 コーナー隣接領域 26 ずれ 27 スリット 28 ウェル 10 semiconductor substrate 11 semiconductor element region 12 conductor film for internal wiring 13 conductor film for first wiring 14 conductor film for second wiring 16 through hole 17 contact hole 18 bonding pad portion 20 field oxide film 21 first interlayer insulating film 22 Two-layer insulating film 23 Protective insulating film 24 Corner region 25 Corner adjacent region 26 Deviation 27 Slit 28 Well
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/31 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/31
Claims (2)
面に接して設けられた配線用導体膜と、この配線用導体
膜の下面に接して設けられた層間絶縁膜とを有する半導
体装置において、 前記半導体装置の少なくともコーナー領域に隣接する領
域に設けられた前記保護用絶縁膜、前記配線用導体膜お
よび前記層間絶縁膜はそれらの上面に設けられた凹凸部
を有することを特徴とする半導体装置。1. A semiconductor comprising a protective insulating film, a wiring conductor film provided in contact with the lower surface of the protective insulating film, and an interlayer insulating film provided in contact with the lower surface of the wiring conductor film. In the device, the protective insulating film, the wiring conductor film, and the interlayer insulating film provided in at least a region adjacent to a corner region of the semiconductor device have uneven portions provided on their upper surfaces. Semiconductor device.
けられた凹部にならうものである請求項1記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the uneven portion follows a concave portion provided on the upper surface of the interlayer insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4160292A JPH05283540A (en) | 1992-02-27 | 1992-02-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4160292A JPH05283540A (en) | 1992-02-27 | 1992-02-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05283540A true JPH05283540A (en) | 1993-10-29 |
Family
ID=12612930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4160292A Pending JPH05283540A (en) | 1992-02-27 | 1992-02-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05283540A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009027139A (en) * | 2007-04-30 | 2009-02-05 | Infineon Technologies Ag | Fixing structure and mating structure |
US8786092B2 (en) | 2005-06-17 | 2014-07-22 | Rohm Co., Ltd. | Semiconductor integrated circuit device |
US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
-
1992
- 1992-02-27 JP JP4160292A patent/JPH05283540A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8786092B2 (en) | 2005-06-17 | 2014-07-22 | Rohm Co., Ltd. | Semiconductor integrated circuit device |
US9041160B2 (en) | 2005-06-17 | 2015-05-26 | Rohm Co., Ltd. | Semiconductor integrated circuit device |
JP2009027139A (en) * | 2007-04-30 | 2009-02-05 | Infineon Technologies Ag | Fixing structure and mating structure |
JP2012119711A (en) * | 2007-04-30 | 2012-06-21 | Infineon Technologies Ag | Anchoring structure and fitting structure |
US9076821B2 (en) | 2007-04-30 | 2015-07-07 | Infineon Technologies Ag | Anchoring structure and intermeshing structure |
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