JP3038904B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a test element group (TEG) pattern on a scribe area in a semiconductor integrated circuit.

[Prior Art] In a conventional semiconductor integrated circuit, an opening of an interlayer insulating layer provided for connecting a plurality of metal wiring layers of a pad section of a TEG is almost the same size as a pad opening, Therefore, it overlapped the slit opening of the metal wiring layer.

1 and 2 show a conventional example. FIG. 1 is a plan view, and FIG. 2 is a sectional view taken along line AA in FIG. Reference numeral 101 denotes a first metal wiring layer, and reference numeral 102 denotes a second metal wiring layer. Reference numeral 103 denotes an opening edge of the final protective film, and reference numeral 104 denotes an interlayer insulating layer between the first metal wiring layer (101) and the second metal wiring layer (102). 105
Denotes a slit opening provided in the metal wiring layer. The opening (104) of the interlayer insulating layer is the opening (103) of the final protective film.
As a result, the slit portion of the metal wiring layer overlaps with the opening of the interlayer insulating layer.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, since the openings of the interlayer insulating layer between the metal wiring layers are almost the same size as the pad openings, the slit openings of a plurality of metal wiring layers are formed. When they are overlapped, the hole becomes a deep hole reaching up to near the substrate surface, and there are problems such as a short circuit with the substrate at the time of opening the pad hole or abnormal formation of a bump portion due to resist destruction due to expansion of residual air at the time of bump formation. Therefore, the present invention solves such a problem, and an object of the present invention is to provide a pattern capable of stably forming a TEG arranged on a scribe without affecting the chip size and the number of data creation steps. To provide shape.

[Means for Solving the Problems] The integrated circuit of the present invention is arranged on a scribe area.
The slit opening of the metal wiring layer of the pad portion of the TEG and the opening of the interlayer insulating layer provided for connecting another metal wiring layer located above or below the metal wiring layer do not overlap. And

[Operation] According to the above configuration of the present invention, even when the slit openings of the plurality of metal wiring layers of the pad portion overlap, the openings of the interlayer insulating layer do not overlap with the slits of the metal wiring layer. There is no deep hole reaching from the part to the vicinity of the substrate surface, and it is possible to suppress the occurrence of short-circuit with the substrate when opening the pad hole or the abnormal formation of the bump part due to the resist breakdown due to the expansion of the residual air when forming the bump. It becomes possible.

[Examples] Hereinafter, the present invention will be described based on examples.

3 and 4 show an embodiment of the present invention. FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line AA in FIG. Reference numeral 101 denotes a first metal wiring layer, and reference numeral 102 denotes a second metal wiring layer. Reference numeral 103 denotes an opening edge of the final protective film, and reference numeral 104 denotes an interlayer insulating layer between the first metal wiring layer (101) and the second metal wiring layer (102). 105 is a slit opening provided in the metal wiring layer. The opening (104) of the interlayer insulating layer is completely displaced from the slit opening (105) of the metal wiring layer.

[Effects of the Invention] As described above, according to the invention, since the slit openings of the plurality of metal wiring layers provided in the pad portion do not overlap with the openings of the interlayer insulating layer between the metal wiring layers, the upper layer portion There is no deep hole reaching near the substrate surface, and it is possible to suppress the occurrence of short-circuit with the substrate at the time of opening the pad hole or the formation of abnormal bumps due to resist breakdown due to expansion of residual air at the time of bump formation. Become.

[Brief description of the drawings]

1 and 2 are views showing examples of the shape of a pad portion of a conventional semiconductor integrated circuit. FIG. 3 and FIG. 4 are diagrams showing examples of the shape of a pad portion of a semiconductor integrated circuit according to the present invention. 101 first metal wiring layer 102 second metal wiring layer 103 opening of final protective film 104 first metal wiring layer (101) and second metal wiring layer Interlayer insulating layer 105 of the metal wiring layer (102) ... Slit opening provided in the metal wiring layer

Claims (1)

(57) [Claims] 1. A scribe area provided for separating a semiconductor integrated circuit into respective chips, wherein a TEG disposed on the scribe area is a metal of a pad part for transmitting and receiving signals to and from the outside. In a semiconductor integrated circuit having a slit opening in a wiring layer, and the metal wiring layer of the pad portion is composed of a plurality of layers, the metal wiring layer of the pad portion of the TEG disposed on the scribe region is A semiconductor integrated circuit, wherein an opening of an interlayer insulating layer provided for connecting a slit opening to another metal wiring layer located above or below the metal wiring layer does not overlap.