JPH05283471A - Semiconductor device and base material forming part of the semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device capable of connecting electrodes of semiconductor elements and connecting semiconductor elements in the same package. [Structure] The electrodes of two IC chips 12a and 12b are bonded to a lead-out lead 16a and a lead-out lead 16b ₅ patterned on a film 14. Further, the wirings of the routing leads 16b ₁ and 16b ₄ , 16b ₂ and 16b _{3 which} cannot be connected by the wiring pattern of the leads are the pads 24b ₁ and 24b ₄ formed on the respective routing leads,
Bonding wires 18, 1 between 24b ₂ and 24b ₃
Use 8 to make a jumping connection. After these connections,
The IC chips 12a and 12b, the leads 16 and the bonding wires 18 are sealed with resin in the entire area surrounded by the area 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to semiconductor devices such as I
The present invention relates to a semiconductor device in which a C (integrated circuit) chip is mounted on a film substrate and a base material which is a part of a constituent material of the semiconductor device.

[0002]

2. Description of the Related Art TA is one of IC chip mounting technologies.
There is B (Tape Automated Bonding) technology. The TAB technology is characterized in that it can form leads with a large number of pins and a narrow pitch, as compared with other mounting technologies, and can perform high-speed automatic bonding face-up. For this reason,
In recent years, TAB technology has attracted particular attention.

The TAB tape has a structure in which one or a plurality of IC chips can be mounted on each package of a film carrier in which leads (conductors) are formed on a film made of a synthetic resin such as polyimide. The leads are those that are pulled out of the package to connect to the mounting board,
Some are routed inside a package to make connections within one IC chip or between multiple IC chips. To join these leads and the IC chip,
Usually, there are a transfer bump method in which a bump is transferred to the tip of a lead of a film carrier in advance, and then the lead and an electrode of an IC chip are pressed and heated to be bonded, or a wafer bump method in which a bump is formed in advance on a wafer. is there.

[0004]

By the way, a plurality of I's are provided.
An example in which the C chip is mounted on one package is described in JP-A-59-54252. According to the description of this publication, in order to store two IC chips in one package, wiring is provided on the TAB tape in advance. However, an IC chip to be housed in such a package needs to be designed in advance so that wiring is not performed between both chips. Further, when the wiring between the IC chips must cross each other, it is impossible to perform the wiring only by using the leads formed on the film carrier. Therefore, in this case, it is considered to form leads on both sides of the film, form through holes at predetermined positions on the film, and electrically connect the leads formed on both sides of the film through the through holes. Be done.

However, this method has a problem in that it is difficult to form through holes in a TAB tape having a large number of pins and a narrow pitch, and the cost increases. Therefore, in the conventional semiconductor device, the cross wiring needs to be performed outside the package. Originally, the purpose of accommodating a plurality of IC chips in the same package is to save space in an electronic circuit system. However, when the cross wiring is performed outside the package, an extra space occupied by the cross wiring portion is generated. Therefore, as the number of cross wiring increases, the space increases, and a plurality of IC chips are accommodated in the same package. The merit to do it decreases. In addition, there is a problem in that the appearance is not good, and further, there is a high possibility that the cross wiring portion will be broken or short-circuited, and the reliability of the equipment using the package will be reduced.

The present invention has been made in view of the above circumstances, and a semiconductor device which can connect electrodes of semiconductor elements and connections between semiconductor elements in the same package, and a semiconductor element forming a part of the semiconductor device. It is intended to provide a base material for mounting the.

[0007]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention is a semiconductor device having a large number of terminals for electrically connecting with the outside; A substrate; a plurality of conducting wires wired on the substrate and electrically connected to each terminal of the semiconductor element; and a jumping wire for wiring between predetermined conducting wires among these conducting wires. ing. Further, the jumping wire includes a surface whose surface is coated with an insulator. Further, a resin layer for sealing the semiconductor element and the jumping wire together is further provided. Further, the substrate further includes a mounting portion for mounting the plurality of semiconductor elements. Further, the conductor wire is formed by metal plating based on copper. Further, the metal plating of the above-mentioned conductor includes gold plating. In addition, the substrate includes a substrate made of polyimide.

Further, in order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a large number of terminals for electrically connecting to the outside; a substrate on which a plurality of these semiconductor devices are mounted. A plurality of conducting wires that are wired on the substrate and are electrically connected to the respective terminals of the semiconductor element; a jumping wire for wiring between predetermined conducting wires among these conducting wires; and the jumping wire and the semiconductor A resin layer for sealing the elements together is included. Further, the jumping wire includes a surface whose surface is coated with an insulator. Further, the above-mentioned conductive wire includes one formed by metal plating based on copper. Further, the metal plating of the above-mentioned conductor includes gold plating. In addition, the substrate includes a substrate made of polyimide.

Further, in order to achieve the above object, a semiconductor device according to the present invention is a semiconductor element having a large number of terminals for electrically connecting to the outside; a substrate on which a plurality of these semiconductor elements are mounted. A plurality of conducting wires which are wired on the substrate and are electrically connected to the respective terminals of the semiconductor element; a jumping wire for wiring between predetermined conducting wires among these conducting wires, the surface of the jumping wire being an insulator And a resin layer for sealing the jumping wire and the semiconductor element together. Further, the above-mentioned conductive wire includes one formed by metal plating based on copper. Further, the metal plating of the above-mentioned conductor includes gold plating. In addition, the substrate includes a substrate made of polyimide.

Further, in order to achieve the above object, the base material according to the present invention is a substrate for mounting a semiconductor element having a large number of terminals for electrically connecting to the outside; wiring on this substrate. A plurality of conducting wires for electronically connecting to the respective terminals of the semiconductor element; and among the conducting wires for connecting jumping wires for wiring between predetermined conducting wires among these conducting wires. The terminal is provided in some of them; Further, the substrate further includes a mounting portion for mounting a plurality of semiconductor elements. Further, the conductor wire is formed by metal plating based on copper. The substrate is made of polyimide.

[0011]

According to the present invention, due to the above-described structure, the connection between the electrodes of one semiconductor element or between the plurality of semiconductor elements in the package of the semiconductor device is not achieved by the conductive wire (lead) formed on the substrate (film carrier). When possible, for example, when wiring crosses, jump wiring (conductive wire) is used to make a three-dimensional connection, so that cross wiring that could not be connected in the same package until now can be connected in the same package. Can be done in.

Further, by covering the surface of the jumping wire with an insulator, it is possible to prevent a short circuit between the jumping wire and the conducting wire and between the jumping wires.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view taken along the line AA in FIG. 1 when an IC chip mounted on a TAB tape is sealed with resin. is there.

The semiconductor device shown in FIG. 1 includes two IC chips 12a and 12b and a resin film 14 made of polyimide.
It is provided with a film carrier (TAB tape) on which leads 16 plated with a metal such as gold, tin, solder or the like are further formed on which a pattern is formed with copper, and a bonding wire 18 covered with an insulator. As the bonding wire 18, the insulating coated wire described in JP-A-02-249245 is used. IC chip 12a,
12b is formed in a substantially square shape, and an electrode 22 is formed on the edge portion of the surface thereof. The film 14 is formed with two device holes 21a and 21b corresponding to the mounting positions of the IC chips 12a and 12b and an outer lead hole (not shown). Device holes 21a, 2
Reference numeral 1b is a mounting portion for mounting the IC chips 12a and 12b, which is an opening. The outer lead holes are IC chips 12a, 12 sealed with resin 26.
It is an opening that serves as a guide when punching out b from the film 14. As the material of the film 14, polyimide having good heat resistance and stretch resistance is used. The region 27 surrounded by the alternate long and short dash line shown in FIG. 1 is a region sealed with the resin 26.

The leads 16 are leads 16a for pulling out from the package for connecting to the mounting board, and I.
It has a lead 16b for routing that is routed within the package to connect the C chips 12a and 12b. One end of each of the leads 16 is formed so as to protrude into either of the device holes 21a and 21b. A pad 24 is provided on the extension of the lead-out lead 16a and a part of the lead-out lead 16b. The pad (not shown in FIG. 1) of the lead 16a for drawing out is a test pad for electrical inspection of the IC chip, while the lead 16a for drawing out is provided.
b ₁ pad 24b ₁ ~24b ₄ of ～16B ₄ is for connecting the bonding wire 18. Both ends of the routing lead 16b ₅ are connected to the IC chips 12a and 12b.

In the semiconductor device of the first embodiment, the lead 16 of the TAB tape and the electrode 2 of the IC chips 12a and 12b are used.
The so-called transfer bump method is used to join the two
After transferring bumps (not shown) to the tips of the leads 16a and 16b of the film carrier, the leads and the electrodes 22 of the IC chips 12a and 12b are pressed and heated to bond them. In the TAB tape of the first embodiment, I
Due to the wiring design of the C chip, the routing leads 16b ₁ and 16b
₄ , it is necessary to connect between 16b ₂ and 16b ₃ . Therefore, the pads 24b ₁ and 24b ₄ , the pad 24
Bonding wires 18 and 18 three-dimensionally connect b ₂ and the pad 24 b ₃ , respectively.

FIG. 2 is a sectional view taken along line AA of FIG. 1 showing a state in which the IC chips 12a and 12b bonded to the TAB tape shown in FIG. 1 are sealed with resin 26 over the area 27. By sealing with a resin, high reliability can be maintained without impairing the electrical characteristics of the manufactured semiconductor device.

As described above, in the semiconductor device of this embodiment,
As described above, attach the two IC chips to the film carrier (T
AB tape) 14 mounted on each IC chip 12a, 12
In the package of the cross wiring, the connection between b is mainly performed by using the patterned lead on the film carrier, and the cross wiring which cannot be connected by the lead wiring pattern is connected by the bonding wire. Connection is possible. Further, since the semiconductor device of the present embodiment is connected by the bonding wire within the area of the conventional sealing resin, the shape of the semiconductor device is increased even if the bonding wire is used for three-dimensional connection. There is no. Therefore, space saving can be achieved as compared with the conventional semiconductor device. Further, since the bonding wire 18 is a bonding wire coated with an insulator described in Japanese Patent Laid-Open No. 02-249245, even if the bonding wire 18 and the lead 16 and the bonding wires 18 come into contact with each other, a short circuit occurs. That's not it.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a schematic plan view of a semiconductor device which is a second embodiment of the present invention. In the second embodiment, components having the same functions as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor device shown in FIG. 3 is different from that of the first embodiment in that when the IC chips 12a and 12b are connected, the pad 24b _{1 of the} lead 16b ₁ for routing and the IC
That is, the bonding wire 18 is directly connected to the electrode 22b of the chip 12b. Also in the semiconductor device of the second embodiment, the same effect as in the case of the first embodiment can be obtained.

A third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic plan view of a semiconductor device which is a third embodiment of the present invention. Also in the third embodiment, the above first
Components having the same functions as those of the embodiments are designated by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor device shown in FIG. 4 is an example in which one IC chip 12 is housed in a package and cross wiring is generated. Electrodes 22c ₁ of the pad 24c and the IC chip 12 of the lead 16, the electrode 22c of the IC chip 12 ₂ and 22c _3, pad 24c ₂ of the lead 16 and 2
4c ₃ is connected three-dimensionally with a bonding wire 18. Also in the semiconductor device of the third embodiment, the same effect as in the first embodiment can be obtained.

In each of the above embodiments, the case where one or two IC chips 12 are housed in the same package of the film carrier 14 has been described, but the present invention is not limited to this, and the film carrier is not limited to this. Three or more IC chips may be housed in the same 14 packages.

Further, FIG. 5 shows a plan view of a TAB tape used in the semiconductor device of the fourth embodiment. Also in FIG. 5, those having the same functions as those of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The pattern of FIG. 5 is one of the patterns of the TAB tape actually used. Pads 24a of the lead 16a for pulling out, which are not shown in the other figures in this figure, are also arranged in two corners in four corners. Further, inside the resin sealing area 27 of the TAB tape, punched portions 32 are formed at the four corners.
It is configured so that the resin smoothly flows on both sides of the TAB tape 14.

Outer lead holes 30 are provided at the four corners of the TAB pattern, and the IC chips 12a, 12
The semiconductor device after b is resin-sealed in the region 27 is
It serves as a mark when punching from the AB tape 14. The lead pattern on the TAB tape 14 is more complicated than the other drawings, but is basically the same. However, in FIG. 5, the lead 16a for drawing and the lead 16 for drawing
In addition to b, put the bypass lead 16c in a predetermined place,
The jumping wiring by the bonding wire 18 is configured to be more efficient.

[0026]

As described above, according to the present invention, by virtue of the above-mentioned structure, the connection between the electrodes of one semiconductor element or the connection between a plurality of semiconductor elements in the package of the semiconductor device can be achieved by the substrate (film). If it is not possible with the lead wire formed on the carrier, for example, if the wiring crosses, it is possible to use a jumping wire (conductive wire) to make a three-dimensional connection, thus making it possible to use the same package within the same package. It is possible to provide a semiconductor device capable of performing cross wiring which could not be connected in the same package in the same package, and a base material for mounting a semiconductor element which is a part of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a semiconductor device that is a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view taken along the line AA when the IC chip of the semiconductor device according to the first embodiment of the present invention is sealed with resin.

FIG. 3 is a schematic plan view of a semiconductor device which is a second embodiment of the present invention.

FIG. 4 is a schematic plan view of a semiconductor device which is a third embodiment of the present invention.

FIG. 5 is a plan view of a film carrier used in a semiconductor device according to a fourth embodiment of the present invention.

[Explanation of symbols]

 12 IC chip 14 film 16 lead 16a lead-out lead 16b lead-out lead 16c bypass lead 18 bonding wire 21 device hole 22 electrode 24 pad 26 sealing resin 27 area

Claims (20)

[Claims] 1. A semiconductor element having a large number of terminals for electrically connecting to the outside, a substrate on which the semiconductor element is mounted, and wiring on the substrate, and each terminal of the semiconductor element and an electronic device. A semiconductor device including: a plurality of conductive wires that are electrically connected to each other; and a jumping wire for wiring between predetermined conductive wires among these conductive wires. 2. The semiconductor device according to claim 1, wherein the jumping wire includes a surface of which is coated with an insulator. 3. The semiconductor device according to claim 1, further comprising a resin layer for sealing the semiconductor element and the jumping wire together. 4. The semiconductor device according to claim 1, wherein the substrate further comprises a mounting portion for mounting a plurality of the semiconductor elements. 5. The semiconductor device according to claim 1, wherein the conductive wire is formed by copper-based metal plating. 6. The semiconductor device according to claim 5, wherein the metal plating of the conductive wire includes gold plating. 7. The semiconductor device according to claim 1, wherein the substrate is made of polyimide. 8. A semiconductor element having a large number of terminals for electrical connection to the outside, a substrate on which a plurality of the semiconductor elements are mounted, and wiring on the substrate for each terminal of the semiconductor element. A plurality of conductive wires electrically connected with, a jumping wire for wiring between predetermined conductive wires among these conductive wires, and a resin layer for sealing the jumping wire and the semiconductor element together, A semiconductor device comprising: 9. The semiconductor device according to claim 8, wherein the jumping wire has a surface coated with an insulator. 10. The semiconductor device according to claim 8, wherein the conductive wire is formed by metal plating based on copper. 11. The semiconductor device according to claim 10, wherein the metal plating of the conductive wire includes gold plating. 12. The semiconductor device according to claim 8, wherein the substrate is made of polyimide. 13. A semiconductor element having a large number of terminals for electrically connecting to the outside, a substrate on which a plurality of the semiconductor elements are mounted, and wiring on the substrate for each terminal of the semiconductor element. A plurality of conductive wires that are electrically connected to each other, a jumping wire for wiring between predetermined conductive wires among these conductive wires, and this jumping wire has a surface coated with an insulator,
A semiconductor device comprising: a resin layer for sealing the jumping wire and the semiconductor element together. 14. The semiconductor device according to claim 13, wherein the conductive wire is formed by copper-based metal plating. 15. The semiconductor device according to claim 14, wherein the metal plating of the conductive wire includes gold plating. 16. The semiconductor device according to claim 13, wherein the substrate is made of polyimide. 17. A substrate on which a semiconductor element having a large number of terminals for electrically connecting to the outside is mounted, and wiring for wiring the substrate to electrically connect to each terminal of the semiconductor element. And a terminal provided on some of the conductors for connecting jumping wires for wiring between predetermined conductors among these conductors. Base material for mounting. 18. The base material according to claim 17, wherein the substrate further comprises a mounting portion for mounting a plurality of semiconductor elements. 19. The substrate according to claim 17, wherein the conductive wire is formed by copper-based metal plating. 20. The base material according to claim 17, wherein the substrate is made of polyimide.