JPH05274279A - Parallel processing apparatus and method - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve data transmission speed and efficiency between processors of a parallel processing device. A transmission side processor and a reception side processor are provided with FIFO memories for data transmission and data reception, respectively, and by connecting these memories, an effective data transmission rate between the processors can be improved. Further, a receiving alternate buffer system memory is provided in the receiving side processor, and the received data from the receiving FIFO memory is transferred to one of the receiving buffer memories by the DMA system. Further, by replacing the transfer destination buffer memory for transferring the DMA data from the FIFO memory for each processing phase, the deterioration of the processing capability of the processor due to the data transfer between the processors is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing apparatus and method, and more particularly to a parallel processing apparatus and method in which high speed and flexibility are taken into consideration.

[0002]

2. Description of the Related Art Various proposals have heretofore been made to realize high-speed processing by configuring a parallel arithmetic unit using a plurality of processors. For example, Japanese Patent Application Laid-Open No. 3-174646 discloses a method of connecting a plurality of processors with a dedicated coupling line.

[0003]

In order to realize high-speed processing, it is important to improve the data transmission speed and efficiency between the processors to improve the performance, and the structure of the data transmission path between the processors is flexible. Although it is important to ensure the versatility of the arithmetic unit, in the above-mentioned conventional technique, it has been strongly demanded to improve the data transmission rate between processors and the flexibility of the connection structure.

It is an object of the present invention to provide a parallel processing apparatus and method for improving the data transmission rate and efficiency between processors.

Another object of the present invention is to provide a parallel processing apparatus and method for providing flexibility to a data transmission path structure between processors in order to ensure versatility of an arithmetic unit.

[0006]

The features of the present invention for achieving the above object are as follows.

(1) In order to improve the effective speed of data transmission between processors, the transmitting side processor and the receiving side processor respectively have a data transmission FIFO and a data reception FIFO.
By providing an O (First-in First-out) memory and connecting these, it is possible to improve the effective data transmission rate between the processors.

(2) Further, the reception side processor is provided with a reception alternate buffer system memory, and the reception data from the reception FIFO memory is transferred to one of the reception buffer memories by a DMA (Direct Memory Access) system. Further, by replacing the transfer destination buffer memory for transferring the DMA data from the FIFO memory for each processing phase, it is possible to eliminate the deterioration of the processing capability of the processor due to the data transfer between the processors.

(3) The structure of the parallel processing device can be freely changed by inserting a switch network capable of arbitrarily switching the connection in the connection portion between the plurality of processors.

(4) The connection structure between a plurality of processors is hierarchized, the structures of the respective hierarchies are the same, and the number of hierarchies of the hierarchies is increased, thereby making it possible to increase the number of processors to be connected virtually unlimitedly.

The features of the present invention other than the above and the above are further clarified from the following description.

[0012]

According to the present invention, a transmission FIFO memory and a reception FIFO are respectively provided to two processors for data transmission.
A memory is provided, the space between them is connected, and a receiving data memory area having a replacement buffer configuration is further provided in the receiving processor.
Data is transferred from the reception FIFO memory to the reception buffer by the DMA method. In one processing phase, data is transferred from the reception FIFO memory to one reception buffer, and the contents of the other reception buffer are read out and used for calculation. In the next processing phase, the alternate buffer can be switched and the written data can be read out from the reception FIFO memory for calculation.

Since data is transmitted between the two processors by such a method, one downstream processor refers to the result calculated by the upstream processor in the previous processing phase in terms of data flow by memory access. it can. When pipeline-type parallel processing is performed according to the direction of data flow, the time required for data transmission between processors is only the hardware access time to the high-speed memory.

As a result, the amount of information transmitted between the processors can be improved 10 to 100 times as compared with the conventional system, and the processing capacity of the parallel processing device is improved.

Further, a switch network for exchange connection is inserted between transmission / reception FIFO memories between a plurality of processors to be connected,
Since the connection state can be arbitrarily changed, the connection of the processor group forming the parallel processing device can be set to an efficient structure by adapting to the processing content, and a versatile operation can be performed.

Further, since the connection structure between a plurality of processors is hierarchized and the structure of each hierarchy is the same, it is possible to arbitrarily increase or decrease the number of processors to be connected by increasing or decreasing the number of stages of the hierarchy. It is possible to realize the computing power of the processing performance that matches the purpose.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is suitable for pipeline processing in which a final result is obtained by sequentially processing a set of data, as is found in various signal processing such as sound, image and video. ing. These processes are intended for data having a two-dimensional or three-dimensional spread in the natural world, and are capable of parallel processing simultaneously with pipeline processing. The present invention deals with these parallel and pipeline-processable processing targets by a parallel or pipeline having a structure most suitable for the target or a combination of both (hereinafter, “parallel / pipeline processing”).
Device) and method for realizing high-speed operation. Therefore, not only is the processing capability as a parallel processing device high, but the parallel / pipeline processing structure can be arbitrarily changed according to the target. Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, PE is a processor element and PE is a processor element group.
A group and a processor element group aggregate are called a PE group aggregate.

FIG. 1 shows an example of the structure of a group aggregate which is a constituent element of the parallel processing device. PE group ((1) ~ (2 m
-1)) 4 is a set of processors in charge of parallel / pipeline processing, each of which is composed of a plurality of PEs. The CPU 1 controls and controls the entire operation of the PE group assembly, and a general microprocessor board can be used. The memory 2 is used for storing a processing program of the CPU 1 and data, and a work area.
The external interface section 3 is for data communication when the PE group assembly is used by being connected to an external control computer or the like, and the external interface signal line 8 is an industry standard such as Ethernet. The switch network / synchronization control unit 6 includes a plurality of PEs that perform parallel / pipeline processing.
For the group 4, through the PE connection control network control signal line 12,
Timing control of processing start and connection control between PEs are performed.
The processing start timing may be obtained from the internal processing state of the PE group assembly or may be externally synchronized by the external synchronization signal line 15. PE group connection exchange switch network 7
Can flexibly change the connection form between the plurality of PE groups 4 connected by the PE group linkage signal line 11, and are connected to each other in a desired parallel connection, pipeline connection, or a combination thereof. A parallel / pipeline processing structure is realized. The switch network / synchronization control unit 6 implements the PE group connection switching switch network control signal line 13 so as to realize the connection form between the PE groups determined corresponding to the algorithm to be processed.
The internal connection status of the PE group connection exchange switch network 7 is controlled via the. The CPU bus 9 is a data path for the CPU 1 to control the devices connected to the CPU bus 9, such as the PE group linkage unit 5, the switch network / synchronization control unit 6, etc., based on the progress of processing or an external command. , An industry standard bus will do. The PE group linkage unit 5 is a CPU-P.
It is connected to the PE group 4 via the linkage signal line 10 between the E groups. The PE group aggregate of FIG. 1 is connected to another PE group aggregate via the inter-PE group aggregate linkage signal line 14.

FIG. 2 is a block diagram for explaining the structure of the PE group 4 of FIG. Linkage signal line 1 between PEs
7 is connected to the PE connection exchange switch network 18.

FIG. 3 shows an internal configuration example of each PE ((1) to (2 to the nth power −1)) 16 in FIG.
Further, a memory bus A28, a memory bus B29, and a DMA channel (1 to N) 24 are connected. Memory bus A28
Has an input FIFO memory 25 and an output FIFO memory 26.
Is connected to the communication port control unit 27, and the linkage signal line 3 between processor elements is connected from the port control unit 27.
With 0, connection with other PE is possible. A communication port and an input / output FIFO memory can be connected to a plurality of memory buses A28 to connect with a plurality of PEs. A program memory 20 and a data / work memory 21 are connected to the memory bus B29, and a set of an input buffer A22 and an output buffer B23 are connected to each communication port. The DMA channel 24 is provided corresponding to each communication port, and the data received in the input FIFO memory becomes a processing load of the arithmetic processing unit 19 by the control signal of the arithmetic processing unit 19 via the DMA channel control signal line 31. D in input buffer A22 or input buffer B23
MA transfer.

FIG. 4 shows another example of the internal structure of the PE, in which the memory bus B29 shown in FIG. 3 has an independent structure of the memory bus B29 and the memory bus C32. In this configuration, since the input buffer A22 and the input buffer B23 corresponding to each communication port are connected to different memory buses, in the processing phase where the arithmetic processing unit 19 is accessing the contents of the input buffer A22 via the memory bus B29. DMA data transfer is performed from the input FIFO memory 25 to the input buffer B23 via the memory bus A28 and the memory bus C32, and the input buffer memory is switched for each processing phase. Therefore, the input buffer access by the arithmetic processing unit 19 and the memory bus used for the DMA transfer can be separately performed in parallel, and the deterioration of the processing capacity due to the bus competition can be prevented.

The PE connection exchange switching network 18 of FIG. 2 connects the PE-to-PE linkage signal line 30 connected to the communication port of FIG. 3 or 4 to each communication port and to each PE. PE connection exchange switch network 18 is PE
Each communication port has the same structure as the number of ports. FIG. 5 shows a configuration example of one of the same structures.

As shown in FIG. 5, the function of the connection exchange switch network is to realize the freedom of interconnection between PEs forming a PE group. The switch network unit 33 realizes exchange connection between the connection exchange switch network input signal line 37 and the connection exchange switch network output signal line 38, and the connection exchange switch network input signal line 37 is a PE-PE linkage signal line of each PE. The connection switching switch network output signal line 38 is connected to another PE inter-PE linkage signal line 30 of each PE. The switch net portion 33 is configured by connecting switch elements 36. The connection exchange switch network input signal line 37 is prepared by adding the number of each PE plus one channel for external connection, and the number is preferably selected as a power of 2 in order to improve the efficiency of connection exchange. The configuration in FIG. 5 shows an example in which the number of connectable PEs is eight. The exchange function unit of the switch network unit 33 includes rows from PE0 to PE7 corresponding to the connection destination PE and columns from the 0th stage to the 3rd stage, and the connection exchange is performed by controlling the state of each switch element. The PE of the switch network input signal line 37 and any PE of the connection switching switch network output signal line 38 can be connected.

Generally, when there are 2n PEs,
The 0th to nth stage bus switches are arranged in a matrix so that the number of rows is 2 to the nth power and the number of columns is n + 1, and the connection destinations of the bus switch elements of each matrix are as follows (1) ( 2) Determined according to the principle of (3).

(1) An ordinal number i from 0 to (2 to the nth power) -1 is assigned to PE.

(2) When i is represented by a binary number, (n of 2)
It is an n-digit binary number from the power of 1 to the power of 2 0.

(3) When the bit of the 2nd power of k is 0 in (2): The element of the i-th row (k + 1) th column and the element of the (i + 2kth) -th row kth column The element of the i-th row (k + 1) th column and the i-th row Connect the elements in column k.

In (2), when the k-th power of 2 is 1, the element in the i-th row (k + 1) th column and the element in the (i-2th k-th) -th row k-th column The element in the i-th row (k + 1) th column and the i-th row k Connect the elements in a row.

As described above, (2) and (3) are carried out in steps of 1 from k = 0 to n-1 and from i = 0 to (2 to the nth power) -1.

Since the connection paths between the switch elements from the (n-1) th column to the 1st column may be used in duplicate depending on the connection status between PEs, they are multiplexed as necessary. The connection state of the switch network 33 can be controlled by switching the connection state of each switch element 36. The switching control unit 34 is controlled by the CPU 1 via the PE connection exchange switch network control signal line 12, stores a connection state that can be selected in the connection state memory 35 in advance, and selects a connection pattern by a selection signal from the CPU 1. Then, the state of the switch element 36 is controlled.

The switching control unit 34 stores the switch element states of each matrix in the connection state memory 35 via the PE connection exchange switch network control line 12. When there is a connection switching command from the switch network / synchronization control unit 6, the switching control unit 34 first receives the connection switching command. Next, the switch element state is defined based on the switch connection state selected from the contents of the connection state memory 35. The CPU-PE linkage signal line 10 can be connected to each PE by the fourth or fifth stage switch element 36, and is used for initial program loading from the CPU 1 and data transfer.

FIG. 6 shows an example of the function of each switch element 36. 2 inputs bus input via switch element input signal line 39 and 2 inputs via switch element output signal line 40
Exchange connection is made between the output bus outputs based on an external control signal, and one of the states (a) and (b) is set by a command via the switch signal control signal line 41.

FIG. 7 shows an example of the structure of the switch element 36. AND gate 42, OR gate 4
3, can be realized by combining the NOT gates 44.

FIG. 8 is a block diagram for explaining the operations of the PE (a) 45 and the PE (b) 53 connected to each other in association with each other. The PE 45 includes an arithmetic processor (a) 46,
Input buffer a-A47, input buffer a-B48, input FIFO (a) 49, output FIFO (a) 50, DM
A channel (a) 51 is included. The PE (b) 53 includes an arithmetic processor (b) 54, an input buffer b-A55, an input buffer b-B56, an input FIFO (b) 57, and an output F.
Including IFO (b) 58 and DMA channel (b) 59,
It is connected to the PE 45 via the communication port output (a) 52, the connection exchange switch network 62 and the communication port input (b) 60. The PE (b) 53 is further connected to another PE via the communication port output (b) 61.

FIG. 9 shows PEs connected adjacently as shown in FIG.
An example of the operation of (a) 45 and PE (b) 53 is shown in a time chart. Here, a group of processes that are targets of the parallel / pipeline process will be referred to as one-phase process.

In the processing of phase 1, the arithmetic processor
(a) 46 stores the operation result in the output FIFO memory (a) 50. Focusing on the logical operation of the PE connection exchange switch network 18 in FIG. 2 between the two sets of connected PEs, the connection exchange switch network 62 in FIG. 8 can be simplified. In phase 1, the operation result data stored in the output FIFO memory (a) 50 is transferred to the PE via the PE connection switch network 62.
(b) Immediately transferred to the input FIFO memory (b) 57 of 53. The data in the input FIFO memory (b) 57 is DM
DMA transfer is performed to the input buffer b-A55 by the A channel (b) 59.

In the processing of phase 2, the input buffer b-
A55 is connected to the arithmetic processor (b) 54, and the data from the input FIFO memory (b) 57 is DMA-transferred to the input buffer b-B56. The operation result of the phase 1 is stored in the input buffer b-A 55, and the operation processor (b) 54 can access it in the phase 2 and the operation processor (b) 54 executes the process of the next stage according to the contents in the pipeline. can do. In Phase 2, during this time, the arithmetic processor (a) 46 is in Phase 1
Is executed and the result is stored in the input buffer b-B56 via the PE connection exchange switch network 62.

10 (a) and 10 (b) are examples of connecting and implementing a parallel processing device composed of seven PEs. By switching the connection of the PE connection exchange switch network 18 of FIG. 2, an arbitrary connection between PEs can be realized. PE
In this case, the connection exchange switch network 18 can connect and exchange eight PEs. However, one PE of each of the connection exchange switch network input signal line 37 and the connection exchange switch network output signal line 38 shown in FIG. In the case of, the PEs are not allocated and are left for external connection, and seven PEs are connected. Connection by single line 63, connection by double line 64 and dotted line 6
Reference numeral 5 indicates a connection by a separate PE connection switching network switch network. For example, FIG. 11 is a connection function diagram of the PE connection exchange switch network (a part 1). FIG. 12 is a connection function diagram of the PE connection exchange switch network (a-2). Figure 1
3 is a connection function diagram of the PE connection exchange switch network (a-3). FIG. 14 is a connection function diagram of the PE connection exchange switch network (b-1). FIG. 15 is a connection function diagram of the PE connection exchange switch network (b-2). FIG. 16 shows P
It is a connection function diagram of E connection exchange switch network (b 3).

In the example of FIG. 10A, three sets of PE connection exchange switch networks of FIG. 5 are used, and the portion of the single line 63 is a connection function diagram of PE connection exchange switch network (a 1) (FIG. 11). Of the PE connection exchange switch network (a 2) is connected to the thick line portion of the PE connection exchange switch network (FIG. 12), and the dotted line is further connected. This can be realized by setting the portion 65 to connect the thick line portion in the connection function diagram (FIG. 13) of the PE connection exchange switch network (a 3).

Further, in the example of FIG.
3 sets of PE connection exchange switch networks, and the single line 63 is set to connect the thick line portion in the connection function diagram (FIG. 14) of the PE connection exchange switch network (FIG. 14). The portion 64 is set to connect the thick line portion in the connection function diagram (FIG. 15) of the PE connection exchange switch network (b-2), and the portion of the dotted line 65 is the PE connection exchange switch network (b-3). It can be realized by setting so that the thick line portion in the connection function diagram (FIG. 16) is connected. The connection shown in FIG. 10 is an example, and the CPU 1 sets a PE connection pattern corresponding to the parallel / pipeline processing structure of the processing target, and gives a command to the switch network / synchronization control unit 6. The PE connection command may specify the PE connection pattern only once at the start of the calculation, and may keep the same connection until the calculation is completed. If necessary, the PE connection command may be connected before the start of the processing phase during the calculation. You may change it.

In order to operate each PE which constitutes each PE group 4 according to a desired program and data, it is necessary to load the program and data into each PE at a necessary timing. The PE group linkage portion 5 in FIG.
This group exists for this purpose with respect to the group 4, one of the PE group linkage parts 5 is connected to the CPU bus 9, and the other is connected to the PE group 4.

FIG. 17 shows an example of the configuration of the PE group linkage unit 5 of FIG. 1, in which the memory bus A75 and the memory bus B76 are connected to the arithmetic processing unit 66, and the DMA channel 70 is connected via the DMA channel control line 79. It is connected.
An input FIFO memory 71 and an output F are provided on the memory bus B76.
A communication port including the IFO memory 72 and the port control unit 73 is connected. On the other hand, memory bus A75
Program memory 78, data / work memory 6
7, dual port memory 68, and buffer memory 6
9 is connected. CPU1 means CPU bus 9, CP
The dual port memory 68 is connected via the U-bus interface signal line 74, and the program and data to be loaded into the PE are written from the CPU 1 to the dual port memory 74. What is each PE 16 that constitutes the PE group 4?
They are connected via an E linkage signal line 77. The information written in the dual port memory 68 is DMA
It is written in the output FIFO memory 72 under the control of the channel 70 and transmitted from the port control unit 73 to each PE to which it is connected. The main purpose of the PE group linkage section 5 is to efficiently use each PE.
Since the information is transmitted from the CPU 1, it is preferable to increase the number of communication ports connected to the PE as much as the information transmission capability allows. A DMA channel 70 is provided for this purpose, and the information transferred and stored in the dual port memory 68 or the buffer 69 is distributed and transmitted to the connection destination PEs without imposing a load on the arithmetic processing unit 66. The buffer 69 may be provided for each connection destination PE and used as a storage buffer area for transmission data. Also, the transfer destination of the DMA channel 70 at the time of fetching information from the connection destination PE via the PE linkage signal line 77 and the input FIFO memory. You may use as.

The PE connection exchange switch network 7 in FIG. 1 is a connection exchange switch network for arbitrarily controlling the connection between the PEs included in each PE group 4 to perform data transmission.
Each PE group 4 is connected by a PE group linkage signal line 11, but finally, as shown in FIG.
The inter-group linkage signal line 11 is the PE connection exchange switch network 1.
2 is exchange-connected to each PE.

FIG. 18 shows the structure of the PE connection exchange switch network 7. The PE group connection exchange switch network 7 has the same structure as the PE connection exchange switch network 18 in FIG. However, in the case of PE group connection exchange switch network 7, PE
Unlike the connection exchange switch network 18, each PE from the CPU 1
There is no need to transfer programs and data to
The PU-PE linkage signal line 10 may be omitted. P
The connection state control of the E group connection switching switch network 7 is performed by the switch network / synchronization control unit 6 via the PE group connection switching switch network control signal line 13 in accordance with an instruction from the CPU 1.
With the device shown in FIG. 18, the same control as the connection exchange control performed for each PE in the PE group shown in FIG.
Can be performed on a group. That is, the PE group aggregate shown in FIG. 1 has a group of PEs capable of connection control which is hierarchically divided into two layers. In the PE group connection exchange switch network of FIG. 18, the PE groups are connected to each other and configured by a plurality of PE groups.
At the same time that the group assembly is constructed, a plurality of PE group assemblies can be connected via the inter-PE group assembly linkage signal line 14. The connection between PEs within a PE group can be realized on the same printed board with today's integration technology and mounting technology, but it is composed of PE groups, PE group aggregates, and multiple PE group aggregates in parallel. As the hierarchy of the processing device and the PE group increases, the distance of the signal line connected to the connection exchange switch network becomes longer. The EO / OE conversion unit 80 in FIG. 18 converts the long-distance transmission unit into optical transmission in order to cope with the increase in the connection distance, and prevents a decrease in transmission speed.

FIG. 19 shows a configuration example of a parallel computing device (or parallel computing mechanism) configured by connecting a plurality of PE group aggregates. PE group aggregate ((1) to (2 to the power 1-
The details of 1)) 81 are as shown in FIG. 1, and the external interface signal line 8 is provided via the external interface section 3.
To connect with the linkage bus 86. Here, 1 represents the lowercase letter of the English letter L. The control computer 82 issues a command to the CPU 1 in the PE group assembly, and also executes program development, man-machine communication, through the video terminal 84.
The operation status of the entire parallel computing device is displayed. Further, the operation record of the control computer 82 can be recorded in the printer 83. The PE group aggregates 81 are connected and exchanged by the PE group aggregate connection exchange switch network 85 via the PE group aggregate linkage signal line 14.

FIG. 20 shows a configuration example of the PE group aggregate connection / switching switch network 85 of FIG. The PE group aggregate connection switching switch network 88 has the same structure as the PE connection switching switch network 18 in FIG. 2 and the PE group connection switching switch network 7 in FIG. 18, and has the same connection switching control function. .. The PE group aggregate connection exchange switch network control signal line 89 is the same as the PE group connection exchange switch network control signal line in FIG. Therefore, it may be connected to any one of the PE group aggregates 81 shown in FIG. 19 and controlled similarly to the PE connection switching network 18 for the PE group aggregates. The linkage signal line 87 between parallel arithmetic units connected to the PE group aggregate connecting / switching switch network 85 is used for further connecting and exchanging the parallel arithmetic units as shown in FIG. The linkage signal line 87 between parallel processing devices is the linkage signal line 1 between PE group aggregates.
It has the same structure as 4 logically. EO /
The OE converter is a converter for converting to transmission by an optical signal in order to prevent deterioration of transmission performance because the distance of signal transmission between PE group aggregates becomes long.

FIG. 21 shows the synchronization control function of the switch network / synchronization control unit 6 in FIG. Since the parallel arithmetic device according to the present invention is characterized by performing arithmetic operations in synchronization with each processing phase, it is necessary for each PE to synchronously start the processing phase, and the PE synchronization command 93 is transmitted to the switch network / synchronization. The control unit 6 transmits to each PE at each phase start time. As a method of generating the synchronization signal, the signal of the external synchronization signal line 96 may be used as it is, or the PE synchronization command 93 may be periodically generated by setting the programmable timer 94 by the synchronization timer setting value 91. Here, the synchronization timer set value 91 can be specified by the CPU 1 for the longest time required for each PE to finish the processing of one phase. Especially when the processing time for each phase of each PE changes, the processing end signal 90 of each PE
Must be input to the AND logic 95, and the PE synchronization command 93 must be output when the processing of all PEs is completed. In FIG. 21, the three types of synchronization methods are selectable by the synchronization method selection signal 92, but the switch network / synchronization control unit 6 may have only one or two types of the three types of synchronization methods. .. The synchronization method selection signal 92 is CP
It may be set from U1 or the control computer 82.

FIG. 22 shows a time chart when the synchronization command 93 is generated by the processing end signal 90 of each PE. When the processing of all PEs from PE0 to PEn is completed, the switch network / synchronization control unit 6 reports to the CPU1.
If it is necessary to change the connection of the switching connection switch network based on this report, a change command is issued to the switch network / synchronization control unit 6. When there is no change in connection, each PE is directly instructed to start the next processing phase.

FIG. 23 shows a printed board 10 of the PE group shown in FIG.
0 shows an example of implementation on 0. The processor 97 preferably has a high-speed processing capability, for example, a DSP (digital signal processor is adopted. P shown in FIG. 3 is used.
Of E, the arithmetic processing unit 19 and the plurality of DMA channels 2
4, the peripheral circuit related to the linkage between PEs is largely omitted by using as the processor 97 a DSP in which a plurality of communication ports composed of an input FIFO 25, an output FIFO 26, and a control port 27 are integrated on one chip. You can A highly integrated and high-speed memory is suitable for the memory 98, and 4 Mbit SRAM is preferable in the current state of the art. The switch network element 99 must connect the linkage signal lines between the processors in the shortest distance, and can freely control the connection from the outside by a program.
For this purpose, the connection exchange switch network corresponding to FIG. 5 is integrated into a circuit to minimize the signal propagation delay of the switch section.
Moreover, by realizing the miniaturization of the circuit at the same time by integration and arranging as many PEs as possible on one printed board,
Improves linkage performance between PEs. The processors 97 are arranged so as to be concentrated in the central portion of the printed board by surrounding the switch network elements 99 so that the distance between them is minimized. The printed board connecting portion 101 is the CPU-in FIG.
PE group linkage signal line 10, PE group linkage signal line 11, and PE connection exchange switch network control signal line 12
Is to be pulled out of the printed board and connected to another printed board. The other printed boards referred to here are a PE group other than itself, a PE group linkage unit, a PE group connection / switch network, and a switch network / synchronization control unit.

FIG. 25 shows an example of mounting the PE group connection exchange switch network of FIG. 18 and the PE group aggregate connection exchange switch network of FIG. 20 on a printed board. PE group and P
The logical structure of the linkage signal line to the outside of the E group aggregate is the same as that of the PE, and is the connection between the FIFOs. Since the logical specifications of the PE group and the PE group assembly from the outside are the same as those of the PE, they can be mounted on the same printed circuit board as the PE connection exchange switch network of FIG. That is, the switch network element 99 of FIG. 23 is applied as it is, the processor 97 and the memory element 98 are removed, and at the same time, the driver unit 102 is necessary as necessary to guarantee the reduction of the electric signal level due to the signal interface with the outside of the printed board. Is installed between the board and the printed board connecting portion 101 for signal connection with the outside of the board. PE
In the case of a group aggregate connection exchange switch network, the distance is long because it is a connection between PE group aggregates having a unit structure. If necessary, an E / O converter and an O / E converter may be connected to the end of the printed board connecting portion 101. The printed board connecting portion 101 is connected to the PE group linkage signal line 11 or P.
The linkage signal line 14 between the E group aggregates and the PE connection exchange switch network control signal line 12 are drawn out of the printed board,
It is for connecting to another printed board or unit. The other printed boards or units mentioned here are
The PE group of the connection destination or the PE group aggregate of the connection destination.

FIG. 24 is a diagram conceptually showing the relationship between PEs included in the parallel arithmetic unit according to the present invention. PEs are layered in 3 stages, and PEs are connected to each other.
One PE group has the same external linkage signal line as one PE as a whole. A PE group aggregate is formed by collecting a plurality of PE groups and connecting them to each other. Further, a group of a plurality of PE group aggregates that are connected to each other is a parallel computing device (also referred to as a parallel computing mechanism).

That is, the logical relationship of the PE group aggregate to the parallel computing device, the logical relationship of the PE group to the PE group aggregate, and the logical relationship of the PE to the PE group are all the same structure. This relationship (hierarchical level / connected elements / linkage between elements) is 1) parallel arithmetic unit / PE group aggregate / PE group aggregate linkage signal line 2) PE group aggregate / PE group / PE group linkage signal line 3) It becomes a linkage signal line between PE group / PE / PE. By having such a logical structure, there is no logical restriction in stacking and connecting a plurality of PEs over three layers, and it is possible to realize a parallel arithmetic device of practically any scale. In particular, in the parallel computing device according to the present invention, as regards the linkage between PEs, the smaller the degree of passing through the upper hierarchy, the smaller the mounting distance of the linkage signal line and the number of logic gate stages to pass through, which enables high-speed and large-capacity data transmission. It is possible to allocate the information transmission capacity stepwise from PEs that are in a logically close relationship to PEs that are in a logically distant relationship.

As described above, since a plurality of processors are connected by the FIFO and DMA transfer is performed between the receiving memory area of the alternate buffer structure and the receiving FIFO, the transfer data between the processors of both the transmitting and receiving processors Data can be read and written in memory cycles, improving the data transmission speed and efficiency between processors. As a result, the processing capability of the parallel computing device is improved. Further, since the connection state between the processors can be arbitrarily changed by the connection exchange switch network, it is possible to perform efficient calculation by adapting to the processing contents of a wide range of applications.

[0054]

According to the present invention, it is possible to provide a parallel processing apparatus and method for improving the data transmission rate and efficiency between processors.

Further, according to the present invention, it is possible to provide a parallel processing apparatus and method in which flexibility is imparted to a data transmission path structure between processors in order to ensure versatility of an arithmetic unit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a PE group aggregate according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a PE group according to an embodiment of the present invention.

FIG. 3 is an internal configuration diagram of a PE according to an embodiment of the present invention.

FIG. 4 is a diagram showing another example of the internal configuration of the PE according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a PE connection exchange switch network according to an embodiment of the present invention.

FIG. 6 is a diagram showing an example of the function of the switch element of FIG.

FIG. 7 is a diagram showing an example of the configuration of the switch element of FIG.

FIG. 8 is a connection configuration diagram between adjacent PEs according to an embodiment of the present invention.

9 is a time chart showing an example of the operation of the configuration shown in FIG.

FIG. 10 is a diagram showing a connection implementation example of a PE according to an embodiment of the present invention.

FIG. 11 is a PE connection exchange switch network according to an embodiment of the present invention.
It is a connection function diagram of (a 1).

FIG. 12 is a PE connection exchange switch network according to an embodiment of the present invention.
It is a connection function diagram of (a2).

FIG. 13 is a PE connection exchange switch network according to an embodiment of the present invention.
It is a connection function diagram of (a3).

FIG. 14 is a PE connection exchange switch network according to an embodiment of the present invention.
It is a connection function diagram of (b 1).

FIG. 15 is a PE connection exchange switch network according to an embodiment of the present invention.
It is a connection function diagram of (b 2).

FIG. 16 is a PE connection exchange switch network according to an embodiment of the present invention.
It is a connection function diagram of (b 3).

FIG. 17 is a connection configuration diagram of a PE group linkage unit according to an embodiment of the present invention.

FIG. 18 is a configuration diagram of a PE group connection exchange switch network according to an embodiment of the present invention.

FIG. 19 is a configuration diagram of a parallel arithmetic device according to an embodiment of the present invention.

20 is a diagram showing a configuration example of the PE group aggregate connection / switching switch network of FIG. 19;

FIG. 21 is a diagram showing an example of a synchronization control function according to an embodiment of the present invention.

22 is a diagram showing an example of a time chart of the synchronization control shown in FIG.

FIG. 23 is a diagram showing an example of mounting a PE group on a printed board according to an embodiment of the present invention.

FIG. 24 is a conceptual diagram showing an example of a hierarchical structure of a parallel arithmetic device in one embodiment of the present invention.

FIG. 25 is a diagram showing an example of mounting a PE group connection exchange switch network and a PE group aggregate connection exchange switch network on a printed board according to an embodiment of the present invention.

[Explanation of symbols]

1 ... CPU, 2 ... Memory, 3 ... External interface section, 4 ... PE group, 5 ... PE group linkage section, 6 ... Switch network / synchronization control section, 7 ... PE group connection / switching switch network, 8
... external interface signal line, 9 ... CPU bus, 10
... CPU-PE group linkage signal line, 11 ... PE group linkage signal line, 12 ... PE connection exchange switch network control signal line, 13 ... PE group connection exchange switch network control signal line,
Reference numeral 14 ... PE group aggregate linkage signal line, 15 ... External synchronization signal line, 16 ... PE, 17 ... PE linkage signal line, 18 ... PE connection exchange switch network, 19 ... Arithmetic processing unit, 20 ... Program memory, 21 ... Data / work memory, 22 ... Input buffer A, 23 ... Input buffer B,
24 ... DMA channel, 25 ... Input FIFO, 26 ... Output FIFO, 27 ... I / O port controller, 28 ... Memory bus A, 29 ... Memory bus B, 30 ... Processor element linkage signal line, 31 ... DMA channel control signal Line, 32 ... memory bus C, 33 ... switch network part, 34
... switching control unit, 35 ... connection state memory, 36 ... switch element, 37 ... connection exchange switch network input signal line, 38
Connection switching switch network output signal line, 39 switch element input signal line, 40 switch element output signal line, 41 switch element control signal line, 42 AND gate, 43 O
R gate, 44 ... NOT gate, 45 ... PE (a), 4
6 ... Arithmetic processor (a), 47 ... Input buffer a-
A, 48 ... Input buffer a-B, 49 ... Input FIFO
(A), 50 ... Output FIFO (a), 51 ... DMA channel (a), 52 ... Communication port output (a), 53 ... PE
(B), 54 ... Arithmetic processor (b), 55 ... Input buffer b-A, 56 ... Input buffer b-B, 57 ... Input F
IFO (b), 58 ... Output FIFO (b), 59 ... DM
A channel (b), 60 ... Communication port input (b), 61
... communication port output (b), 62 ... connection exchange switch network,
63 ... Single line, 64 ... Double line, 65 ... Dotted line, 66 ... Arithmetic processing section, 67 ... Data / work memory, 68 ... Dual port memory, 69 ... Buffer memory, 70 ... DMA channel, 71 ... Input FIFO, 72 … Output FIFO, 7
3 ... Port control unit, 74 ... CPU bus interface signal line, 75 ... Memory bus A, 76 ... Memory bus B, 77
... PE linkage signal line, 78 ... Program memory, 7
9 ... DMA channel control line, 80 ... EO / OE converter,
81 ... PE group aggregate, 82 ... Control computer, 83 ... Printer, 84 ... Video terminal, 85 ... PE group aggregate connection / switch network, 86 ... Linkage bus, 87 ... Parallel processing unit linkage signal line, 88 ... PE group aggregate Connection exchange switch network, 89 ... PE group assembly connection exchange switch network control signal line, 90 ... PE processing end signal, 91 ... synchronization timer set value, 92 ... synchronization method selection signal, 93 ... PE synchronization instruction,
94 ... Programmable timer, 95 ... AND logic, 96
... external synchronization signal line, 97 ... processor, 98 ... memory element, 99 ... switch network element, 100 ... printed board, 10
1 ... Printed board connection part, 102 ... Switch network driver part.

Claims (19)

[Claims] 1. An arithmetic processing unit, an input FIFO memory provided on a signal input side, and an output FI provided on a signal output side.
A parallel processing device including a processor element having an FO memory, comprising a plurality of processor elements, and including a processor element group for performing data transmission between the processor elements via a processor element connection switching network. Parallel processing device. 2. The processor element according to claim 1, wherein the processor element is different from a first bus connecting the arithmetic processing unit and the input FIFO memory and / or the output FIFO memory, and a first bus different from the first bus. The parallel processing apparatus further comprising: an input buffer connected to the arithmetic processing unit by a second bus; and means for performing DMA transfer of data between the input buffer and the FIFO memory. 3. A parallel structure comprising a plurality of processor element groups according to claim 1, and including a processor element group aggregate for performing data transmission between the processor element groups via a processor element group connection switching network. Processing equipment. 4. The parallel processing device according to claim 1, wherein the processor element group aggregate has a management processor for controlling the processor element group connection switching network. 5. A parallel arrangement comprising a plurality of processor element group aggregates according to claim 4, and connecting the processor element group aggregates with each other using a linkage signal line between the processor element group aggregates for transmitting data between the processor element group aggregates. Processing equipment. 6. The parallel processing apparatus according to claim 1, wherein the processor element connection exchange switch network has a structure that enables connection between arbitrary processor elements. 7. The parallel processor according to claim 4, wherein the management processor can control a connection state of the processor element connection switching switch network via a switch network connection control unit in accordance with a processing target. Processing equipment. 8. The management processor according to claim 4, wherein the management processor can control the connection state of the processor element connection exchange switch network via a switch network connection control unit in accordance with the progress of processing. Parallel processing device. 9. A plurality of processor elements each including a computing unit having a plurality of transmission channels and a main memory,
A switch network capable of arbitrarily controlling connection of some or all of the transmission channels by external control is arranged on the same printed board, and a plurality of processors on the same printed board associate and process information with each other. Parallel processing device characterized by. 10. n pieces (n is a natural number) on the same printed board
2m units (m
Is a natural number), and m sets of switch networks that connect channels that can be one input channel and channels that can be one output channel from each processor are provided. The parallel processing device is characterized in that the input channel of the above and the output channel of an arbitrary processor can be connected in a one-to-one correspondence according to control from the outside. 11. The switch network between a plurality of processors according to claim 10, wherein the input side to the output side of the switch network are formed on the same integrated circuit, and each of the m switch networks is formed as required. The input and output channels are grouped by a specific number of bits and divided, and a set of switch networks is divided into a plurality of bit slices corresponding to the groups. A parallel processing device characterized by being integrated in an integrated circuit. 12. A system according to claim 10, wherein n is selected to be a power of 2 2k, a switch network capable of connecting to n processors is provided, and n-1 processors are arranged. Without arranging one processor, the input channel group for the non-allocated processor is connected to the output channel group for the non-allocated processor of another parallel arithmetic device having the same structure in a one-to-one correspondence, By connecting the output channel groups to the input channel groups to the non-arranged processors of another parallel arithmetic unit having the same structure to each other in a one-to-one relationship, the processors in the two parallel arithmetic units can be mutually connected. A parallel processing device having a structure. 13. A system according to claim 10, wherein n is selected to be a power of 2 2k, and a switch network capable of connecting to n processors is provided, and then n-1 processors are arranged. N sets of external connection input / outputs for an aggregate of n parallel arithmetic devices having an input channel group and an output channel group for external connection without arranging one processor A parallel processing device having a structure in which channel groups are connected by a switch network having the same structure as the processors in the parallel processing device are connected, and the processors in the n sets of parallel processing devices can be connected to each other. .. 14. The switch network to which the n parallel arithmetic devices are connected according to claim 13, wherein n−1 parallel arithmetic devices are connected and one parallel arithmetic device is not connected and the non-connection is made. N parallel computing device aggregates having an input channel group and an output channel group for the parallel computing device for external connection
To the aggregate of up to n pieces, the n sets of external connection input / output channel groups are connected by a switch network having the same structure as that of each processor in the parallel operation device, and n sets of parallel operations are connected. A parallel processing device having a structure in which processors in a device assembly can be connected to each other. 15. An arithmetic processing unit, an input FIFO memory provided on a signal input side, and an output F provided on a signal output side.
A first bus connecting the IFO memory, the arithmetic processing unit, and the FIFO memory; an input buffer connected to the arithmetic processing unit by a second bus different from the first bus; An information processing method having a processor element including means for performing DMA transfer of data to and from the FIFO memory, wherein in the case of performing data transfer between a plurality of processor elements, an output from a transmitting side arithmetic processing unit When writing data directly to the FIFO memory and transmitting information to the receiving side input FIFO memory, a pair of receiving side input buffers for DMA transfer from the receiving side input FIFO memory are prepared for each receiving side input FIFO memory, and configured as an alternate buffer memory. Then, in the first phase, one of the pair of alternate buffer memories is The DMA transfer destination from the input FIFO memory is used, and the other of the replacement buffer memories is set as a processing target data area of the reception side arithmetic processing unit. In the second phase, the other of the replacement buffer memories is transferred from the input FIFO memory. As a DMA transfer destination,
A parallel processing method, wherein one of the replacement buffer memories is used as a processing target data area of a reception side arithmetic processing unit. 16. The method according to claim 15, wherein when each of the plurality of processor elements shares a group of processing tasks, it occurs at a timing longer than the longest time required to execute one phase of processing. A synchronization signal generating means for outputting a synchronization signal to the processor element, wherein the processor element starts the processing of one phase at the time when the synchronization signal is generated from the synchronization signal generating means, and executes the next synchronization. A parallel processing method characterized in that the processing of the next phase is started when a signal is generated. 17. The synchronizing signal generating means according to claim 15, wherein the synchronizing signal generating means detects that all the processors of the processor group have completed one-phase processing, and generates the synchronizing signal based on the result. And parallel processing method. 18. The synchronization signal generating means according to claim 15, wherein the synchronization signal generating means generates the synchronization signal at a cycle longer than the longest time required for all the processors of the processor group to complete one-phase processing. A parallel processing method characterized by: 19. The parallel processing method according to claim 15, wherein said synchronization signal generating means can change the generation period of said synchronization signal in response to a command from said management processor.