JP3209630B2 - Data transfer device and multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer apparatus for transferring data between processors and transferring data between the processors and the outside in a multiprocessor system in which a plurality of processors perform parallel processing. is there.

[0002]

2. Description of the Related Art In recent years, the scale of information processing has been increased, and a computer system with high performance has been required. The parallel computer is designed to improve performance by sharing processing among many processors. In general, in parallel processing, data transfer between processors is required as the processing in a plurality of processors progresses. In order to perform such communication between processors, various interconnection networks (data transfer networks) have been proposed. Among them, the crossbar network is a complete connection network, and communication between arbitrary processors can be realized by one data transfer.

FIG. 22 shows a configuration of a conventional multiprocessor system in which a plurality of processor elements (PEs) are connected by a crossbar network. In the figure, reference numeral 50 denotes a transmitting processor element, 55 denotes a receiving processor element, 60 denotes a transmitting data transfer control device, 65 denotes a receiving data transfer control device, and 70 denotes a buffer as a data transfer channel (connection node). Unit.

[0004] How a crossbar network logically represented as shown in FIG. 22 is realized by actual hardware differs depending on each parallel computer. Also,
The procedure for accessing the network as the processing progresses also differs depending on the processing content. FIG. 23 shows a FIFO buffer 71 of the first-in first-out type in which each buffer unit 70 is provided.
FIG. The processor element 50 on the transmission side can send data to the channel while the FIFO buffer 71 is empty. The receiving processor element 55 reads data from the non-empty FIFO buffer 71. Therefore, it is not necessary to set the connection state of the entire network, unlike the case where the connection node is constituted by a simple switch.

FIGS. 24 and 25 show examples of generation of a buffer unit address (channel number) for designating a data transfer destination in the configuration shown in FIGS. 22 and 23.
FIG. 24 shows a configuration of a conventional address generation circuit built in the transmission-side data transfer control device 60. FIG.
In 4, the address generation circuit 61 includes an n-bit pointer 62 and a +1 adder 63. According to this configuration, when data is sent from the transmitting processor element 50 to the receiving processor element 55, the buffer unit address A held in the n-bit pointer 62 is incremented by the address update request signal CNT every time data is transferred. 25, the channel number of the data transfer destination can be sequentially designated. This is called "burst transfer". This data transfer method does not require extra time for channel designation and only needs to provide a pulse as a CNT signal, so that the data transfer rate is high.

[0006]

In the configuration of the address generation circuit 61 as shown in FIG. 24 in the conventional data transfer apparatus, for example, if the n-bit pointer 62 is 2 bits, 0, 1, 2, 3, 0, 1, 1 2, 3, ..., 2
Only the size of the power is counted, the range of change of the address is fixed, and limited to sequential address generation.

For this reason, in a multiprocessor system using a data transfer network having a fixed size, the efficiency of parallelization decreases because the size of the network cannot be optimized according to the processing contents. In addition, when processor elements are grouped and it is desired to perform different data transfer for each group, burst transfer cannot be employed, so that another data transfer method having a low transfer rate must be used. ing.

Further, in a multiprocessor system using a data transfer network capable of generating only sequential addresses as described above, there is a problem that, for example, three-dimensional array data cannot be efficiently processed. This is because, when data is distributed and collected in a multiprocessor system, discrete address values often appear.

An object of the present invention is to increase the processing efficiency of a multiprocessor system by employing a programmable address generation mechanism.

[0010]

In order to achieve the above object, the present invention restricts the upper and lower limits of a buffer unit address and changes the increment thereof.

[0011]

According to the present invention, the network can be divided by the upper and lower limits of the buffer unit address, so that the processing efficiency of the multiprocessor system can be improved. By limiting the address change range, it is possible to arbitrarily select data transfer between the processor elements and data transfer between the processor elements and the data input / output device.

Also, by changing the increment, discrete address values can be generated easily and at high speed.
It is possible to efficiently generate a transfer destination address or a transfer source address of a network suitable for a data structure of dimensions or more.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a configuration of a data transfer apparatus according to an embodiment of the present invention. The data transfer control device 10 and the K buffer units (BU) 20 are interconnected by a data transfer bus 16. The data transfer control device 10 includes an address register 1
2, an address counter 13, a comparator 14, a network interface 6, an internal bus 15, and an address control circuit 11 for controlling them. The address register 12, the address counter 13, and the comparator 14 constitute the address generation circuit 7.
R / W is a register setting signal for controlling address setting from a processor element (not shown) to the address register 12, SET and CNT are address setting signals and address update request signals to the address counter 13, and C is a comparator 14 A is a buffer unit address sent to the data transfer bus 16.

FIG. 2 is a diagram showing a detailed internal configuration of the address generation circuit 7. As shown in FIG. The address register 12 holds three addresses: an initial address, a lower limit address, and an upper limit address. The address counter 13 includes a +1 adder 17
, A selector 18 and an address latch 19. The selector 18 selects one of the three addresses of the initial address and the lower limit address from the address register 12 and the address after being incremented by the +1 adder 17 in accordance with the address setting signal SET. The output of the selector 18 is input to the address latch 19, and the held value A is used as an address output to each buffer unit 20. The output A of the address latch 19 and the upper limit address from the address register 12 are compared by the comparator 14.
To enter. Comparator 14 compares these two values,
The comparison result is returned to the address control circuit 11 as a match signal C.

Next, the operation of the data transfer device having the above configuration will be described. FIG. 3 shows an example of address setting. First, the initial address of the address register 12 (for example, 17)
Is selected by the selector 18 and stored in the address latch 19, and the buffer unit address A is set as the initial address. Then, data transfer is performed to the buffer unit 20 specified by the address A. next,
The selector 18 is switched to the output of the +1 adder 17, and the address update request signal CNT is applied to the address latch 19 every time data is transferred.
Are sequentially incremented. When transferring data to the buffer unit 20 one after another, the address is sequentially changed by the CNT signal and burst transfer is performed. When the address held by the address latch 19 reaches the upper limit address (for example, 25), the comparator 14 outputs a match signal C. At this time, the selector 18 is set to the lower limit address (for example, 1) by the address setting signal SET.
0), and the lower limit address is stored in the address latch 19. As a result, the address held in the address latch 19 returns to the lower limit address after data transfer related to the upper limit address. In this manner, as shown in FIG. 3, starting from the initial address, address generation is performed that sequentially changes between the lower limit address and the upper limit address.

As described above, according to the present data transfer device,
Providing the address generation circuit 7 for sequentially accessing the buffer unit by specifying the upper and lower limits of the buffer unit address enables burst transfer to a part (one group) of the K buffer units 20 as data transfer destinations. . In addition, by rewriting the address in the address register 12 for the buffer units in different groups, data can be transferred between the buffer units belonging to the group and the transfer destination can be easily switched.

As shown in FIG. 4, an address switching circuit 8 which is switched by a selection signal SEL from the control register 9 may be added to the address register 12. The K buffer units 20 are divided into several groups, and a plurality of sets of initial, lower limit and upper limit addresses for each group are stored in the address register 12, and one of the sets is selected to perform data transfer. Can be easily switched.

The address update request signal CNT may be generated every time a plurality of data are sent, thereby making it possible to respond to packet transfer. Address counter 1
Although the +1 adder 17 is used for 3, a burst transfer in which the address is sequentially reduced from the upper limit to the lower limit can be performed by using a -1 adder.

Next, the configuration of a multiprocessor system using the data transfer device will be described with reference to FIG. In FIG. 5, 5 × 8 (= 40) buffer units (BU) 20 and 5+
Eight (= 13) data transfer control devices 10 are arranged side by side to form a crossbar type data transfer network.
Each of the five row buses 16a is connected to a first data transfer port 31 of a processor element (PE) 30. The eight column buses 16b are connected to the second data transfer port 32 of the processor element 30,
It is connected to the O device 40.

FIG. 6 shows the configuration of one buffer unit (BU) 20 located at the intersection of the row bus 16a and the column bus 16b. Two ports 22, 23 connected to the row bus 16a and the column bus 16b, respectively;
The connection to the FO memory 21 has a path for transferring data in both directions.

Next, a data transfer operation in the multiprocessor system having this configuration will be described. The processor element 30 stores the address register 12 (FIG. 1,
The data is transferred to the buffer unit 20 in the range specified in 2). When each processor element 30 generates an address from 0 to 4, data is mutually transferred between the five processor elements 30. When the address setting is changed for each group of the processor elements 30, data transfer is performed between the groups within the set address range. For example, two processor elements (PE0, 1) set the lower limit address to 0, the upper limit address to 1, and the remaining three processor elements (PE0, 1).
(2,3,4) sets the lower limit address to 2 and the upper limit address to 4
Set to. At this time, the processor element 30
It is divided into two groups, and mutual data transfer within each group is performed. If each processor element (PE0-4) sets the lower limit address to 5 and the upper limit address to 7, and the three I / O devices 40 set the lower limit address to 0 and the upper limit address to 4, the processor element 30 , And data transfer between the I / O device 40 becomes possible.

By such address generation, the number of processor elements and the number of I / O devices can be arbitrarily added and extended, and the data transfer destination can be changed only by changing the address range by software. FIG.
The bidirectional data transfer can be executed by the buffer unit 20 shown in FIG.

As described above, according to the present multiprocessor system, the processor elements 30 are grouped by providing the address generation circuit 7 (FIG. 1) for sequentially accessing by designating the address range, and the mutual Data transfer can be performed. Therefore, the data transfer network can be divided into optimal sizes according to the processing contents, and parallel processing can be performed efficiently. Further, the processor element 30 and the I / O device 40
Data transfer to and from can also be easily performed. In addition, since the address is specified in the address range, network expansion is easy.

Note that eight row buses 16a and five column buses 16b are provided, and three of the eight row buses 1a are provided.
An I / O device 40 may be connected to each of the devices 6a via the data transfer control device 10. Both the number of row buses 16a and the number of column buses 16b are assigned to the processor element 3
A configuration in which the number is larger than 0 is also possible. In this case, data transfer between the I / O device 40 and the two ports 31 and 32 of the processor element 30 is possible.

The data transfer control device 10 shown in FIG. 7 is obtained by adding a common bus interface 42 for connecting the internal bus 15 to the common bus 41 to the configuration shown in FIG. As shown in FIG. 8, for example, three data transfer control devices 10 are connected to one common bus 41, and the common bus 41
Can be connected to five I / O devices 40. According to the configuration of FIG. 8, the expansion of the I / O device becomes easy without expanding the buffer unit of the network.

(Embodiment 2) FIG. 9 shows another example of an address generation circuit in a data transfer control device used in a multiprocessor system. The address counter 13 of the address generation circuit of FIG. 9 includes two +1 adders 17a, 1
7b, the upper selector 18a, and the lower selector 18b
And a 2-bit upper address latch 19a and a 2-bit lower address latch 19b. The high-order selector 18a, in response to the SET1 signal, outputs the high-order 2 bits of the initial address of the address register 12, the high-order 2 bits of the low-order address of the address register 12, and the +1 adder 1
7a is selected from the output of the upper address latch 1
Give to 9a. On the other hand, the lower selector 18 b
According to the signal, one of the lower 2 bits of the initial address of the address register 12, the lower 2 bits of the lower limit address of the address register 12, and the output of the +1 adder 17b is selected and supplied to the lower address latch 19b. Moreover,
Upper address latch 19a and lower address latch 19b
Is independently updated by the CNT1 signal and the CNT2 signal. The output A1 of the upper address latch 19a and the output A2 of the lower address latch 19b are combined to form a 4-bit buffer unit address A.

Next, the data transfer operation between processors in a three-dimensional array by the address generation circuit of FIG. 9 will be described with reference to FIGS. The total number of processor elements 30 is n × n, where n is a constant of a power of two. In the following description, n = 4.

FIG. 10 shows an example of a multiprocessor system when the number of processor elements 30 is 16. 1
The six processor elements 30 store 16 × 16 buffer units 20 in the row bus 16 a and the column bus 1.
6b. In parallel processing in numerical calculation such as fluid analysis, three-dimensional array data representing the state of a fluid is distributed to each processor element 30, and parallel processing is performed while exchanging data between the processor elements 30.

A description will be given of a method of dividing data when the three-dimensional array data is divided into 16 processor elements 30 and processed in parallel.

As shown in FIG. 11A, a 4 × 4 × 4 three-dimensional array is represented by A (1: 4, 1: 4, 1: 4). When dividing the three-dimensional array A into 16 one-dimensional arrays, three types of division methods are possible. FIG.
(B) is a division A (1: 4, / 1: 4,1: 4) in the X direction.
/ (), And FIG. 11 (c) shows a division A (1: 4 /,
1: 4, / 1: 4), and FIG.
(/ 1: 4, 1: 4 /, 1: 4). In each case, one of the 16 one-dimensional arrays is shown in FIG.
It is assigned to 16 processor elements 30 in 0.

In the case of division in the X direction, the virtual processor element array 30 having a two-dimensional arrangement as shown in FIG.
a is assumed. For example, / 4, 1 / of the virtual processor element array 30a has a one-dimensional array A
(1: 4, / 4,1 /) is assigned. Since the actual processor elements 30 (that is, physical processor elements) in FIG. 10 are one-dimensionally arranged, it is necessary to further allocate a virtual processor element to the physical processor element 30b according to FIG. FIG.
The correspondence between the number of the virtual processor element and the number of the physical processor element is shown. Division A in the X direction (1:
4, / J, K /) (J = 1: 4, K = 1: 4), the number / J, K / of the virtual processor element is L =
When (J−1) × 4 + K−1 (1 ≦ J, K ≦ 4), it is assigned to the number L of the physical processor element.

When the three-dimensional array allocated as described above is processed in parallel, one processor element 30 (3
The change in the state of the entire space area cannot be obtained by only one operation on the one-dimensional array in 0b). In order to perform the operation on the entire three-dimensional space area, it is necessary to perform the operation while sequentially changing the division direction. For example, when a partial differential equation is solved by a difference method, ADI (Alterninin) is used.
The g Direction Implicit method is such an operation method.

FIG. 14 shows a processor element 30 (30) for switching from division in the X direction to division in the Y direction.
The state of data transfer during b) is shown. Division A in Y direction
In the case of (I /, 1: 4, / K) (I = 1: 4, K = 1: 4), the virtual processor element numbers / K, I / are
When M = (K−1) × 4 + I−1 (1 ≦ I, K ≦ 4), it is assigned to the number M of the physical processor element.

First, 16 processor elements 30 (30b) each having a one-dimensional array divided in the X direction
The operation of transferring data to the buffer unit 20 via the data transfer control device 10 and the row bus 16a will now be described. For example, the one-dimensional array A (1: 4, / 1, 1) held by the physical processor element 30b of number 1
2 /) are four elements A (1, / 1,2 /), A (2,
/ 1,2 /), A (3,1 / 1,2 /), A (4,1 / 1,
2 /). At this time, the address generation circuit (FIG. 9) of the data transfer control device 10 connected to the physical processor element 30b of No. 1
lower address latch 19b while fixing the content of a to 1
The buffer unit address A
4, 5, 6, and 7 are sequentially generated. This gives 1
The four elements of the dimensional array A (1: 4, / 1,2 /) are distributed and arranged in the four buffer units 20. Data transfer from the physical processor element 30b of another number to the buffer unit 20 is performed in a similar manner.
All the element data of the dimensional array A (1: 4, 1: 4, 1: 4) are distributed and arranged in 64 buffer units 20.

Next, 64 elements each having one element data
From the buffer units 20, the data transfer control device 1
The operation of transferring data to the 16 processor elements 30 (30b) via 0 and the column bus 16b will be described. FIG. 15 shows a state of data transfer to the physical processor element 30b of number 4 to which the one-dimensional array A (1 /, 1: 4, / 2) divided in the Y direction is assigned. The one-dimensional array to be transferred to the physical processor element 30b of number 4 is the element data A (1, //) transferred from the physical processor element 30b of number 1.
1, 2 /) and the physical processor element 30 of number 5
element data A transferred from b (1, / 2,2 /)
And element data A (1, / 3,2 /) transferred from the physical processor element 30b of number 9 and number 1
And the element data A (1, / 4,2 /) transferred from the third physical processor element 30b. Therefore, the address generation circuit (FIG. 9) of the data transfer control device 10 connected to the physical processor element 30b of No. 4 fixes the contents of the lower address latch 19b to 1 while sequentially updating only the upper address latch 19a. As shown in FIG.
1, 5, 9, and 13 are sequentially generated. This allows
The element data distributed and arranged in the four buffer units 20 is collected in the physical processor element 30b of No. 4. The data transfer from the buffer unit 20 to the physical processor element 30b of another number is executed in the same manner, and as a result, the three-dimensional array A (1: 4, 1: 4,
1: 4) are distributed to the 16 physical processor elements 30b while being divided in the Y direction.

As described above, according to the address generation circuit of FIG. 9, by dividing an address into upper and lower parts,
The change of the dividing direction of the three-dimensional array in the multiprocessor system can be realized by burst transfer, and high-speed data transfer is possible.

When the size of the array to be handled is larger than the number of processor elements 30 (30b), one physical processor element 30b shares two or more virtual processor elements. At this time,
Data transfer between the processor elements 30 (30b) can be performed by repeatedly using the address generation circuit of FIG.

(Embodiment 3) In the multiprocessor system of FIG. 10, since the square root n of the total number of the processor elements 30 is a power of 2, the output of the upper address latch 19a in the address generation circuit of FIG. The buffer unit address A can be obtained by assigning the output of the lower address latch 19b to the lower bits.

Next, an example of an address generation circuit applicable to a case where the square root n of the total number of processor elements is not a power of 2 will be described with reference to FIG. The address counter 13 of the address generation circuit of FIG.
7c, a +1 adder 17b, an upper selector 18a,
A lower selector 18b, a 4-bit upper address latch 19a, a 2-bit lower address latch 19b, and a second adder 43 are provided. Address register 12
Holds the increment address in addition to the initial, lower and upper addresses. The first adder 17c outputs the result of addition of the output A1 of the upper address latch 19a and the increment address from the address register 12. Second adder 43
Outputs the result of addition of the output A1 of the upper address latch 19a and the output A2 of the lower address latch 19b as a buffer unit address A. Then, the output A of the second adder 43 and the upper limit address from the address register 12 are input to the first comparator 14, and the output A2 of the lower address latch 19b and the increment address from the address register 12 are input to the second comparator 14. To the comparator 14b. The first and second comparators 14 and 14b output coincidence signals C and Cb, respectively.

For example, in the case of data transfer to the three buffer units 20 at addresses 6, 7, and 8, the increment address in the address register 12 is set to 3 and the contents of the upper address latch 19a are set to 6. The contents of the lower address latch 19b are changed by 0, 1, 2 and 1 while being fixed. As shown in FIG. 18, addresses 1, 4, 7,.
In the case of generating addresses for data transfer from the five buffer units 20 of 10 and 13, the increment address in the address register 12 is set to 3 while the contents of the lower address latch 19b are fixed to 1. The contents of the upper address latch 19a are changed by 0, 3, 6, 9, 12, and 3 at a time.

As described above, according to the address generation circuit of FIG. 17, the two adders 17c and 43 related to the address are used.
Is provided, high-speed burst transfer can be realized even when the square root of the total number of processor elements is not a power of 2.

(Embodiment 4) Next, an example of a multiprocessor system having a two-dimensional arrangement of processor elements will be described. FIG. 19 shows only the buffer unit in the same system, and has a configuration (5 × 8 × 5 configuration) in which five sets of the buffer unit 20 in FIG. 5 are stacked. 5 × 5 row bus and 5 × 5 column bus
5 × 5 processor elements are connected. 5x remaining
5 × 3 I / O devices are connected to the three column buses.

FIG. 20 shows the 5 × 8 of the s-th surface (0 ≦ s ≦ 4).
The connection relationship between the processor elements via the buffer units 20 and the connection relationship between the processor elements and the I / O devices are shown. In this system, 5 in the s plane
The first ports of each of the processor elements (0, s) to (4, s) are connected to the five buses via the row bus 16a, the data transfer control device 10, the buffer unit 20, and the column bus 16b on the s-th surface. It is connected to the second port of each of the processor elements (s, 0) to (s, 4) on the surface. Also, three I / O devices (s, 0) in the s-th plane,
(S, 1) and (s, 2) are connected to the processor element via the buffer unit 20 in the same plane.

In the multiprocessor system having the above configuration, data transfer between the processor elements and data transfer between the processor elements and the I / O device can be performed. The total number of processor elements is n × n
(5 × 5 = 25 in the above example), the total number of buffer units necessary for data transfer between the processor elements is n × n × n (5 × 5 × 5 = 1 in the above example).
25), and the total number of buffer units n × n × n × n (for example, 5 × 5 × 5 ×
5 = 625). Also, I / O devices can be easily connected.

Next, an example in which a common bus for the I / O device as shown in FIG. 8 is introduced into the multiprocessor system shown in FIGS. 19 and 20 will be described. As shown in FIG. 21, the number of 5 × 3 column buses related to the connection of the I / O device is (s, t) (0 ≦ s ≦ 4 and 0 ≦ t ≦ 2), The first common bus 41a is connected to the buses (0,0) to (4,0), and the second group of column buses (0,1) to (4,0).
The first common bus 41b is connected to 1), and the third common bus 41c is connected to the third group of column buses (0, 2) to (4, 2). Then, these three common buses 41a,
41b, 41c, one I / O device (I / O ₀ ,
I / O ₁ , I / O ₂ ) 40 are connected. For example, I / O
_{Since 0} is connected to all row buses on all surfaces via the first common bus 41a, all processor elements can perform data transfer with I / O ₀ via the row bus. . The same applies to I / O ₁ and I / O ₂ . Further, an I / O device can be independently extended for each of the common buses 41a, 41b and 41c, and additional connection to the I / O device is only required if necessary.

As described above, the I / O as shown in FIG.
By introducing a common bus for the devices, one I / O device can be shared by all processor elements. Also, since the buses are grouped, if a failure occurs in an I / O device on one common bus,
Data input / output by I / O devices on another common bus is possible, and the influence of a failure can be reduced.

[0048]

As described above, according to the present invention, the change range of the buffer unit address can be arbitrarily limited, so that the data transfer destinations or the data transfer destinations can be grouped, and the parallelization can be achieved. Efficiency can be increased. Further, by limiting the buffer unit address, any data transfer between the processor elements and any data transfer between the processor elements and the data input / output device can be selected.

Further, since discrete address values can be generated easily and at high speed, a network suitable for a data structure of three or more dimensions can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an address generation circuit in FIG. 1;

FIG. 3 is a diagram illustrating an example of generation of a buffer unit address by the address generation circuit of FIG. 2;

FIG. 4 is a configuration diagram showing a modification of the address generation circuit of FIG. 2;

FIG. 5 is a configuration diagram of a multiprocessor system using the configuration of FIG. 1;

6 is a configuration diagram of one buffer unit in FIG. 5;

FIG. 7 is a configuration diagram showing a modification of the data transfer control device in FIG. 1;

FIG. 8 is a configuration diagram of a multiprocessor system using the data transfer control device of FIG. 7;

FIG. 9 is a configuration diagram illustrating another modification of the address generation circuit of FIG. 2;

10 is a configuration diagram of a multiprocessor system using the configuration of the address generation circuit of FIG. 9 in a data transfer control device.

11A is a diagram illustrating a three-dimensional array to be processed by the multiprocessor system of FIG. 10; FIG.
FIG. 4C is a diagram illustrating division in the direction, FIG. 4C is a diagram illustrating division in the Y direction of the three-dimensional array, and FIG.

FIG. 12 shows the multiprocessor system of FIG. 10;
FIG. 7A is a diagram illustrating a two-dimensional arrangement of virtual processor elements when processing the three-dimensional array of FIG.

FIG. 13 is a diagram showing the correspondence between physical processor element numbers and virtual processor element numbers in FIG. 12;

FIG. 14 is a conceptual diagram showing a state of distribution and collection of data in the multiprocessor system of FIG.

FIG. 15 is a conceptual diagram showing details of data collection by one processor element in FIG. 14;

16 is a diagram illustrating an example of generation of a buffer unit address by the address generation circuit of FIG. 9;

FIG. 17 is a configuration diagram showing still another modification of the address generation circuit of FIG. 2;

18 is a diagram illustrating an example of generation of a buffer unit address by the address generation circuit of FIG. 17;

FIG. 19 shows a two-dimensional arrangement of the buffer units in FIG.
It is a block diagram showing the example extended to the dimensional arrangement.

20 is a diagram illustrating connection of the buffer units on the s-th surface in a multiprocessor system using the buffer units arranged three-dimensionally in FIG. 19;

FIG. 21 is a diagram showing an example in which a common bus similar to that of FIG. 8 is introduced into the multiprocessor system shown in FIGS. 19 and 20.

FIG. 22 is a configuration diagram of a conventional multiprocessor system.

FIG. 23 is a configuration diagram of one buffer unit in FIG. 22;

24 is a configuration diagram of an address generation circuit built in the transmission-side data transfer control device in FIG. 22;

FIG. 25 is a diagram illustrating an example of generation of a buffer unit address (channel number) by the address generation circuit of FIG. 24;

[Explanation of symbols]

 Reference Signs List 6 network interface 7 address generation circuit 8 address switching circuit 9 control register 10 data transfer control device 11 address control circuit (control means) 12 address register (storage means) 13 address counter (update means) 14 comparator (comparison means) 14b comparison Device 15 Internal bus 16 Data transfer bus 17, 17a, 17b +1 Adder 17c Adder 18 Selector 18a Upper selector 18b Lower selector 19 Address latch 19a Upper address latch 19b Lower address latch 20 Buffer unit 21 FIFO memory 30 Processor element 16a Row bus ( 16b Column bus (second data transfer bus) 40 I / O device (data input / output device) 41, 41a to 41c Common bus 42 Common bus Interface 43 Adder A Buffer unit address (channel number) C Match signal CNT Address update request signal SET Address setting signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13 / 14,13 / 28,13 / 36 G06F 15 / 16,15 / 173 H04L 11/20

Claims (29)

(57) [Claims] A buffer unit connected to a common data transfer bus; and a buffer unit address for sequentially selecting an arbitrary number of buffer units from the plurality of buffer units. A data transfer control device for controlling data transfer between the buffer unit selected by the buffer unit address and the data transfer bus, the data transfer control device comprising: Storage means for holding first and second addresses that specify a range of unit addresses; and holding the first address given from the storage means.
Updating means for outputting as the buffer unit address while sequentially updating the held first address; and a buffer unit address output from the updating means coincides with a second address provided from the storage means. A comparing means for outputting a coincidence signal, and sequentially applying an address update request signal to the updating means so as to cause the updating means to execute an address update, and receiving the coincidence signal from the comparing means. A data transfer device, comprising: a control unit for giving an address setting signal to the updating unit so as to set the first address held in the storage unit to the updating unit. 2. The data transfer device according to claim 1, wherein the storage unit has a function of further holding a third address different from the first and second addresses as an initial address. A data transfer apparatus further comprising a function of setting an initial address held by the storage means in the updating means before outputting an address update request signal to the updating means. 3. The data transfer device according to claim 1, wherein said updating means has a function of independently updating an upper part and a lower part of said held first address. apparatus. 4. The data transfer apparatus according to claim 1, wherein said updating means includes means for adding an increment address to said held first address. 5. The data transfer device according to claim 1, wherein the data transfer control device is commonly connected to a data transfer control device of at least one other data transfer device and at least one data input / output device. And a common bus interface means interposed between the common bus and the data transfer bus. 6. Coordinates (x, y), x, y = 0 to N-1
(N ≧ 2), N ² buffer units arranged at two-dimensional lattice points represented by the following, and each of the N ² buffer units is commonly connected to N buffer units arranged in the x direction. N first
And N ^second buffer units commonly connected to N buffer units arranged in the y direction among the N ² buffer units, respectively.
A data transfer bus, 2N data transfer controllers connected to respective ends of the first and second data transfer buses, and the first data transfer of the 2N data transfer controllers A first data transfer port connected to one of the N data transfer controllers connected to an end of the bus;
A second data transfer port connected to one of the N data transfer controllers connected to the end of the second data transfer bus among the 2N data transfer controllers; and a N number of processor elements, wherein each of the 2N data transfer control device, any from among the N buffer units which are commonly connected to the data transfer control device of the N ² pieces of buffer units Storage means for holding first and second addresses specifying a range of buffer unit addresses for sequentially selecting a number of buffer units; holding first addresses provided from the storage means;
Updating means for outputting as the buffer unit address while sequentially updating the held first address; and a buffer unit address output from the updating means coincides with a second address provided from the storage means. A comparing means for outputting a coincidence signal, and sequentially applying an address update request signal to the updating means so as to cause the updating means to execute an address update, and receiving the coincidence signal from the comparing means. Control means for providing an address setting signal to the updating means so as to set the first address held by the storage means in the updating means. 7. The multiprocessor system according to claim 6, wherein said storage means has a function of further holding a third address different from said first and second addresses as an initial address, and said control means A multi-processor system further comprising a function of setting an initial address held by the storage means in the updating means prior to outputting an address update request signal to the updating means. 8. The multiprocessor system according to claim 6, wherein said updating means has a function of independently updating an upper part and a lower part of said held first address. system. 9. The multiprocessor system according to claim 6, wherein said updating means includes means for adding an increment address to said held first address. 10. The multiprocessor system according to claim 6, wherein N (K ≧ 1) additional buffer units are connected to each of said N first or second data transfer buses. And K third data transfer buses commonly connected to N additional buffer units arranged in the y direction or the x direction of the N × K additional buffer units, respectively, and the third data transfer K connected to each end of the bus
A multiprocessor system further comprising a plurality of additional data transfer control devices. 11. The multiprocessor system according to claim 10, further comprising at least one data input / output device connected to said K additional data transfer control devices. 12. The multiprocessor system according to claim 10, wherein L is connected to each of L (L ≧ 2) additional data transfer control device groups obtained by dividing the K additional data transfer control devices. A multiprocessor system further comprising: a plurality of common buses; and M (M ≧ L) data input / output devices connected to at least one of the L common buses. 13. The multiprocessor system according to claim 10, wherein each of the K additional data transfer control devices is commonly connected to the additional data transfer control device among the N × K additional buffer units. Additional storage means for storing first and second addresses for specifying a buffer unit address range for sequentially selecting an arbitrary number of additional buffer units from the N buffer units; and the additional storage means. And an additional updating means for holding the first address given from the buffer unit and outputting the buffered address as the buffer unit address while sequentially updating the held first address; and a buffer unit address output from the additional updating means. An adder for outputting a match signal when the second address provided from the additional storage means matches; An adding / comparing means, an address updating request signal is sequentially given to the additional updating means so as to cause the additional updating means to execute an address update, and the additional storing means holds the output when a matching signal is output from the additional comparing means. A multi-processor system comprising an additional control means for giving an address setting signal to the additional updating means so as to set the first address in the additional updating means. 14. The multiprocessor system according to claim 13, wherein said additional storage means has a function of further holding a third address different from said first and second addresses as an initial address, Means for setting the initial address held by the additional storage means in the additional update means prior to outputting an address update request signal to the additional update means, the multiprocessor system further comprising: . 15. The multiprocessor system according to claim 13, wherein said additional updating means has a function of independently updating an upper part and a lower part of said held first address. Processor system. 16. The multiprocessor system according to claim 13, wherein said additional updating means includes means for adding an increment address to said held first address. 17. The multiprocessor system according to claim 13, wherein each of the K additional data transfer control devices includes at least one other additional data transfer control device and at least one data input / output device. A multiprocessor system further comprising common bus interface means interposed between a common bus connected in common and one of the third data transfer buses. 18. Coordinates (x, y, z), x, y, z = 0
~N-1 (N ≧ 2) , in a 3-dimensional of N ³ pcs arranged at a lattice point buffer unit represented, N number of buffers, each arranged in the x direction among the N ³ pieces of buffer units first data transfer bus of N ² present, which are commonly connected to the unit, each said N ³ pieces of the N aligned in the y direction in the buffer unit buffer unit commonly connected N ² pieces of the second in a data transfer bus, the first and the 2N ² pieces of the data transfer control device connected to each end portion of the second data transfer bus, said first data of said 2N ² pieces of the data transfer control device A first data transfer port connected to one of the N ² data transfer controllers connected to the end of the transfer bus; and a ^second data transfer port of the 2N ² data transfer controllers.
And a N ² pieces of processor elements each having one to a second data transfer ports connected in the connected N ² pieces of the data transfer control device to the end of the data transfer bus, said 2N each of the ^two data transfer control device, the N ³ pieces of buffer units the data transfer control device to the commonly connected the N from the buffer unit any number of buffer units sequentially selected to for Storage means for holding first and second addresses specifying a range of buffer unit addresses; holding first addresses provided from the storage means;
Updating means for outputting as the buffer unit address while sequentially updating the held first address; and a buffer unit address output from the updating means coincides with a second address provided from the storage means. A comparing means for outputting a coincidence signal, and sequentially applying an address update request signal to the updating means so as to cause the updating means to execute an address update, and receiving the coincidence signal from the comparing means. Control means for providing an address setting signal to the updating means so as to set the first address held by the storage means in the updating means. 19. The multiprocessor system according to claim 18, wherein said storage means has a function of further holding a third address different from said first and second addresses as an initial address, and said control means A multi-processor system further comprising a function of setting an initial address held by the storage means in the updating means prior to outputting an address update request signal to the updating means. 20. The multiprocessor system according to claim 18, wherein said updating means has a function of independently updating an upper part and a lower part of said held first address. system. 21. The multiprocessor system according to claim 18, wherein said updating means includes means for adding an increment address to said held first address. 22. The multiprocessor system according to claim 18, wherein each of said N ² first or second data transfer buses has K
N (K ≧ 1) connected N ² × K additional buffer units, and each of the N ² × K additional buffer units is common to N additional buffer units arranged in the y direction or the x direction. N × K third data transfer buses connected to each other; and N × K third data transfer buses connected to respective ends of the third data transfer buses.
A multiprocessor system further comprising × K additional data transfer control devices. 23. The multiprocessor system according to claim 22, further comprising at least one data input / output device connected to said N × K additional data transfer control devices. . 24. The multiprocessor system according to claim 22, wherein said N × K additional data transfer control devices are connected to each of L (L ≧ 2) additional data transfer control device groups. A multiprocessor system further comprising: L common buses; and M (M ≧ L) data input / output devices connected to at least one of each of the L common buses. 25. The multiprocessor system according to claim 22, wherein each of the N × K additional data transfer control devices is common to the additional data transfer control devices among the N ² × K additional buffer units. Additional storage means for holding first and second addresses specifying a buffer unit address range for sequentially selecting an arbitrary number of additional buffer units from the connected N buffer units; and Additional update means for holding a first address given from the additional storage means and outputting the buffered address as the buffer unit address while sequentially updating the held first address; and a buffer unit output from the additional update means A match signal is output when the address matches the second address given from the additional storage means. An additional comparing means, an address updating request signal is sequentially given to the additional updating means so as to cause the additional updating means to execute an address update, and when an additional signal is output from the additional comparing means, the additional storing means A multi-processor system comprising: an additional control unit that supplies an address setting signal to the additional updating unit so as to set the held first address in the additional updating unit. 26. The multiprocessor system according to claim 25, wherein said additional storage means has a function of further holding a third address different from said first and second addresses as an initial address, Means for setting the initial address held by the additional storage means in the additional update means prior to outputting an address update request signal to the additional update means, the multiprocessor system further comprising: . 27. The multiprocessor system according to claim 25, wherein said additional updating means has a function of independently updating an upper part and a lower part of said held first address. Processor system. 28. The multiprocessor system according to claim 25, wherein said additional updating means includes means for adding an increment address to said held first address. 29. The multiprocessor system according to claim 25, wherein each of said N × K additional data transfer control devices includes at least one other additional data transfer control device and at least one data input / output device. A multi-processor system, further comprising common bus interface means interposed between a common bus commonly connected to the third data transfer bus and one of the third data transfer buses.