JPH0526979A - Test simplification circuit - Google Patents

Abstract

PURPOSE:To prevent generation of error at data read-out by investigating change of ampere value flowing in from an electric power source when data expectation value of an internal circuit is applied to predetermined observation points. CONSTITUTION:When correct-or-wrong test of logic level of observation points 1, 2, 3 and so on is perform, expectation value of logic level of each observation point is serially input from a data input terminal 52, being synchronized with clock input from a clock input terminal 53. Subsequently, a test mode switching pin 51 is changed to H level along with monitoring ampere value of electric power source. In this occasion, in the case that logic level of each observation point is the same as each expectation value, the ampere value of electric power source does not change, and, on the other hand, logic level of one or a plurality of observation points differ from each expectation value, excess electric current flows at the observation points and thereby the ampere value of electric power source changes. Accordingly, whether logic level at each observation point shows correct logic level or not, can be tested in that manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test facilitating circuit, and more particularly to a circuit for checking signal levels at various observation points inside a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have become larger and larger, and the necessity of testing whether or not the internal logic circuit is at a normal logic level is becoming more and more important. For example, a matrix observation method is known as a test facilitation circuit that facilitates testing of signal levels at a large number of observation points of the internal circuit.

FIG. 3 is a diagram schematically showing a test facilitation circuit using this matrix observation method. In this test facilitating circuit, the circle of FIG. 3 arranged in the controller 11, the column address selecting circuit 12, the row address selecting circuit 13, and each node (observation point) selected by the both address selecting circuits 12 and 13 is selected. It is composed of a large number of gate circuits 14 as shown in A, and a data receiving circuit 15 for receiving the logic level of each node output from the large number of gate circuits 14.

In each gate circuit 14, one input terminal 20a of the AND gate 20 is connected to the node of the internal circuit corresponding to the gate circuit 14, and the other input terminal 2
0b is connected to the address line selected by the row address selection circuit 13, and the transfer gate 21 connected to the output terminal 20c of the AND gate 20.
Of the transfer gate 21 is connected to the address line selected by the column address selection circuit, and the output side of the transfer gate 21 is connected to the data receiving circuit 15.

The controller 11 also receives a clock input pin 16 for inputting a clock signal, a test mode switching pin 17 for switching between a test mode and a normal operation mode, and an address of a desired node in the internal circuit. The address input pin 18 and the data output pin 19 for outputting the logic level of the node of the address designated by the address input pin 18 are used as dedicated test pins.

In order to observe the logic level of a desired node in the internal circuit using the test facilitation circuit shown in FIG. 3, a predetermined test mode selection signal (for example, an H level signal) is applied to the test mode switching pin 17. ) Is input, and a clock signal is input from the clock input pin 16 and addresses of a desired number of nodes are sequentially input from the address input pin 18. Then, both address selection circuits 12 and 1
A large number of desired nodes are sequentially designated by 3 and signals representing the logical levels of these large numbers of nodes are input to the data receiving circuit 15. The signals representing the logical levels of the large number of nodes are passed through the data output pin 19. Are sequentially taken out. This facilitates testing whether a given node is at a given logic level.

[0007]

However, the above-mentioned test facilitation circuit requires a large-scale test-dedicated circuit, and the data reading side also needs a large-scale circuit such as the data receiving circuit 15. , Before observing the logic level of the desired internal node, it is necessary to confirm that a read error by the circuit on the read side of this data does not occur, so it is necessary to start checking each node of the internal circuit. There is a problem that it is difficult.

An object of the present invention is to solve the above problems and to provide a test facilitating circuit in which an error does not occur when reading data.

[0009]

According to the test facilitation circuit of the present invention for achieving the above object, each output side is connected to a plurality of observation points in an internal circuit, and each output side is kept at high impedance. It is characterized by comprising a plurality of gate circuits capable of switching between an operating mode to be performed and a test mode in which an input side test signal is applied to each of the observation points.

Here, in the test facilitation circuit,
It is preferable to include a serial / parallel conversion circuit that serially inputs a plurality of test signals, converts them into parallel test signals, and inputs each of the parallel test signals into each of the plurality of gate circuits.

[0011]

According to the test facilitation circuit of the present invention, in the conventional test facilitation circuit, it is necessary to confirm the reliability of the circuit on the data read side before observing the logic level of the internal circuit. The circuit on the side was abolished. That is, the present invention refers to an expected value of the data of the internal circuit (an expected signal level that a certain node should be at the H level or the L level if the circuit is complete, without reading the data from the internal circuit). )
Is applied to a certain observation point, the logic level at that observation point is the same as the expected value and the anti-expected value (L level when the expected value is H level, H level when the expected value is L level). It is noted that the current value flowing from the power source changes in the same case as in (1).

In the test facilitating circuit of the present invention, since the plurality of gate circuits are connected to the plurality of observation points (nodes) in the internal circuit, the output of the gate circuit is kept at high impedance, which is a normal condition. The operation is performed, and in the test mode, it is possible to test whether or not there is an error in the internal circuit by applying each expected value from this gate circuit to each observation point and observing the power supply current.
Therefore, in this case, since the data read circuit is unnecessary, it is naturally unnecessary to confirm the reliability of the data read circuit, and the logic level of each observation point of the internal circuit can be checked more easily and accurately than in the conventional case.

When the test facilitating circuit includes the serial / parallel conversion circuit, only three test-dedicated pins are required as shown in an embodiment to be described later. The number is reduced, and the number of pins for exchanging data between the internal circuit and the outside can be increased accordingly. In the above description, it is explained that the expected value is applied to each observation point, but it is not necessary to apply the expected value to each observation point, and the circuit is based on the fact that the power supply current has changed by applying the anti-expected value. Of course, it may be judged that is normal.

[0014]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a diagram showing a test facilitation circuit according to an embodiment of the present invention. The output sides of the tristate buffers 31, 32, 33, ... Are connected to the observation points 1, 2, 3, ... In the internal circuit. Control terminals 31a and 32 of the tristate buffers 31, 32, 33, ...
, 33a, ... Are connected to each other and to the test mode switching pin 51. The input side of each tristate buffer 31, 32, 33, ... Is connected to the Q output terminal of each D-type flip-flop 41, 42, 43 ,. The D input terminal of the D-type flip-flop 41 is connected to the data input pin 52, and the D-type flip-flop 42,
The D input terminals of 43, ... Are connected to the Q output terminals of the adjacent D-type flip-flops 41, 42 ,.
The clock input terminal of each D-type flip-flop 41, 42, 43, ... Is connected to the clock input pin 53. As a result, these D-type flip-flops 41, 4
, 43 constitute the shift register 40 as a whole.

Here, the tristate buffers 31, 3
2, 33, ... are control terminals 31a, 32a,
33a, ..., depending on the signal input to the H side of the input side,
It has a mode for transmitting the L level signal to the output side as it is and a mode for holding the output side in high impedance. Here, an operation mode signal (for example, L level) is input from the test mode switching pin 51. The output sides of the tristate buffers 31, 32, 33, ... Are held at a high impedance by the input of a test mode selection signal (eg, H level) from the test mode switching pin 51.
1, 32, 33, ... Are each D-type flip-flop 41,
The Q outputs of 42, 43, ...
It is in a state of being applied to 3, ....

When testing whether or not each observation point 1, 2, 3 ... Is at the correct logic level using the test facilitating circuit, data input is performed in synchronization with the clock input from the clock input pin 53. The expected value of the logic level of each observation point is serially input from the pin 52. After the input of the expected value is completed, the test mode switching pin 51 is changed to the H level while monitoring the power supply current. At this time, if the logic level of each observation point is as expected, the power supply current does not change, while the logic level of one or more of the observation points is different from each expected value. If so, an extra current is generated at that observation point, which changes the power supply current. Therefore, this makes it possible to test whether the logic level of each observation point indicates the correct logic level. Here, when it is determined that the logic level of each observation point is not according to each expected value, to determine which observation point has the wrong logic level,
It can be examined by applying a voltage to each observation point so that only one of the many observation points has an anti-expected value.

FIG. 2 is a diagram showing a test facilitating circuit according to another embodiment of the present invention. The components corresponding to the components in the embodiment shown in FIG. 1 are assigned the same numbers and symbols as the numbers and symbols shown in FIG. 1, and description of common points is omitted. In this test facilitation circuit, instead of the tristate buffers 31, 32, 33, ... In the test facilitation circuit shown in FIG. 1, the buffers 61, 62, 63 ,. The transfer gates 71, 72, 73, ... Are provided,
The gate terminals 71a, 72a, 73a, ... Of the transfer gates 71, 72, 73 ,.
Connected to 1. The address decoder 81 is connected to the address clock input pin 54, and when the L level signal is continuously input from the address clock input pin 54 for a predetermined time or longer, all the transfer gates 71, 72, 73 ,. Gate terminals 71a, 72
.. are set to L level, whereby the output sides of all of these transfer gates 71, 72, 73, ... Are stored in high impedance, and when a clock pulse is input from the address clock input pin 54, each clock pulse is input. , Gate terminals 71a, 72a, 7 of the transfer gates 71, 72, 73, ...
Of 3a, ..., An H level signal is sequentially applied to each one gate terminal.

When the test facilitating circuit shown in FIG. 2 is used to test whether the observation points 1, 2, 3, ... Are at the correct logic level, the address clock input pin 5 is used.
While keeping 4 at the L level, a clock is input from the clock input pin 53, and the expected logical level of each observation point is serially input from the data input pin 52 in synchronization with the input of this clock. After the input of the expected value is completed, the clock signal is input from the address clock input pin 54 while monitoring the power supply current. If the power supply current does not change even if this clock signal is input, each observation point is at the correct logic level, and if the power supply current changes when a predetermined number of clock pulses are input, the observation point corresponding to this predetermined number. There is an error in the logic level of. As described above, a large number of observation points may be sequentially tested. Although the expected value is input here, it may be determined that the logic level of the observation point is wrong by inputting the anti-expected value and not changing the power supply voltage.

In each of the above embodiments, the expected value (or anti-expected value)
However, the present invention is not limited to serially inputting an expected value (or an anti-expected value). For example, when the number of observation points is relatively small, The circuit may be configured so that each expected value of 1 is input in parallel. However, when the circuit is configured to input the expected value (or the anti-expected value) serially as shown in each of the above embodiments, the number of dedicated test pins is smaller than that in the conventional example (see FIG. 3) described above. Therefore, the number of pins that can be effectively used for exchanging data between the internal circuit and the external circuit increases accordingly.

In each of the above embodiments, the tristate buffer and the combination of the buffer and the transfer gate are used as an example of the "gate circuit" according to the present invention.
It goes without saying that the gate circuit according to the present invention is not limited to these.

[0021]

As described above, in the test facilitation circuit of the present invention, each output side is connected to each of a plurality of observation points in the internal circuit, and the operation mode in which each output side is held at high impedance and Equipped with multiple gate circuits that can be switched to the test mode in which the test signal on the input side is applied to each observation point, a circuit for reading the data at the time of test is not required, and an error caused by this circuit occurs A test facilitation circuit that does not need to be performed is realized.

In the present invention, a plurality of test signals are serially input, converted into parallel test signals, and the parallel test signals are input to a plurality of gate circuits, respectively. When the conversion circuit is provided, the number of test-dedicated pins is smaller than in the conventional case, and therefore the number of pins for exchanging data between the internal circuit and the external circuit in the normal operating state can be increased accordingly.

[Brief description of drawings]

FIG. 1 is a diagram showing a test facilitation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a test facilitation circuit according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a conventional test facilitation circuit using a matrix observation method.

[Explanation of symbols]

1, 2, 3 observation points 31, 32, 33 tristate buffers, 40 shift register 41, 42, 43 D-type flip-flops 61, 62, 63 buffers 71, 72, 73 Transfer gate 81 Address decoder

Claims (2)

[Claims] 1. An operation mode in which each output side is connected to a plurality of observation points in an internal circuit, each output side is maintained in high impedance, and a test in which an input side test signal is applied to each observation point. A test facilitating circuit having a plurality of gate circuits capable of switching between modes. 2. A serial-parallel conversion circuit for serially inputting a plurality of test signals, converting them into parallel test signals, and inputting each of the parallel test signals into each of the plurality of gate circuits. The test facilitation circuit according to claim 1, wherein