JPH05267483A - Carrier board for integrated circuit package - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding the improvement of carriers for integrated circuit packages used for carrying and testing integrated circuit packages, the width is extremely narrow, the number is increasing, and the pitch is extremely narrow. An object of the present invention is to provide a carrier for an integrated circuit package, which enables mounting of an integrated circuit package having a broken lead. [Construction] A carrier for an integrated circuit package, which is used for carrying or carrying an integrated circuit package on which a semiconductor chip is mounted, wherein when carrying out a test of this semiconductor chip, the leads of this integrated circuit package are A first slit 1a is provided at a cutting position, a second slit 1b is provided at a position inside the first slit 1a for cutting the lead before using the integrated circuit package, and an outside of the second slit 1b. On one side, an adhesive application area 1c for adhering the tie bar and the lead of this integrated circuit package is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved carrier for an integrated circuit package which is used to carry and test the integrated circuit package.

In an integrated circuit package for mounting a highly integrated semiconductor chip, the lead width is extremely narrow, the number of leads is increasing, and the pitch is extremely narrow. In a carrier for an integrated circuit package used for carrying or carrying an integrated circuit package having such a lead and carrying out a test, the width of the lead receiving portion for inserting the lead of the integrated circuit package becomes extremely narrow, The increasing number and extremely narrow pitch make it extremely difficult to manufacture carriers for integrated circuit packages, and it is also difficult to insert leads accurately into the lead receiving portion.

Under the circumstances as described above, a carrier for an integrated circuit package that can easily mount an integrated circuit package having leads whose number is extremely narrowed and whose width is extremely narrowed. Is required.

[0004]

2. Description of the Related Art A conventional carrier for an integrated circuit package will be described in detail with reference to FIG. FIG. 5 is a diagram showing a state in which an integrated circuit package is mounted on a carrier for a conventional integrated circuit package.

A conventional carrier for an integrated circuit package is provided with a lead receiving portion 11a as shown in FIG. 5, and the lead 2b of the integrated circuit package 2 is inserted into the lead receiving portion 11a to mount the integrated circuit package 2 thereon. Eleven.

In a flat type integrated circuit package having a high degree of integration and a large number of leads, the width of the leads 2b is narrowed to 0.2 mm and the pitch of the leads 2b is set to 0.
Since it is 5 mm, the lead receiving portion 11a of the carrier 11
The width of the carrier is 0.3 mm and the pitch is 0.5 mm.
Has become very difficult to manufacture.

Even if the carrier 11 having such a fine dimension can be managed by some means, it is very difficult to correctly insert the large number of leads 2b into the lead receiving portion 11a and mount the integrated circuit package 2 on the carrier 11. Even if it can be mounted somehow, there is a problem that the lead 2b is deformed when the test terminal is brought into contact with it during transportation or during a test.

[0008]

In the conventional carrier for an integrated circuit package described above, the width of the leads of the integrated circuit package becomes extremely narrow, the number of leads increases, and the pitch becomes extremely narrow. However, there is a problem that it is extremely difficult to manufacture a carrier for an integrated circuit package that mounts such an integrated circuit package. When the integrated circuit package is mounted on the carrier for this integrated circuit package, as shown in FIG. ) Lead as shown in
2b and the bottom of the lead receiving portion 11a of the carrier 11 may not come into close contact with each other.
Hold the tip of the lead 2b as shown in Fig. 6 (b).
However, there is a problem in that the contact between the test terminal 3 and the lead 2b becomes unstable due to the deformation.

Under the circumstances as described above, the present invention can be used for an integrated circuit package having an extremely narrow width and an increased number of leads and an extremely narrow pitch. The purpose is to provide a carrier of.

[0010]

A carrier board for an integrated circuit package according to the present invention is a carrier for an integrated circuit package used for carrying an integrated circuit package having a semiconductor chip mounted thereon for carrying or testing. A first slit is provided at a position where the leads of the integrated circuit package are cut when the semiconductor chip is tested, and the first slit is provided at a position inside the first slit where the leads are cut before using the integrated circuit package. A second slit is provided, and an adhesive application area for adhering the tie bar and the lead of the integrated circuit package is provided outside the second slit.

[0011]

That is, according to the present invention, the positioning pin holes of the integrated circuit package carrier board are aligned with the positioning pin holes of the integrated circuit package, and the tie bars and leads of the integrated circuit package are applied to the carrier board. It is adhered to the carrier board for integrated circuit package by the adhesive applied to the area and conveyed, and before conducting the test, the lead having a size slightly narrower than the width of the first slit is cut in the first slit. A test terminal is contacted with the lead separated from the tie bar and the test is performed. Before using the integrated circuit package, a lead having a size slightly narrower than the width of the second slit is used in the second slit. Since the adhesive is applied only to the outside of the second slit because it is cut and removed, the integrated circuit package is integrated into the integrated circuit. It is possible to remove from the carrier board for the package.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. 1 is a diagram showing a carrier board for an integrated circuit package according to an embodiment of the present invention, and FIG. 2 is a diagram showing a state in which an integrated circuit package is attached and mounted on a carrier board for an integrated circuit package according to an embodiment of the present invention. FIG. 3 is a diagram showing a state in which an integrated circuit package of one embodiment according to the present invention is tested, and FIG. 4 is a diagram showing a carrier board for an integrated circuit package according to one embodiment of the present invention with the integrated circuit package removed. Is.

A carrier board for an integrated circuit package according to an embodiment of the present invention is a carrier for mounting and mounting an integrated circuit package on which a semiconductor chip is mounted for carrying or testing.

As shown in FIG. 1, the carrier board 1 for this integrated circuit package has an adhesive application area 1 from the outer edge.
The carrier board 1 has c, a first slit 1a, a coating region 1d, a second slit 1b, and a pin hole 1e which is aligned with a pin hole for positioning a tie bar of an integrated circuit package.

As shown in FIG. 2, when the integrated circuit package 2 is attached to the carrier board 1 by aligning the pin holes 1e of the carrier board 1 with the pin holes 2c of the integrated circuit package 2, the tie bar 2a is attached to the carrier board 1. The coating area 1c is provided at a position to be attached to the integrated circuit package, and the first slit 1a is provided at a position where the lead 2b of the integrated circuit package 2 is cut before the semiconductor chip mounted on the integrated circuit package 2 is tested. Before using the package 2, place the lead 2b of the integrated circuit package 2 at a position where the lead 2b is cut.
A slit 1b is provided.

Since such an integrated circuit package 2 is mounted by being attached to the carrier board 1, both the tie bar 2a and the leads 2b are securely fixed to the carrier board 1, so that the leads 2b are not deformed during transportation.

Before testing the semiconductor chip mounted on the carrier board 1, as shown in FIG. 3, the first slit 1a is formed.
Inside the lead 2b, which is slightly narrower than the width of the first slit 1a
Cut off and remove, and make the test by contacting the test terminal with the contact point of the test terminal marked with a small circle in the figure.

Since the lead 2b is partially cut but is attached to the coating area 1d, the lead 2b is not deformed even if it is stored and transported in this state. Immediately before using the integrated circuit package 2 in the customer's assembling process, as shown in FIG.
Leads that are slightly narrower than the width of the second slit 1b within 1b
When 2b is cut off and removed, the adhesive is not applied to the surface of the carrier board 1 inside the second slit 1b.
It can be detached from and used.

[0019]

As is apparent from the above description, according to the present invention, an integrated circuit package is adhered and fixed to a carrier board for an integrated circuit package having an extremely simple structure so that the leads are not deformed. It is possible to provide a carrier board for an integrated circuit package, which has an advantage that the package can be transported and tested, and which can be expected to have a remarkable economic effect and reliability improvement effect.

[Brief description of drawings]

FIG. 1 is a diagram showing a carrier board for an integrated circuit package according to an embodiment of the present invention,

FIG. 2 is a diagram showing a state in which an integrated circuit package is attached and mounted on a carrier board for an integrated circuit package according to an embodiment of the present invention;

FIG. 3 is a diagram showing a state in which an integrated circuit package according to an embodiment of the present invention is tested.

FIG. 4 is a diagram showing a carrier board for an integrated circuit package according to an embodiment of the present invention with an integrated circuit package removed,

FIG. 5 is a diagram showing a state in which an integrated circuit package is mounted on a carrier for a conventional integrated circuit package,

FIG. 6 is a diagram showing a problem of a carrier for a conventional integrated circuit package,

[Explanation of symbols]

1 is a carrier board, 1a is a first slit, 1b is a second slit, 1c is a coating area, 1d is a coating area, 1e is a pin hole, 2e is an integrated circuit package, 2a is a tie bar, 2b is a lead, and 2c is a pin hole. ,

Claims (1)

[Claims] 1. A carrier for an integrated circuit package, which is used for carrying or carrying an integrated circuit package on which a semiconductor chip is mounted, for carrying or testing, the carrier for the integrated circuit package being tested. A first slit (1a) is provided at a position where the lead is cut, and a second slit (1b) is provided at a position inside the first slit (1a) where the lead is cut before using the integrated circuit package. A carrier board for an integrated circuit package, wherein an application area (1c) of an adhesive for adhering the tie bar and the lead of the integrated circuit package is provided outside the second slit (1b).