JPH05267334A - Manufacture of integrated circuit device - Google Patents
Manufacture of integrated circuit deviceInfo
- Publication number
- JPH05267334A JPH05267334A JP5866692A JP5866692A JPH05267334A JP H05267334 A JPH05267334 A JP H05267334A JP 5866692 A JP5866692 A JP 5866692A JP 5866692 A JP5866692 A JP 5866692A JP H05267334 A JPH05267334 A JP H05267334A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- polycrystalline silicon
- type
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路装置の製造方
法に関し、特にゲート・オーバーラップ型のＬＤＤ構造
を有するＭＯＳトランジスタの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an integrated circuit device, and more particularly to a method of manufacturing a MOS transistor having a gate overlap type LDD structure.
【０００２】[0002]
【従来の技術】１９８７年１２月のインターナショナル
・エレクトロン・デバイス・ミーテイグの予稿集３８−
４１ページ（Ｐｒｏｃ．Ｉｎｔｌ．Ｅｌｅｃｔｒｏｎ．
Ｄｅｖｉｃｅｓ Ｍｅｅｔｉｎｇ，ＰＰ．３８−４１
（Ｄｅｃ．１９８７））に報告されたゲート・オーバー
ラップ型のＬＤＤ構造（“ＧＯＬＤ”型と呼ばれてい
る）を有するＭＯトランジスタの従来の製造方法につい
て、図２を参照して説明する。2. Description of the Related Art Proceedings of International Electron Device Meeting in December 1987 38-
Page 41 (Proc. Intl. Electron.
Devices Meeting, PP. 38-41
(Dec. 1987)), a conventional method for manufacturing an MO transistor having a gate-overlap type LDD structure (referred to as "GOLD" type) will be described with reference to FIG.
【０００３】Ｐ型のシリコン基板１の主表面上に選択的
に素子分離用のフィールド酸化膜２，ゲート酸化膜４を
形成し、燐がドープされた第１の多結晶シリコン膜５を
全面に形成し、その表面に自然酸化膜６を形成する。次
に、全面に燐がドープされた第２の多結晶シリコン膜を
形成する。続いて、自然酸化膜６をエッチング・ストッ
パーとしたフォトリソグラフィにより、第２の多結晶シ
リコン膜を所望の形状に加工して、多結晶シリコン膜７
を形成する。次に、燐をイオン注入し、Ｎ型の低濃度層
８を形成する〔図２（ａ）〕。A field oxide film 2 and a gate oxide film 4 for element isolation are selectively formed on the main surface of a P type silicon substrate 1, and a phosphorus-doped first polycrystalline silicon film 5 is formed on the entire surface. Then, the native oxide film 6 is formed on the surface. Next, a second polycrystalline silicon film doped with phosphorus is formed on the entire surface. Then, the second polycrystalline silicon film is processed into a desired shape by photolithography using the natural oxide film 6 as an etching stopper, and the polycrystalline silicon film 7 is formed.
To form. Next, phosphorus is ion-implanted to form the N type low concentration layer 8 [FIG. 2 (a)].
【０００４】全面に、ＣＶＤ法により２酸化シリコン膜
を堆積し、ＲＩＥを行い、多結晶シリコン膜７の側面に
２酸化シリコン膜からなるサイドウオール９を形成す
る。この工程で、自然酸化膜６は自然酸化膜６ａとなる
〔図２（ｂ）〕。A silicon dioxide film is deposited on the entire surface by a CVD method and RIE is performed to form a side wall 9 of the silicon dioxide film on the side surface of the polycrystalline silicon film 7. In this step, the natural oxide film 6 becomes the natural oxide film 6a [FIG. 2 (b)].
【０００５】多結晶シリコン膜７およびサイドウオール
９とをマスクとした第１の多結晶シリコン膜５のエッチ
ングを行ない、多結晶シリコン膜５ａを形成する〔図２
（ｃ）〕。“ＧＯＬＤ”型のゲート電極は、多結晶シリ
コン膜７，５ａ（および自然酸化膜６ａ，サイドウオー
ル９）から構成される。The first polycrystalline silicon film 5 is etched by using the polycrystalline silicon film 7 and the side walls 9 as a mask to form a polycrystalline silicon film 5a [FIG. 2].
(C)]. The "GOLD" type gate electrode is composed of the polycrystalline silicon films 7 and 5a (and the natural oxide film 6a and the sidewall 9).
【０００６】砒素のイオン注入，アニールを行ない、Ｎ
型の高濃度層１０を形成する〔図２（ｄ）〕。その後、
公知の方法により、層間絶縁膜，コンタクトホール，配
線金属の形成を行ない、従来の“ＧＯＬＤ”型の集積回
路装置が形成される。Arsenic ion implantation and annealing are performed, and N
The high concentration layer 10 of the mold is formed [FIG. 2 (d)]. afterwards,
The conventional "GOLD" type integrated circuit device is formed by forming an interlayer insulating film, a contact hole, and a wiring metal by a known method.
【０００７】[0007]
【発明が解決しようとする課題】上述した従来のＧＯＬ
Ｄ型のＭＯＳトランジスタの製造方法では、ソース・ド
レインの高濃度層がゲート電極とセルフアラインのイオ
ン注入により形成される。従って、その後の熱処理で高
濃度層を形成する不純物が拡散し、その結果、ゲート電
極と高濃度層とがオーバーラップしてしまう。DISCLOSURE OF THE INVENTION The conventional GOL described above
In the method of manufacturing a D-type MOS transistor, high-concentration layers of source / drain are formed by self-aligned ion implantation with a gate electrode. Therefore, the subsequent heat treatment diffuses the impurities forming the high-concentration layer, and as a result, the gate electrode and the high-concentration layer overlap.
【０００８】このオーパーラップにより、 （１）ゲート−ドレイン間，ゲート−ソース間の寄生容
量が増大し、デバイスの動作スピードを低下させる。 （２）オーバーラップ部で、バンド間トンネリングが生
じる。という問題点がある。Due to this overlap, (1) the parasitic capacitance between the gate and the drain and between the gate and the source is increased, and the operation speed of the device is reduced. (2) Band-to-band tunneling occurs at the overlap portion. There is a problem.
【０００９】[0009]
【課題を解決するための手段】本発明の集積回路装置の
製造方法では、ゲート・オーバーラップ型のＬＤＤ構造
を有するＭＯＳトランジスタのゲート電極長を決定する
ためのサイドウオールとソース・ドレインとなる高濃度
層を形成するためのサイドウオールとをそれぞれ別々に
形成し、別々に使用する。In the method of manufacturing an integrated circuit device according to the present invention, a sidewall and a source / drain for determining a gate electrode length of a MOS transistor having a gate overlap type LDD structure are used. Sidewalls for forming the concentration layer are separately formed and used separately.
【００１０】[0010]
【実施例】本発明の一実施例について、図１を参照して
説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.
【００１１】Ｐ型のシリコン基板１の主表面上に、選択
酸化法（ＬＯＣＯＳ）により素子分離領域に６００〜１
０００ｎｍの膜厚のフィールド酸化膜２を形成する。次
に、７００〜９００℃の乾燥酸素の雰囲気で１０〜２５
ｎｍの膜厚のゲート酸化膜４を形成する。ＧＯＬＤ型の
ゲート電極の下層ゲート電極の構成材料となる燐がドー
プされた５０〜１００ｎｍのＮ型の第１の多結晶シリコ
ン膜５を形成する。多結晶シリコン膜５の表面に、１〜
１０ｎｍの膜厚の自然酸化膜６を形成する。ＧＯＬＤ型
のゲート電極の上層ゲート電極の構成材料となる燐がド
ープされた１００〜２００ｎｍの膜厚のＮ型の第２の多
結晶シリコンを、ＬＰＣＶＤ法により堆積する。On the main surface of the P type silicon substrate 1, element isolation regions 600 to 1 are formed by selective oxidation (LOCOS).
A field oxide film 2 having a film thickness of 000 nm is formed. Next, in an atmosphere of dry oxygen at 700 to 900 ° C. for 10 to 25
A gate oxide film 4 having a film thickness of nm is formed. A phosphorus-doped N-type first polycrystalline silicon film 5 of 50 to 100 nm, which is a constituent material of a lower gate electrode of the GOLD type gate electrode, is formed. 1 to the surface of the polycrystalline silicon film 5
A natural oxide film 6 having a film thickness of 10 nm is formed. Phosphorus-doped N-type second polycrystalline silicon having a film thickness of 100 to 200 nm, which is a constituent material of the upper gate electrode of the GOLD type gate electrode, is deposited by the LPCVD method.
【００１２】フォトリソグラフィにより、第２の多結晶
シリコン膜をドライエッチングし、多結晶シリコン膜７
を形成する。弗素，あるいは塩素を含んだガスによりこ
のドライエッチングを行なうと、第２の多結晶シリコン
膜と自然酸化膜６との選択比が十分に得られ、自然酸化
膜６がエッチング・ストッパーとなる。燐を３０〜１０
０ｋｅＶ，５×１０13〜３×１０13ｃｍ-2イオン注入
し、Ｎ型の低濃度層８を形成する〔図１（ａ）〕。The second polycrystalline silicon film is dry-etched by photolithography to remove the polycrystalline silicon film 7.
To form. When this dry etching is performed with a gas containing fluorine or chlorine, a sufficient selection ratio between the second polycrystalline silicon film and the natural oxide film 6 is obtained, and the natural oxide film 6 serves as an etching stopper. 30 to 10 phosphorus
Ion implantation is performed at 0 keV and 5 × 10 13 to 3 × 10 13 cm −2 to form the N-type low concentration layer 8 (FIG. 1A).
【００１３】ＬＰＣＶＤ法により１００〜２００ｎｍの
膜厚の窒化シリコン膜を堆積する。の窒化シリコ膜に対
して弗素を含むガス系によりＲＩＥを行い、多結晶シリ
コン膜７の側面に第１のサイドウオール９ａを形成す
る。多結晶シリコン膜７および第１のサイドウオール９
ａをマスクとし、弗素，あるいは塩素を含むガス系によ
り、自然酸化膜６，多結晶シリコン膜５を順次ドライエ
ッチングする。これにより、自然酸化膜６ａ，多結晶シ
リコン膜５ａが形成される。熱燐酸により、第１のサイ
ドウオール９ａを選択的に除去する〔図１（ｂ）〕。A silicon nitride film having a thickness of 100 to 200 nm is deposited by the LPCVD method. RIE is performed on the silicon nitride film of No. 2 by a gas system containing fluorine to form the first sidewall 9a on the side surface of the polycrystalline silicon film 7. Polycrystalline silicon film 7 and first sidewall 9
Using a as a mask, the natural oxide film 6 and the polycrystalline silicon film 5 are sequentially dry-etched by a gas system containing fluorine or chlorine. As a result, the natural oxide film 6a and the polycrystalline silicon film 5a are formed. The first side wall 9a is selectively removed by hot phosphoric acid [FIG. 1 (b)].
【００１４】ＬＰＣＶＤ法により、１００〜２００ｎｍ
の膜厚の２酸化シリコン膜を堆積し、弗素を含むガス系
によりこの２酸化シリコン膜に対してＲＩＥを行い、第
２のサイドウオール１１を形成する〔図１（ｃ）〕。本
実施例のゲート電極は、下層ゲート電極であるＮ型の多
結晶シリコン膜５ａ，上層ゲート電極であるＮ型の多結
晶シリコン膜７（および自然酸化膜６ａ，第２のサイド
ウオール１１）から構成される。100-200 nm by LPCVD method
A silicon dioxide film having a thickness of 2 is deposited, and RIE is performed on the silicon dioxide film with a gas system containing fluorine to form the second sidewall 11 [FIG. 1 (c)]. The gate electrode of this embodiment is formed from the N-type polycrystalline silicon film 5a which is the lower layer gate electrode, the N-type polycrystalline silicon film 7 which is the upper layer gate electrode (and the natural oxide film 6a, the second sidewall 11). Composed.
【００１５】砒素を２０〜７０ｋｅＶ，１〜５×１０15
ｃｍ-2イオン注入し、シリコン基板１の表面にＮ型の高
濃度層１０ａを形成する〔図１（ｄ）〕。以下は、通常
のプロセスと同一である。ＣＶＤ法によりＢＰＳＧ膜を
６００〜８００ｎｍ成長し、８５０〜９００℃の窒素雰
囲気で２０〜４０分間のリフローを行う。フォトリソグ
ラフィにより、コンタクトホールを開孔する。厚さ０．
６〜１．０μｍのシリコン入りアルミニウム膜をスパッ
タし、フォトリソグラフィにより配線金属のパターニン
グを行う。Arsenic is added at 20 to 70 keV, 1 to 5 × 10 15
cm −2 ions are implanted to form an N-type high concentration layer 10a on the surface of the silicon substrate 1 [FIG. 1 (d)]. The following is the same as the normal process. A BPSG film is grown to a thickness of 600 to 800 nm by the CVD method, and reflow is performed in a nitrogen atmosphere at 850 to 900 ° C. for 20 to 40 minutes. A contact hole is opened by photolithography. Thickness 0.
An aluminum film containing silicon having a thickness of 6 to 1.0 μm is sputtered, and a wiring metal is patterned by photolithography.
【００１６】[0016]
【発明の効果】以上説明したように本発明は、ゲート・
オーバーラップ型のＬＤＤ構造（逆Ｔ字型のゲート電
極）を有するＭＯＳトランジスタの製造方法において、
ゲート電極長を決定するためのサイドウオールと、高濃
度層を形成するためのサイドウオールとを別々にするこ
とにより、ゲート電極とソースあるいはドレインとのオ
ーバーラップをゼロにできる。As described above, according to the present invention, the gate
In a method of manufacturing a MOS transistor having an overlap type LDD structure (inverted T-shaped gate electrode),
By separating the side wall for determining the gate electrode length and the side wall for forming the high concentration layer, the overlap between the gate electrode and the source or drain can be zero.
【００１７】この結果、従来の逆Ｔ字型ゲート電極を有
するＭＯＳトランジスタの欠点である寄生容量の増大，
およびバンド間トンネリングの発生という問題を解決
し、この構造のＭＯＳトランジスタの性能をさらに向上
させることが可能である。As a result, increase in parasitic capacitance, which is a drawback of the conventional MOS transistor having an inverted T-shaped gate electrode,
It is possible to solve the problem of occurrence of band-to-band tunneling and further improve the performance of the MOS transistor having this structure.
【図１】本発明の一実施例を説明するための工程順の断
面図である。FIG. 1 is a cross-sectional view in process order for explaining an embodiment of the present invention.
【図２】従来の集積回路装置の製造方法を説明するため
の工程順の断面図である。2A to 2D are cross-sectional views in order of processes for explaining a conventional method for manufacturing an integrated circuit device.
１ Ｐ型のシリコン基板 ２ フィールド酸化膜 ３ Ｐ型のチャネル・ストッパー ４ ゲート酸化膜 ５，５ａ，７ Ｎ型の多結晶シリコン膜 ６，６ａ 自然酸化膜 ８ Ｎ型の低濃度層 ９，９ａ，１１ サイドウオール １０，１０ａ Ｎ型の高濃度層 1 P-type silicon substrate 2 Field oxide film 3 P-type channel stopper 4 Gate oxide film 5, 5a, 7 N-type polycrystalline silicon film 6, 6a Natural oxide film 8 N-type low concentration layer 9, 9a, 11 Sidewall 10,10a N type high concentration layer
Claims (2)
的にフィールド酸化膜，ゲート酸化膜を形成する工程
と、 全面にＮ型の多結晶シリコン膜を堆積し、前記多結晶シ
リコン膜表面に自然酸化膜を形成し、全面に導伝体膜を
形成する工程と、 フォトリソグラフィにより、前記導伝体膜を所望の形状
にパターニングする工程と、 イオン注入により、前記シリコン基板の表面にＮ型の低
濃度層を形成する工程と、 全面に第１の絶縁膜を堆積し、ＲＩＥエッチバックによ
り、該導伝体膜の側面に前記第１の絶縁膜からなる第１
のサイドウオールを形成する工程と、 該導伝体膜および前記第１のサイドウオールをマスクに
して前記自然酸化膜および前記多結晶シリコン膜を順次
エッチングする工程と、 前記第１のサイドウオールを除去し、全面に第２の絶縁
膜を堆積し、ＲＩＥエッチバックにより、該導伝体膜の
側面，該自然酸化膜の側面，該多結晶シリコン膜の側
面，並びに前記第１のサイドウオールにより覆われてい
た該自然参加膜の上面を覆う前記第２の絶縁膜からなる
第２のサイドウオールを形成する工程と、 イオン注入により、前記シリコン基板の表面にＮ型の高
濃度層を形成する工程と、 全面に層間絶縁膜を堆積する工程と、 コンタクトホールを開孔する工程と、 配線金属を形成する工程と、 を有することを特徴とする集積回路装置の製造方法。1. A step of selectively forming a field oxide film and a gate oxide film on one main surface of a P-type silicon substrate, and an N-type polycrystalline silicon film is deposited on the entire surface to form the polycrystalline silicon film. A step of forming a natural oxide film on the surface and forming a conductive film on the entire surface; a step of patterning the conductive film into a desired shape by photolithography; and a step of ion implantation on the surface of the silicon substrate. A step of forming an N-type low-concentration layer and a step of depositing a first insulating film on the entire surface and performing RIE etch back to form a first insulating film on the side surface of the conductive film.
The step of forming the sidewalls of the above, the step of sequentially etching the natural oxide film and the polycrystalline silicon film using the conductor film and the first sidewall as a mask, and the removal of the first sidewall Then, a second insulating film is deposited on the entire surface, and the side surface of the conductive film, the side surface of the natural oxide film, the side surface of the polycrystalline silicon film, and the first side wall are covered by RIE etchback. Forming a second sidewall made of the second insulating film covering the upper surface of the naturally participating film, and forming an N-type high concentration layer on the surface of the silicon substrate by ion implantation And a step of depositing an interlayer insulating film on the entire surface, a step of forming a contact hole, and a step of forming a wiring metal, a method of manufacturing an integrated circuit device.
ることを特徴とする請求項１記載の集積回路装置の製造
方法。2. The method of manufacturing an integrated circuit device according to claim 1, wherein the first insulating film is a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5866692A JPH05267334A (en) | 1992-03-17 | 1992-03-17 | Manufacture of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5866692A JPH05267334A (en) | 1992-03-17 | 1992-03-17 | Manufacture of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05267334A true JPH05267334A (en) | 1993-10-15 |
Family
ID=13090914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5866692A Withdrawn JPH05267334A (en) | 1992-03-17 | 1992-03-17 | Manufacture of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05267334A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7550357B2 (en) | 2006-03-07 | 2009-06-23 | Oki Semiconductor Co., Ltd. | Semiconductor device and fabricating method thereof |
-
1992
- 1992-03-17 JP JP5866692A patent/JPH05267334A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7550357B2 (en) | 2006-03-07 | 2009-06-23 | Oki Semiconductor Co., Ltd. | Semiconductor device and fabricating method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |