JPH05256910A - Testing circuit - Google Patents

Abstract

PURPOSE:To measure the DC at an external terminal readily in a testing circuit in a semiconductor integrated circuit. CONSTITUTION:This circuit is constituted of an X-stage counter 1, a test control part 2 and a switch comprising transfer gates IT1, IT2, OT1 and OT2. The X-stage counter 1 receives pulses from the outside and counts the pulses. Output signals Q1, Q2-QX are inputted into the test control part 2. The test control part 2 outputs control signals M1, M2, Mn and Mn+1 for setting the test. With the control signals M1, M2, Mn and Mn+1, the output destination of an external input buffer and the input destination of the an external output buffer are switched to an external input/output terminal DM from an inner circuit 3.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to test circuits, and more particularly to
The present invention relates to a test circuit for a semiconductor integrated circuit (hereinafter referred to as an internal circuit).

[0002]

2. Description of the Related Art A conventional example of this type of test circuit is shown in FIG. This test circuit is used to test the internal circuit 3 which performs a predetermined operation, and is usually integrated with the internal circuit and integrated into a semiconductor. In this case, the internal circuit 3
Is a plurality of external input terminals I1, I2 and external output terminal O
1, O2, and an external input / output terminal IO. Of these, the external input / output terminal IO is selectively used as an input terminal of an input signal or an output terminal of an output signal. In this relationship, the external input / output terminal IO is an input side buffer (hereinafter,
It is connected to the internal circuit 3 via an input side) and an output side buffer (hereinafter, simply referred to as an output side), both input / output sides are switched by a switch, and the external input / output terminal IO is selectively selected. It is configured so that it can be used as an input terminal or an output terminal.

A test circuit for testing such an internal circuit 3 comprises a test control section 2 having external test signal input terminals S1, S2 to Sn and control signal terminals connected to the internal circuit 3.
have.

When the internal circuit 3 is tested by using the test control unit 2, test signals are input to the external test signal input terminals S1, S2 to Sn to control signals M1, M2, M3 to Mm.
Is output to the internal circuit 3 via the control signal terminal. At the time of this test, the internal circuit 3 is supplied with input signals from the input sides of the external input terminals I1 and I2 and the external input / output terminal IO, and from the output sides of the external output terminals O1 and O2 and the external input / output terminal IO. The output signal is output.

The operation of this test circuit will be described more specifically. First, an arbitrary test mode is set by a test signal input from the external test signal input terminals S1, S2 to Sn to the test control section 2, and control signals M1, M2, M for that purpose are set.
3 to Mm are output from the test controller 2 to the internal circuit 3.
Internal circuit 3 to which control signals M1, M2, M3 to Mm are input
Changes to a test state according to the test mode. By thus changing the mode of the internal circuit 3 and dividing the function of the internal circuit 3, various tests in the internal circuit 3 can be easily performed.

[0006]

However, the above-mentioned conventional test circuit is a specific test among various tests, for example, a DC measurement test of an external input terminal, an external output terminal, or an external input / output terminal, that is, It has a drawback that it is not suitable for performing a DC voltage measurement test. Specifically, in the above circuit configuration, when performing DC measurement on the input side of the external input terminal and the external input / output terminal, it is necessary to make a judgment by a large-scale and complicated functional test in an arbitrary test mode. .. Also, D on the output side of the external output terminals and external input / output terminals
When performing C measurement, it is necessary to stop the function when the output reaches a desired level and perform DC measurement. in this way,
Since a large-scale and complicated functional test is required for DC measurement, it is difficult to program a measuring machine and it is difficult to perform a manual test.

[0007]

According to the present invention, in a test circuit for testing an internal circuit, which comprises an external input buffer and an external output buffer, a pulse input terminal for inputting a pulse signal, A predetermined external input / output terminal, a counter that counts a pulse signal from the pulse input terminal, a test control unit that inputs a signal output from the counter and outputs a control signal that controls a test state, and the control signal Thus, a test circuit including an output destination of the external input buffer and a switch for switching the input destination of the external output buffer to the predetermined external input / output terminal can be obtained.

[0008]

The control signal is output according to the output signal of the counter as described above, and the output destination of the external input buffer and the input destination of the external output buffer are switched and connected to a specific external input / output terminal by the control signal. By DC
The measurement can be easily performed.

[0009]

The first embodiment of the present invention will be described below. FIG. 1 shows a circuit diagram of a test circuit according to a first embodiment of the present invention. This test circuit is a circuit for testing an internal circuit 3 like the conventional test circuit shown in FIG. Yes, the integrated circuit is formed together with the internal circuit 3, and the external input terminal I
1, I2, external output terminals O1 and O2, and external input / output terminal IO. The illustrated test circuit further receives the outputs of the X-stage counter 1 and the counter 1 having an external pulse signal input terminal P1 and an external reset signal input terminal R1, and outputs control signals M1 to M1 to (n + 1) control signal terminals. Mn
Test control unit 2 that outputs +1 and buffers (no number) and switches (transfer gates) IT1 to ITn and OT1 to O provided between internal circuit 3 and each terminal
It is composed of Tm and T1. Each transfer gate has an N-side terminal and a P-side terminal, and opens when the logic signals “1” and “0” are applied to the N-side terminal and the P-side terminal, respectively. , Will be described as being in a closed state.

Further, a pull-down resistor R is connected between the illustrated external pulse signal input terminal P1 and the ground, and the external pulse signal input terminal P1 is directly connected to the clock input terminal CK of the X-stage counter 1. On the other hand, it is connected to an inverted clock input terminal (here, represented by ck) via an inverter circuit.

When the reset signal is received from the external reset signal input terminal R1, the X-stage counter 1 and, in some cases, the internal circuit 3 are also initialized. The external pulse signal supplied from the external pulse signal input terminal P1 is input to the X-stage counter 1 via the clock input terminal CK and counted, and the count result is the count output signals Q1, Q2 to QX.
It is output to the test control unit 2 as (X = 1, 2, 3, ...).

Here, transfer gates IT1, T2, ITn, OT provided between the internal circuit 3 and each terminal.
1, OT2, and OTm have N and P channel side gate terminals, and control signals of opposite polarities are applied to both channel side gate terminals. Specifically, the input sides of the external input terminals I1 and I2 and the external input / output terminal IO are connected to the internal circuit 3 and the transfer gates IT1 and IT2 to ITn through the respective input buffers.
The other (output side) of each of the transfer gates IT1 and IT2 to ITn is connected to a specific external input / output terminal DM and is output to the outside. Further, control signals M1 and M2 to Mn are input to the N channel side gates of the transfer gates IT1 and IT2 to ITn, respectively.
On the other hand, an inverted signal of each N-channel side gate is input to each P-channel side gate.

The inputs of the output buffers connected to the output sides of the external output terminals O1 and O2 and the external input / output terminal IO are selectively supplied to the internal circuit 3 and the external input / output terminal DM by transfer gates OT1 and OT2 to OTm. Connected.
Each of the transfer channel OT1, OT2 to OTm side P-channel side gates connected to the internal circuit 3 receives the control signal Mn + 1, and each N-channel side gate receives the inverted signal of the P-channel side gate input. Enter. Further, each of the transfer channel OT1 and OT2 to OTm has an N channel side gate connected to the external input / output terminal DM, and a control signal Mn + 1 is input to each of the P channel side gates. Input the inverted signal of the input. Further, the transfer gate T1 is a transfer gate constituting the output side of the external input / output terminal IO,
Its gate input is connected to the internal circuit 3, and selectively outputs the outputs from the transfer gate OTm and the output buffer to the external input / output terminal IO.

The test control section 2 receives the output signals Q1, Q2 to QX of the X-stage counter 1 and outputs control signals M1, M2 to Mn, Mn + 1 for setting the respective test states to the transfer gates IT1, IT2 to IT2. ITn, OT1, OT2
Output to the gate input of ~ OTm. In addition, the internal circuit 3
Are external input terminals I1 and I2 and external output terminals O1 and O
2. Each block is connected to the external input / output terminal IO and has a normal product function.

The operation of the test circuit according to the first embodiment described above will be described below. First, the X-stage counter 1 is initialized by the external reset signal input terminal R1, and the counter value becomes zero. At this time, the control signals M1, M2 to Mn
, Mn + 1 are all at the low level (logic "0" level), and the normal operation state is set. That is, the input buffers connected to the external input terminals I1 and I2 are connected to the internal circuit 3, while the output buffers connected to the external output terminals O1 and O2 are also gates of the transfer gates OT1 and OT2 on the internal circuit 3 side. Is connected to the internal circuit 3 via. The external input / output terminal IO is selectively connected to the input buffer or the output buffer.

On the other hand, the counter value of the X-stage counter 1 becomes 1 by the first pulse input from the external pulse signal input terminal P1. As a result, the test control unit 2 sets only the control signal M1 to the high level. Then, only the transfer gate IT1 is turned on, and only the output of the input buffer connected to the external input terminal 11 is output to the external input / output terminal DM, which facilitates the DC measurement of the external input terminal I1.

Next, the counter value of the X-stage counter 1 becomes 2 by the second pulse input from the external pulse signal input terminal P1. As a result, the test control section 2 becomes high level only for the control signal M2, and the transfer gate I
Only T2 turns on. Then, only the output of the input buffer connected to the external input terminal I2 is output to the external input / output terminal DM, so that the DC measurement of the external input terminal I2 becomes possible.

The counter value of the X-stage counter 1 is n at the n-th pulse input from the external pulse signal input terminal P1. As a result, the test control unit 2 causes the control signal M
Only n becomes high level and only the transfer gate ITn is turned on. As a result, only the output of the input buffer connected to the external input / output terminal IO is output to the external input / output terminal DM, and DC measurement can be performed when the external input / output terminal IO is input.

Further, the counter value of the X-stage counter 1 becomes n + 1 by the (n + 1) th pulse input from the external pulse signal input terminal P1. As a result, the test controller 2 sets only the control signal Mn + 1 to the high level, and the transfer gate O
The gates of the internal circuits 3 of T1 and OT2 to OTm are closed, while the gates of the external input / output terminal DM are opened. As a result, the input of the output buffer connected to the external output terminals O1 and O2 and the external input / output terminal IO is switched to the external input / output terminal DM. For this reason,
It becomes possible to perform DC measurement at the time of outputting the external output terminals O1 and O2 and the external input / output terminal IO.

On the other hand, the transfer gate T1 is a DC measurement (control signal Mn at the input side of the external input / output terminal IO).
Only at high level), it turns off, and the external input / output terminal I
It is set by the internal circuit 3 so that it is turned on during DC measurement on the output side of O (only the control signal Mn + 1 is at high level). If it is difficult to set the internal circuit 3, the control signal Mn + 1
It is necessary to incorporate logic so that it can be turned on.

As shown, the pull-down resistor R connected to the external pulse signal input terminal P1 protects the X-stage counter 1 from counting when noise is input from the external pulse signal input terminal P1. It is a thing. Of course, a pull-up resistor may be used instead of the pull-down resistor. Further, this resistor is not particularly required when it is not opened to the outside.

In the circuit diagram of FIG. 1, the external input terminal I
1, I2, external input / output terminal IO output terminal when measuring the input side DC (external input / output terminal DM)
And external output terminals O1 and O2, external input / output terminals I1 and I
When the DC measurement on the output side of 2 is made common with the terminal (external input / output terminal DM) that is input from the outside, it is not necessary to make it common and another terminal may be provided. Also, the external input terminals I1 and I2 and the external input / output terminal I
When performing DC measurement on the input side of O, the terminal (external input / output terminal DM) that outputs to the outside need not be limited to one terminal. If possible, 1 for each external input terminal
It may be configured to use terminals. With this configuration,
There is an effect that DC measurement can be performed at the input side of all the external input terminals I1 and I2 and the external input / output terminal IO at a time.

Below, 12 external input terminals (including an external reset signal input terminal and an external pulse signal input terminal),
5 external input / output terminals (including external input / output terminal DM),
An example in the case of 10 external output terminals will be described. In this case, the number of external input terminals is 10 (excluding external reset signal input terminal and external pulse signal input terminal) + the number of external input / output terminals is 4 (excluding external input / output terminal DM) +1 (when measuring DC on the output side) Since +1 (normal operation state) = 16,
In the case of the configuration of FIG. 1, 16 control signals are required, and therefore the X stage counter has 4 stages. When the counter value of the 4-stage counter is 0, it is in a normal operation state. When the counter value is 1 to 10, DC measurement of the external input terminals 1 to 10 is possible, and when the counter value is 11 to 14, the external input / output terminals 1 to 4
Can be measured on the input side of DC, and the counter value is 15 and the output side D of the external output terminals 1-10 and external input / output terminals 1-4
C measurement is possible.

FIG. 2 shows a part of the test circuit according to the second embodiment of the present invention. The basic structure of this test circuit is the same as that of the first embodiment shown in FIG. 1, except for the external input terminal (the input side of the external input / output terminal). Therefore, the points related to this difference will be described below.

The external input terminals I1, I2, I3 to In are
It is input to an internal circuit (not shown) and transfer gates IT1, IT2, IT3 to ITn through each input buffer. Each transfer gate IT1, IT2, IT3
The other side (output side) of ITn is an n-input AND gate A
It is input to the OR gate O1 having 1 and n inputs. Transfer channel IT1, IT2, IT3 to ITn N-channel side gates respectively input control signal M1 and P
The channel side gate inputs the inverted signal of the N channel side gate input.

The output of the AND gate A1 is output to the transfer gate T1 and the output of the OR gate O1 is output to the transfer gate T2. The other (output side) of the transfer gates T1 and T2 are both external input / output terminals DM
Is output to. Further, the N-channel side gates of the transfer gates T1 and T2 receive the control signals M1 'and M1 ", respectively, and the P-channel side gate inputs an inverted signal of each N-channel side gate input.

The operation of the test circuit according to the second embodiment will be described below. When the counter value in the X-stage counter (not shown) becomes 1, the control signals M1, M1 'output from the test control unit 2 become high level, and the transfer gates IT1, IT2, IT3 to ITn, T1 are turned on. To do. Therefore, the external input terminals I1, I2, I3 to In
When all the signals become high level, the external input / output terminal DM
Goes high due to AND gate A1.

When the counter value of the X-stage counter becomes 2, the control signals M1 and M1 "become high level, and the transfer gates IT1, IT2, IT3 to IT.
n and T2 turn on respectively. Therefore, when the external input terminals I1, I2, I3 to In are all at the low level, the external input / output terminal DM becomes the low level by the OR gate O1. As a result, the external input terminals I1, I2, I3 ...
DC measurement of In can be performed collectively for all terminals.

[0029]

As described above, according to the test circuit of the present invention, DC measurement of the external input terminal and the external input / output terminal can be performed without requiring a large-scale and complicated functional test. Therefore, there is an effect that the program of the measuring machine is easy and the manual test can be easily measured.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a test circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a test circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional test circuit.

[Explanation of symbols]

R1 external reset signal input terminal P1 pulse signal input terminal I1, I2, I3, In external input terminal IO, DM external input / output terminal Q1, Q2, QX output signal M1, M1 ', M1 ″, M2, Mn, Mn + 1 Control signal R Pull-down resistance IT1, IT2, IT3, ITn, OT1, OT2, O
Tm, T1, T2 transfer gate A1 AND gate O1 OR gate S1, S2, Sn External test signal input terminal N N-channel transistor P P-channel transistor

Claims (1)

[Claims] 1. A test circuit for testing an internal circuit, comprising: an external input buffer and an external output buffer; a pulse input terminal for inputting a pulse signal; a predetermined external input / output terminal; A counter that counts a pulse signal from a pulse input terminal, a test control unit that inputs a signal output from the counter and outputs a control signal that controls a test state, and an output destination of an external input buffer and an external output by the control signal. A test circuit, comprising: a switch for switching an input destination of the buffer to the predetermined external input / output terminal.