JP2000049583A - Output circuit - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide an output circuit capable of coping with a variation in an output MOSFET of an IC and a variation in a characteristic impedance of a transmission line and optimizing the output impedance. SOLUTION: An output circuit OC includes an output buffer OB, an input buffer IB, a delay circuit DL constituting an impedance adjustment circuit, a counter CTRLH, a CTRL transmission line L, and the like. First set by the RST signal, the output circuit O
The output impedance of C has a maximum value. The impedance adjustment clock signal ZSCK passes through the output circuit OB, is totally reflected at the far end of the transmission line L, returns, enters the input buffer IB, and is compared with Vref. The counting of the counter circuit is started from the start of the ZSCK transmission, and an impedance adjustment signal corresponding to the counted value is output to the output buffer OB.
, The reflected input value decreases, and when it becomes equal to Vref, inversion of the input buffer IB occurs. The count value at this time means optimization of impedance matching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit,
For example, it is used to optimize an output circuit mounted on a logic integrated circuit device having a CMOS (complementary MOS) logic gate as a basic element and its output impedance, and to increase the speed and cost of a logic integrated circuit device including the same. And particularly effective technologies.

[0002]

2. Description of the Related Art P-channel and N-channel MOSFs
There is a CMOS logic gate made of ET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is a general term for an insulated gate type field effect transistor). There is also a logic integrated circuit device having a CMOS logic gate as a basic element, and an output circuit including an output MOSFET mounted on such a logic integrated circuit device.

[0003]

In a logic integrated circuit device or the like including an output circuit, an output terminal of each output circuit is coupled to a corresponding output external terminal.
An input terminal of a receiving-side input circuit is coupled via a transmission line having a predetermined characteristic impedance. In recent years, as the speed of a logic integrated circuit device and the like has been increased, it is essential that an output circuit has an output impedance matching the characteristic impedance of a transmission line. Therefore, prior to the present invention, the present inventors have developed a logic integrated circuit device having an impedance adjustment circuit capable of automatically matching the output impedance of the output circuit with the characteristic impedance of the transmission line. I noticed that a dot was left.

That is, this logic integrated circuit device has a large number of external terminals for output and a large number of output circuits provided in correspondence with the external terminals, and provides an output impedance between each output circuit and the characteristic impedance of the transmission line. The matching is performed by coupling a terminating resistor of, for example, about 50 Ω (ohm) corresponding to the characteristic impedance of the transmission line to a specific output external terminal, and regarding the resistance value as the characteristic impedance of the transmission line. The impedance adjustment by this method is performed DC, that is, in a state where the normal operation of the logic integrated circuit device and the system including the same is stopped, and the output impedance obtained by the measurement is mounted on the logic integrated circuit device. Are uniformly assigned to all output circuits. As a result, it is not possible to cope with process variations of MOSFETs and the like constituting the output circuit and variations in characteristic impedance due to the wiring form of the transmission line, and it is not possible to sufficiently exhibit the interface performance of the output circuit and the transmission line. . In addition, since a specific output external terminal and an external resistor are required for impedance adjustment, the number of required external terminals and the number of required elements of the logic integrated circuit device are increased, and cost reduction is hindered.

An object of the present invention is to realize an output circuit capable of coping with a process variation of an output MOSFET and a variation of a characteristic impedance of a transmission line and optimizing the output impedance. Another object of the present invention is to improve the interface performance of a logic integrated circuit device or the like including an output circuit, reduce the number of required external terminals and the number of required elements, and increase the speed and cost.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, an output buffer of an output circuit mounted on a logic integrated circuit device or the like having a CMOS logic gate as a basic element is provided in parallel between, for example, an output power supply voltage and an output external terminal, and is provided with a first impedance control. N first output MOSFETs each selectively turned on in response to a valid level of a corresponding bit of a signal
And an n number of second output terminals provided in parallel between the output external terminal and the ground potential of the circuit and selectively turned on in response to the effective level of the corresponding bit of the second impedance control signal. And one of the input terminals is coupled to the corresponding output external terminal, and the other input terminal is connected to the other input terminal. When a predetermined pulse signal is output via the corresponding output buffer and a predetermined pulse signal is output through the corresponding output buffer, an external terminal for output during a period until the reflected signal at the far end of the transmission line of the high level or low level change arrives An input buffer for selectively inverting the logic level of the output signal when the reflected potential at the reference voltage reaches the reference voltage, and the output thereof is used as a first or second impedance control signal. In the initial state, after the count value is reset so that the output impedance of the output circuit becomes the maximum value, the first and second counts are selectively counted up in response to the level inversion of the output signal of the input buffer during the period. And an impedance adjustment circuit including the counter circuit.

[0008] According to the above-mentioned means, each output circuit and a system including the same are kept in a normal operation state without requiring a specific output external terminal and an external resistor for impedance matching. The output impedance of the output circuit can be automatically and efficiently matched to the characteristic impedance of the corresponding transmission line and optimized. As a result, it is possible to realize an output circuit capable of coping with the process variation of the output MOSFET and the variation of the characteristic impedance of the transmission line and automatically optimizing the output impedance, thereby achieving a logic integrated circuit device including the output circuit. Interface performance and the required number of external terminals and external components can be reduced, and the speed and cost of the logic integrated circuit device and the like can be reduced.

[0009]

FIG. 1 shows an output circuit OC (output circuit) with an impedance adjustment function to which the present invention is applied.
The circuit diagram of one embodiment is shown. 2 and 3 show the output circuit O with the impedance adjustment function of FIG.
Output buffer OB and counter circuit CTR included in C
The circuit diagrams of one embodiment of H are shown respectively. With reference to these figures, the configuration and operation of the output circuit OC with an impedance adjustment function of this embodiment and its components and the features thereof will be described.

The output circuit OC with an impedance adjustment function of this embodiment is not particularly limited, but is mounted on a logic integrated circuit device having a CMOS logic gate as a basic element together with a plurality of other output circuits with an impedance adjustment function. Is done. Each of the circuit elements shown in FIGS.
Together with other circuit elements (not shown) of the logic integrated circuit device, they are formed on a single semiconductor substrate surface such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The counter circuit CTRL has the same configuration as the counter circuit CTRL of FIG. Further, the output buffer O of the output circuit OC having an impedance adjustment function is provided.
Each unit except B uses a power supply voltage VDD such as +3.3 V (volt) as its operation power supply, while the output buffer OB uses an output power supply voltage VTT such as +1.3 V as its operation power supply.

In FIG. 1, an output circuit OC having an impedance adjusting function of this embodiment has an impedance adjusting clock signal ZSCK, that is, an internal node n at its input terminal.
an output buffer OB for receiving the internal signal na at a.
One input terminal includes a corresponding output external terminal out, that is, an input buffer IB coupled to the internal node nb and receiving the reference voltage Vref at the other input terminal. The output terminal of output buffer OB is coupled to internal node nb, that is, output external terminal out. The reference voltage Vr
ef is an intermediate potential between the output power supply voltage VTT and the ground potential VSS, that is, VTT / 2. The output power supply voltage VTT is, for example, +1.3 V as described above, and the reference voltage Vref is +0.65 V.

Output circuit OC with impedance adjustment function
Further includes a delay circuit DL, flip-flops FF1 and FF2, which constitute an impedance adjustment circuit together with the input buffer IB, a counter circuit CTRH (first counter circuit), and a CTRL (second counter circuit). Of these, the delay circuit DL has an internal signal n
a, that is, the impedance adjustment clock signal ZSCK is supplied. The data input terminal D of the flip-flop FF1 is supplied with an internal signal nc as an output signal of the input buffer IB, and the data input terminal D of the flip-flop FF2 is supplied with an inverted signal of the inverter V2.

A clock input terminal CK of the flip-flops FF1 and FF2 is commonly supplied with an internal signal na, that is, a delay signal of the impedance adjustment clock signal ZSCK by the delay circuit DL, that is, an internal signal nd at an internal node nd. Also, the non-inverted output signal Q of the flip-flop FF1, that is, the internal signal ne is an AND signal.
The non-inverted output signal Q of the flip-flop FF2, that is, the internal signal nh is supplied to the third input terminal of the gate G1.
The signal is supplied to a third input terminal of the AND gate G2. An impedance adjustment enable signal ZSEN is commonly supplied to first input terminals of the AND gates G1 and G2 from a control circuit (not shown) of the logic integrated circuit device. Also,
A second input terminal of the AND gate G2 has an internal signal nd.
Is supplied to a second input terminal of the AND gate G1.
An inverted signal from the inverter V1 is supplied. The output signal of the AND gate G1, that is, the internal signal nf at the internal node nf, is supplied to the counter circuit CTRH as a count-up signal, and the output signal of the AND gate G2, that is, the internal signal ni at the internal node ni, is supplied as a count-up signal to the counter circuit CTRL. Supplied to

The counter circuits CTRLH and CTRL include:
Further, a reset signal RST is commonly supplied from the control circuit. The 4-bit output signal of the counter circuit CTRH is the impedance control signals AH0 to AH3.
(First impedance control signal) is supplied to the upper control terminal of the output buffer OB and the counter circuit CTRL
Is a four-bit output signal of the impedance control signal AL0.
ＡＬAL3 (second impedance control signal) is supplied to its lower control terminal.

Here, the output buffer OB is not particularly limited, but as shown in FIG.
Output external terminal out corresponding to T (first power supply voltage)
And one N-channel output MOS provided between
FET N10 and n-channel type n output MOS transistors provided in parallel with this output MOSFET, that is, four output MOS transistors
FETs N11 to N14 (first output MOSFETs). The output buffer OB is a single N-channel output MOSFET provided between the corresponding output external terminal out and the ground potential VSS (second power supply voltage).
N20 and four N-channel output MOSFETs N21 to N21 provided in parallel with the output MOSFET.
24 (second output MOSFET).

Output MOSF constituting output buffer OB
The internal signal na, that is, the impedance adjustment clock signal ZSCK is supplied to the gate of the ETN 10, and the output MO
An inverted signal from the inverter V3 is supplied to the gate of the SFET N20. The output MOSFET N1
The gates 1 to N14 have corresponding AND gates G31.
To G34 are respectively supplied to the output MOSF
The gates of ETN21 to N24 have an AND gate G41.
To G44 are supplied. One input terminal of each of AND gates G31 to G34 has a corresponding impedance control signal AH0 from counter circuit CTRH.
AH3 is supplied, and an internal signal na is commonly supplied to the other input terminals. Also, AND gate G
One of the input terminals of 41 to G44 has a counter circuit CT.
RL corresponding impedance control signals AL0-AL
3 is supplied, and the other input terminal is commonly supplied with an inverted signal of the internal signal na by the inverter V3.

Accordingly, the AND gates G31 to G34
Are selectively set to a high level when the internal signal na is set to the high level and the corresponding impedance control signals AH0 to AH3 are set to the valid level, that is, the high level, and the output signals of these AND gates are output. Output MOSFET N11 corresponding to high level
To N14 are selectively turned on. Similarly,
The output signals of the AND gates G41 to G44 are the internal signals n
a is set to a low level, and the corresponding impedance control signals AL0 to AL3 are set to an effective level, that is, a high level, so that they are selectively set to a high level. MOSFETs N21 to N24 are selectively turned on. Needless to say, the output buffer OB
Output terminal, that is, the output external terminal out,
When one of SFETs N10 and N11 to N14 is turned on, a high level such as output power supply voltage VTT is output, and when one of output MOSFETs N20 and N21 to N24 is turned on, ground potential VSS is applied. Is output.

In this embodiment, the output MOSFET N
11 to N14 and N21 to N24 are 2 to 0th power to cubic ratio, that is, W, 2 for a predetermined value W or W '.
W, 4W and 8W, or W ', 2W', 4W '
And a gate width of 8 W '. As is well known, the value of the on-resistance of the MOSFET is
It increases in inverse proportion to the gate width. Accordingly, the output impedance ZO of the output buffer OB, that is, the output circuit OC with the impedance adjustment function at the time of high level output is obtained.
utH is the impedance control signal AH when K is a constant and the gate width of the output MOSFET N10 is W0.
A total of 16 count values “0000” “000” of 0 to AH3
With respect to “1” to “1111”, step-like values are sequentially obtained as follows: ZoutH = K / W0 ZoutH = K / (W0 + W) to ZoutH = K / (W0 + 15W)

Similarly, when the output buffer OB, that is, the output impedance ZoutL of the output circuit OC with impedance adjustment function at the time of low level output, is K ′ as a constant and the gate width of the output MOSFET N20 is W0 ′,
The count value “00” of the impedance control signals AL0 to AL3
For "00""0001" to "1111", take a step-like value such as ZoutL = K '/ W0' ZoutL = K '/ (W0' + W ') or ZoutL = K' / (W0 '+ 15W') It will be.

From these facts, the count value of the impedance control signals AH0 to AH3 of the output buffer OB, that is, the output impedance ZoutH when the output circuit OC with the impedance adjustment function is at the high level, is set to the initial value, that is, "0000". When the count value of the impedance control signals AH0 to AH3 is set to its final value, that is, “1111”, it becomes the minimum. Further, the output buffer OB, that is, the output impedance Zout at the time of low-level output of the output circuit OC with the impedance adjustment function is output.
L also becomes maximum when the count value of the impedance control signals AL0 to AL3 is set to the initial value, that is, “0000”,
It becomes minimum when the count value of the impedance control signals AL0 to AL3 is set to the final value of “1111”.

Next, the counter circuits CTRLH and CTRL
Is not particularly limited, but the counter circuit CTRH of FIG.
, Four edge-triggered flip-flops FF11 to FF are serially coupled in such a manner that their non-inverted output terminal Q and clock input terminal CK are sequentially coupled.
14 inclusive. A reset signal RST is supplied to reset input terminals RS of these flip-flops. The output signal of the AND gate G1, that is, the internal signal nf is supplied to the clock input terminal CK of the first-stage flip-flop FF11, and its inverted output signal QB is supplied to the data input terminal D of each flip-flop. You. The non-inverted output signals Q of the flip-flops become impedance control signals AH0 to AH3, respectively.

As a result, the flip-flops FF11 to FF14 constituting the counter circuit CTRH operate as 4-bit binary counters, perform a stepping operation in response to the rise of the internal signal nf, and form the impedance control signals AH0 to AH3. I do. When the reset signal RST is set to the high level, the flip-flops FF11 to FF11
The FFs 14 are all reset, and the counter circuit C
The count value of TRH, that is, the impedance control signal AH0
AH3 becomes “0000”.

Returning to the description of FIG. The internal signal na, that is, the impedance adjustment clock signal ZSCK, supplied from the control circuit (not shown) of the logic integrated circuit device to the output circuit OC with the impedance adjustment function is output from the output buffer OB.
From the internal node nb, that is, the corresponding output external terminal ou.
t to the transmission line L and the delay circuit D
After being delayed by L for the delay time td, it becomes an internal signal nd. In this embodiment, the delay time td of the delay circuit DL is tpdo and tpdi as the transmission delay time of the output buffer OB and the input buffer IB, respectively, and the transmission delay time of one way of the transmission line L is tp, as described later.
When dL is set, td is set so that td = tpdo + tpdL + tpdi, where td is tpdo + tpdi <td <tpdo + tpdi + 2t
Any pdL can be used. The delay time td of the delay circuit DL is equal to the impedance adjustment clock signal ZS.
CK is output via an output buffer OB to an external terminal ou for output.
t, that is, when the signal is output to the transmission line L, the signal is transmitted to the internal node nc via the input buffer IB as it is, then reflected at the far end of the transmission line L, returned to the output external terminal out, and Until the signal is transmitted to the internal node nc via the internal node nc, that is, an intermediate time point in the impedance determination period.

As is well known, the reflection potential Vr of the output external terminal out at the beginning when the impedance adjustment clock signal ZSCK is output to the transmission line L via the output buffer OB is, for example, the high-level output voltage of the output buffer OB, The absolute value of the output power supply voltage VTT is defined as VTT,
When the output impedance of the output buffer OB, that is, the output impedance of the output circuit OC with the impedance adjustment function is Zout, and the characteristic impedance of the transmission line L is Zo, Vr = VTT × Zo / (Zout + Zo). Therefore, when the output impedance Zout of the output buffer OB matches the characteristic impedance Zo of the transmission line L, the reflection potential Vr becomes Vr = VTT / 2, which matches the potential VTT / 2 of the reference voltage Vref.

Next, the input buffer IB is connected to the internal node n
b, that is, the reflected potential Vr at the output external terminal out is compared with the potential of the reference voltage Vref. When the reflected potential Vr is higher than the reference voltage Vref, the output signal, that is, the logic level of the internal signal nc is selectively inverted. Therefore,
The fact that the internal signal nc is not inverted and remains at the high level during the high-level output impedance determination period means that the output impedance ZoutH of the output buffer OB, that is, the output circuit OC with impedance adjustment function at the time of high-level output is still the transmission line. L is greater than the characteristic impedance Zo of the internal signal nc.
That the logic level is inverted to low level
Output impedance ZoutH is characteristic impedance Z
This indicates that it has become smaller than o. Further, the fact that the internal signal nc is at the same level that is not inverted during the impedance determination period at the time of low level output, that is, at the low level, indicates that the output impedance Zout is still larger than the characteristic impedance Zo of the transmission line L, and the logical level of the internal signal nc Is inverted to a high level, indicating that the output impedance Zout has become smaller than the characteristic impedance Zo of the transmission line L.

From these, first, the counter circuit CT
RH and CTRL are reset, and their count values, that is, impedance control signals AH0 to AH3 and A
L0 to AL3 are set to the initial value “0000”, and the output impedances ZoutH and ZoutL at the time of high-level output and low-level output of the output buffer OB are each set to the maximum value, and then the impedance adjustment clock signal ZSCK is set.
Are repeatedly input, and the internal signal nc changes to low level during the impedance determination period at the time of high level output,
The counter circuit C operates until the internal signal nc changes to the high level during the impedance determination period at the time of the low level output.
By counting up TRH and CTRL and gradually reducing the output impedance Zout of the output buffer OB, the output impedance Zou of the output buffer OB, that is, the output circuit OC with the impedance adjustment function, is obtained.
tH and ZoutL can be matched and optimized with the characteristic impedance Zo of the corresponding transmission line L, respectively.

As described above, the internal signal nc is supplied to the data input terminal D of the flip-flop FF1 and, after being inverted by the inverter V2, supplied to the data input terminal D of the flip-flop FF2. As described above, the internal signal nd, which is the output signal of the delay circuit DL, is commonly supplied to the clock input terminals CK of these flip-flops FF1 and FF2, and the output signals of the flip-flops, that is, the internal signals ne and nh are After an AND operation with the impedance adjustment enable signal ZSEN and the internal signal nd or its reflection signal is performed by the AND gate G1 or G2, the counter circuit CTRLH or CTRL is obtained.
Signal, ie, the internal signal nf or n
i. Note that, although not particularly limited, the flip-flop FF1 is a so-called positive edge trigger type flip-flop, and its state changes in response to a rising edge of the internal signal nd. The flip-flop FF2 is a so-called negative edge trigger type flip-flop, and its state changes upon receiving a falling edge of the internal signal nd.

Thus, the logic level of the internal signal nc, which is the output signal of the input buffer IB, is taken into the flip-flop FF1 at the rising edge of the internal signal nd, that is, in the middle of the impedance determination period at the time of high level output, and the internal signal nd , That is, in the middle of the impedance determination period at the time of low-level output, is taken into the flip-flop FF2. Then, in response to the non-inverted output signal Q of the flip-flop FF1, that is, the high level of the internal signal ne, the output signal of the AND gate G1, that is, the internal signal nf becomes high level in synchronization with the low level of the internal signal nd. In response to the rising edge, the counter circuit CTRH counts up. In response to the non-inverted output signal Q of the flip-flop FF2, that is, the high level of the internal signal nh, the AND gate G2
, The internal signal ni goes high in synchronization with the high level of the internal signal nd, and the counter circuit CTRL counts up in response to the rising edge of the internal signal ni.

FIG. 4 shows a connection diagram of an embodiment at the time of adjusting the high-level output impedance of the output circuit OC with the impedance adjusting function of FIG. FIG. 5 is a signal waveform diagram of one embodiment at the time of high-level output impedance adjustment of the output circuit OC with the impedance adjustment function of FIG. 1, and FIG. 6 is an enlarged signal waveform diagram of the embodiment. It is shown. With reference to these figures, a specific operation, impedance adjustment method, and characteristics of the output circuit OC with an impedance adjustment function of this embodiment when adjusting the high-level output impedance will be described.

FIG. 4 shows a part of the output circuit OC having the impedance adjustment function shown in FIG. 1 relating to the adjustment of the high-level output impedance, which is rearranged and repeated, and only the necessary description will be added. FIG. 6 is an enlarged view of a part of FIG. 5 and should be referred to as necessary. 5 and 6, the internal signal nb
That is, the level of the output signal at the output external terminal out is shown in an enlarged manner as compared with other signals. Furthermore, in the output circuit OC with the impedance adjusting function of this embodiment, the adjustment of the output impedance at the time of the high-level output and the adjustment of the output impedance at the time of the low-level output can be performed simultaneously at the same time. In the signal waveform diagram, only one of them is shown.

In FIG. 4, when the output impedance of the output circuit OC with an impedance adjusting function is adjusted to a high level, a transmission line L having a predetermined characteristic impedance Zo is coupled to the output external terminal out. . At the far end of the transmission line L, the input impedance of the logic integrated circuit device on the receiving side is Hi-Z (high impedance).
To the input external terminal in. Note that the transmission delay time for one way of the transmission line L is tpdL. The output buffer OB and the input buffer IB are respectively tp
The delay circuit DL has a transmission delay time of td = tpdo + tpdL + tpdi, as described above.

Output circuit OC with impedance adjustment function
Then, as shown in FIG. 5, first, the reset signal RST
Is temporarily set to a high level like the power supply voltage VDD for a predetermined period, and in response to the rise of the reset signal RST, the counter circuit CTRH is reset. Therefore, the count value of the counter circuit CTRH, that is, the impedance control signals AH0 to AH3 are initialized to “0000”.
And each of the bits is at a low level such as the ground potential VSS.

Immediately after the reset of the counter circuit CTRH, the impedance adjustment enable signal ZSEN and the impedance adjustment clock signal ZSCK are both set to the ground potential V.
It is set to a low level like SS. Further, since the impedance adjustment enable signal ZSEN and the impedance adjustment clock signal ZSCK are set to the low level, in the output buffer OB, the output signals of the AND gates G31 to G34 and G41 to G44 are all set to the low level such as the ground potential VSS. Output MO for output
Only SFETN20 is turned on. Therefore, a low level such as the ground potential VSS is output to the internal node nb, that is, the output external terminal out, and the internal signal nc, which is an output signal of the input buffer IB, is changed to a high level such as the power supply voltage VDD. Is done. In response to the low level of the impedance adjustment clock signal ZSCK, the internal signal nd, which is the output signal of the delay circuit DL, changes to the ground potential VS.
In response to the low level of the internal signal nd, the internal signal ne as the output signal of the flip-flop FF1 and the internal signal nf as the output signal of the AND gate G1 are set to the low level such as the ground potential VSS.

When the reset signal RST is returned to a low level such as the ground potential VSS, the impedance adjustment enable signal ZSEN is changed to the power supply voltage VD after a predetermined period.
The impedance adjustment clock signal ZSCK is repeatedly set to a high level such as the power supply voltage VDD or a low level such as the ground potential VSS with a predetermined period. Note that the number of times that the impedance adjustment clock signal ZSCK is repeatedly set to the high level is the counter modulo of the counter circuit CTRH, that is, 16 times.
SEN is returned to a low level such as the ground potential VSS when a predetermined time (for example, after the clock signal has been output 2 ⁿ times) has elapsed from the last fall of the impedance adjustment clock signal ZSCK.

Output circuit with impedance adjustment function OC
Output buffer OB receives the internal signal na, that is, the high level of the impedance adjustment clock signal ZSCK, and turns on the output MOSFET N10. However, the other output MOSFETs N11 to N14 are all kept in an off state because the impedance control signals AH0 to AH3 are all at the low level and the output signals of the corresponding AND gates G31 to G34 are all at the low level. The output impedance ZoutH of the buffer OB, that is, the output circuit OC with an impedance adjustment function at the time of high-level output is the maximum value, that is, K / W0. Therefore, the internal node nb, that is, the output external terminal o
output signal level at the output MOSFET N
In response to the ON state of the output buffer OB, the output buffer OB attempts to rise to a high level such as the output power supply voltage VTT after the transmission delay time tpdo, but as described above, the output impedance ZoutH of the output buffer OB becomes the maximum value K /
Since it is set to W0, it is limited by the reflection potential VH0 such that VH0 = VTT × Zo / (ZoutH + Zo).

Needless to say, the maximum value K / W0 of the output impedance ZoutH of the output buffer OB is larger than the characteristic impedance Zo of the transmission line L, and the reflection potential VH0 is lower than VTT / 2.
Therefore, the internal signal nc, which is the output signal of the input buffer IB, remains at the low level even after the transmission delay time tpdi of the input buffer IB has elapsed.

By the way, the high-level output signal output from the output external terminal out to the transmission line L is output from the far end of the transmission line L in the high impedance state when the one-way transmission delay time tpdL has elapsed. After being totally reflected by
When the transmission delay time 2tpdL corresponding to the round trip elapses, the output external terminal out of the logic integrated circuit device on the output side is output.
, And the potential of the output signal at the output external terminal out is set to a completely high level like the output power supply voltage VTT.

On the other hand, a high level change of the internal signal na, that is, the impedance adjustment clock signal ZSCK is delayed by a transmission delay time td of td = tpdo + tpdL + tpdi by the delay circuit DL of the output circuit OC with an impedance adjustment function and transmitted to the internal node nd. Is done. The transmission delay time td of the delay circuit DL is
As described above, the impedance adjustment clock signal ZSC
K is output to the output external terminal out via the output buffer OB, that is, to the transmission line L, is transmitted to the internal node nc via the input buffer IB, and is reflected at the far end of the transmission line L to be output to the output external terminal. This period corresponds to a period until the signal returns to the terminal out and is further transmitted to the internal node nc via the input buffer IB, that is, an intermediate time point of the adjustment in the impedance determination period. At the rising edge of the internal signal nd, the internal signal nc By determining the level of
The output buffer OB, that is, the output impedance ZoutH of the output circuit OC with the impedance adjustment function is the transmission line L
It can be determined whether the characteristic impedance is greater than the characteristic impedance Zo.

As represented by the potential VH0 in FIGS. 5 and 6, when the potential of the output signal at the internal node nb, that is, the output external terminal out is lower than the reference voltage Vref during the impedance determination period, the internal signal nc becomes high level. Is input to the flip-flop FF1 at the rising edge of the internal signal nd, and the non-inverted output signal Q, that is, the internal signal ne is set to a high level like the power supply voltage VDD. In response to the high level of the internal signal ne and the high level of the inverted signal of the internal signal nd by the inverter V1, the output signal of the AND gate G1, that is, the internal signal nf is set to the high level. The circuit CTRH is counted up, and the count value becomes "0001".

Thus, at the time of the next high level change of the internal signal na, that is, the impedance adjustment clock signal ZSCK, the output buffer OB outputs two output MOSFETs N
10 and N11 are turned on, and the output impedance ZoutH of the output buffer OB, that is, the output circuit OC with the impedance adjustment function is the second largest, ZoutH = K / (W0 + W). Therefore, the level of the internal node nb, that is, the output external terminal out during the impedance determination period is the potential VH1, but this potential VH1 is still lower than the reference voltage Vref, and the internal signal nc is still at the high level. Therefore, the flip-flop FF1 is kept in the set state even at the next rising of the internal signal nd, and the internal signal ne, which is the output signal, is kept at the high level. As a result, in response to the next low level of the internal signal nd, the internal signal nf, which is the output signal of the AND gate G1, goes high again, and the counter circuit CTR
H is counted up and the counted value is “0010”
Becomes

The output buffer OB receives the count value “0010” of the impedance control signals AH0 to AH3 and the internal signal na, that is, the next high level of the impedance adjustment clock signal ZSCK, and outputs two output MOSFETs N.
10 and N12 are turned on, the output impedance ZoutH of the output buffer OB, that is, the output circuit OC with the impedance adjustment function is the third largest, and ZoutH = K / (W0 + 2W). Therefore, the level of the internal node nb, that is, the output external terminal out during the impedance determination period is the potential VH2, but this potential VH2 is still lower than the reference voltage Vref, and the internal signal nc remains at the high level. Therefore, at the next rising of the internal signal nd, the flip-flop FF1 is kept in the set state, and the internal signal ne, which is the output signal, is kept at the high level. As a result, the internal signal nf, which is the output signal of the AND gate G1, becomes the high level again in response to the next low level of the internal signal nd, and the counter circuit CTRH counts up, and the count value becomes "00".
11 ".

In the output buffer OB, similarly, the count value "0011" of the impedance control signals AH0 to AH3 and the internal signal na, that is, the impedance adjustment clock signal ZS
In response to the next high level of CK, three output MOSFs
ETN10 to N12 are turned on and output buffer O
B, that is, the output impedance ZoutH of the output circuit OC with the impedance adjustment function is the fourth largest, ZoutH = K / (W0 + 3W). Therefore, the level of the internal node nb, that is, the output external terminal out during the impedance determination period is the potential VH3 higher than the reference voltage Vref, and the internal signal nc is set to the low level in response to this. For this reason, the flip-flop FF1 goes low in response to the next rising of the internal signal nd, and the internal signal ne, which is the output signal, is changed to low level. As a result, when the internal signal nd goes low next time, the internal signal nf, which is the output signal of the AND gate G1, remains low, and the counter circuit CTRH does not count up. This state is maintained until the next input of the internal signal na, that is, the impedance adjustment clock signal ZSCK, and the output buffer OB is continuously supplied with the impedance control signals AH0 to AH3 having the count value “0011”.

As is clear from the above description, the count value “0011” of the impedance control signals AH0 to AH3 is
When the potential of the output signal at the internal node nb, that is, the reflected external potential at the output external terminal out reaches a predetermined value and becomes higher than the reference voltage Vref during the impedance determination period, in other words, the output buffer OB, that is, the output with the impedance adjusting function. The output impedance ZoutH of the circuit OC is a count value at which the output impedance ZoutH is smaller than the characteristic impedance Zo of the transmission line L and becomes the maximum value.
By holding the signal H and continuously supplying it to the output buffer OB, the output impedance ZoutH of the output buffer OB, that is, the output circuit OC with the impedance adjustment function, and the characteristic impedance Zo of the transmission line L can be matched and optimized.

FIG. 7 is a connection diagram of one embodiment at the time of adjusting the low-level output impedance of the output circuit OC with the impedance adjusting function of FIG. FIG. 8 is a signal waveform diagram of one embodiment at the time of adjusting the low-level output impedance of the output circuit OC with the impedance adjusting function of FIG. 1, and FIG. 9 is an enlarged signal waveform diagram of the embodiment. It is shown. With reference to these figures, a specific operation, impedance adjustment method, and characteristics of the output circuit OC with impedance adjustment function of this embodiment when adjusting the low-level output impedance will be described.

FIG. 7 is a rearrangement of a portion related to the high-level output impedance adjustment of the output circuit OC with an impedance adjustment function of FIG. 1 described above, and only necessary explanations will be added. FIG. 9 is a partially enlarged view of FIG. 8 and should be referred to as necessary. Furthermore, since this embodiment basically follows the embodiment of FIGS. 4 to 6, the description of the same parts as those of the embodiments may be omitted.

In FIG. 7, when output impedance adjustment is performed at the time of low-level output of the output circuit OC with the impedance adjustment function, the transmission line L having the characteristic impedance Zo is connected to the output external terminal out as in FIG. Are combined. At the far end of the transmission line L, the input impedance of the logic integrated circuit device on the receiving side is coupled to the Hi-Z input external terminal in.

Output circuit OC with impedance adjustment function
Then, as shown in FIG. 8, first, the reset signal RST
Is temporarily set to a high level like the power supply voltage VDD for a predetermined period, and in response to the rise of the reset signal RST, the counter circuit CTRL is reset. Therefore, the count value of the counter circuit CTRL, that is, the impedance control signals AL0 to AL3 are set to the initial value “0000”.
And each of the bits is at a low level such as the ground potential VSS.

Immediately after the reset of the counter circuit CTRL, the impedance adjustment enable signal ZSEN and the impedance adjustment clock signal ZSCK are both set to the ground potential V.
It is set to a low level like SS. Further, since the impedance adjustment enable signal ZSEN and the impedance adjustment clock signal ZSCK are set to the low level, in the output buffer OB, the output signals of the AND gates G31 to G34 and G41 to G44 are all set to the low level such as the ground potential VSS. Output MO for output
Only SFETN20 is turned on. Therefore, a low level such as the ground potential VSS is output to the internal node nb, that is, the output external terminal out, and in response to this, the output signal of the input buffer IB, that is, the internal signal ng which is an inverted signal of the internal signal nc is set to the ground potential. It is set to a low level like VSS. Also, the impedance adjustment clock signal Z
In response to the low level of SCK, the internal signal nd as an output signal of the delay circuit DL is set to a low level such as the ground potential VSS, and these impedance adjustment clock signals ZSC
In response to K and the low level of the internal signal nd, the internal signal nh as the output signal of the flip-flop FF2 and the internal signal ni as the output signal of the AND gate G2 are set to the low level.

When the reset signal RST is returned to a low level such as the ground potential VSS, the impedance adjustment enable signal ZSEN is changed to the power supply voltage VD after a predetermined period.
The impedance adjustment clock signal ZSCK is repeatedly set to a high level such as the power supply voltage VDD or a low level such as the ground potential VSS with a predetermined period.

Output circuit OC with impedance adjustment function
In the output buffer OB, the output MOSFET N20 is temporarily turned off in response to the internal signal na, that is, the high level of the impedance adjustment clock signal ZSCK, and the output MOSFET N20 is turned on again in response to the first fall. However, at this time, the other output MO
The SFETs N21 to N24 output the impedance control signal A
All the bits L0 to AL3 are set to the low level, and the output signals of the corresponding AND gates G41 to G44 are all set to the low level, so that they are all kept in the off state, and the output buffer OB, that is, the low level output of the output circuit OC with the impedance adjustment function Output impedance Zout
L is the maximum value, that is, K / W0 '. Therefore, the level of the output signal at the internal node nb, that is, at the output external terminal out, tends to become a low level like the ground potential VSS after the transmission delay time tpdo of the output buffer OB in response to the ON state of the output MOSFET N20. As described above, the output impedance Zo of the output buffer OB
Since utL is set to the maximum value K / W0 ′, it is limited by the reflection potential VL0 such that VL0 = VTT−VTT × Zo / (ZoutL + Zo) = VTT × ZoutL / (ZoutL + Zo).

Needless to say, the maximum value K / W0 'of the output impedance ZoutL of the output buffer OB is set to a value larger than the characteristic impedance Zo of the transmission line L, and the reflection potential VL0 is set to a potential higher than VTT / 2. Therefore, the output signal of input buffer IB, that is, internal signal n
The internal signal ng, which is the inverted signal of c, remains at the high level even after the transmission delay time tpdi of the input buffer IB has elapsed.

As in the case of FIGS. 5 and 6, the low-level output signal output to the transmission line L from the output external terminal out changes to the high impedance state when the one-way transmission delay time tpdL has elapsed. Is totally reflected at the far end of the transmission line L at
At the point in time when L has elapsed, it reaches the output external terminal out of the logic integrated circuit device on the output side, and in response thereto, the potential of the output signal at the output external terminal out is set to a completely low level such as the ground potential VSS. You.

On the other hand, the low level change of the internal signal na, that is, the low level change of the impedance adjustment clock signal ZSCK is transmitted to the internal node nd after being delayed by a transmission delay time td of td = tpdo + tpdL + tpdi by the delay circuit DL of the output circuit OC having the impedance adjustment function. You. The transmission delay time td of the delay circuit DL is
As described above, the output buffer OB, that is, the impedance adjustment function, corresponds to the intermediate time point of the impedance determination period and determines the level of the internal signal nc, that is, the internal signal ng at the rising edge of the internal signal nd. Output impedance Zo of the output circuit OC
It can be determined whether or not utL is greater than the characteristic impedance Zo of the transmission line L.

As represented by the potential VL0 in FIGS. 8 and 9, when the level of the output signal at the internal node nb, ie, the output external terminal out during the impedance determination period is higher than the reference voltage Vref, the low level of the internal signal nc is obtained. That is, the high level of the internal signal ng is taken into the flip-flop FF2 at the rising edge of the internal signal nd, and the non-inverted output signal Q, that is, the internal signal nh is set to the high level like the power supply voltage VDD. In response to the high level of the internal signal nh and the high level of the internal signal nd, the output signal of the AND gate G2, that is, the internal signal ni is set to the high level, and the counter circuit CTRL is counted up in response to the rise of the internal signal ni. , Its count value becomes “0001”.

Thus, in the output buffer OB, the internal signal na, that is, the impedance adjustment clock signal ZSC
At the next high level change of K, two output MOSFETs N
20 and N21 are turned on, and the output impedance ZoutL of the output buffer OB, that is, the output circuit OC with the impedance adjustment function is the second largest, ZoutL = K / (W0 '+ W'). Therefore, the level of the internal node nb, that is, the output external terminal out during the impedance determination period is the potential VL1, but this potential VL1 is still higher than the reference voltage Vref, and the internal signal ng is also kept at the high level. Therefore, the flip-flop FF2 is kept in the set state even at the next rising of the internal signal nd, and the internal signal nh, which is the output signal, is kept at the high level. As a result, the internal signal ni, which is the output signal of the AND gate G2, goes high again upon receiving the next high level of the internal signal nd, and the counter circuit CTR
L is counted up and the count value is “0010”
Becomes

The output buffer OB receives the count value “0010” of the impedance control signals AL0 to AL3 and the internal signal na, that is, the next high level of the impedance adjustment clock signal ZSCK, and outputs two output MOSFETs N.
20 and N22 are turned on, the output buffer OB, that is, the output impedance ZoutL of the output circuit OC with impedance adjustment function is the third largest, and ZoutL = K / (W0 '+ 2W'). Therefore, the level of the internal node nb, that is, the output external terminal out during the impedance determination period is the potential VL2, but this potential VL2 is still higher than the reference voltage Vref, and the internal signal ng is kept at the high level. Therefore, at the next rising of the internal signal nd, the flip-flop FF2 is kept in the set state again, and the internal signal nh as an output signal is kept at the high level. As a result, the internal signal ni, which is the output signal of the AND gate G2, becomes the high level again in response to the next high level of the internal signal nd, and the counter circuit CTRL counts up, and the count value becomes "00".
11 ".

In the output buffer OB, similarly, the count value "0011" of the impedance control signals AL0 to AL3 and the internal signal na, that is, the impedance adjustment clock signal ZS
In response to the next high level of CK, three output MOSFs
ETN20 to N22 are turned on and output buffer O
B, that is, the output impedance ZoutL of the output circuit OC with the impedance adjustment function is the fourth largest, ZoutL = K / (W0 '+ 3W'). Therefore, the level of the internal node nb, that is, the output external terminal out during the impedance determination period becomes the potential VL3 lower than the reference voltage Vref, and in response to this, the internal signal ng is set to the low level. Therefore, the flip-flop FF2 is reset in response to the next rising of the internal signal nd, and the internal signal nh as an output signal is changed to a low level. This allows
When the internal signal nd is changed to the next high level, the internal signal ni as the output signal of the AND gate G2 is kept at the low level, and the counter circuit CTRL does not count up. This state is maintained until the next input of the internal signal na, that is, the impedance adjustment clock signal ZSCK, and the output buffer OB is continuously supplied with the impedance control signals AL0 to AL3 having the count value “0011”.

As is apparent from the above description, the count value “0011” of the impedance control signals AL0 to AL3 is
When the potential of the output signal at the internal node nb, that is, the reflected external potential at the output external terminal out reaches a predetermined value and becomes lower than the reference voltage Vref during the impedance determination period, in other words, the output buffer OB, that is, the output with the impedance adjusting function. The output impedance ZoutL of the circuit OC is a count value at which the output impedance ZoutL is smaller and the maximum value smaller than the characteristic impedance Zo of the transmission line L.
By holding the signal L and supplying it to the output buffer OB, the output buffer OB, that is, the output impedance ZoutL of the output circuit OC with the impedance adjustment function and the characteristic impedance Zo of the transmission line L can be matched and optimized.

In the embodiments shown in FIGS. 4 to 6 and FIGS. 7 to 9, the output impedances ZoutH and ZoutL of the output buffer OB, that is, the output circuit OC with the impedance adjusting function are determined by the counter circuit CT.
RH and CTRL, that is, the impedance control signal AH
It is switched by sequentially counting up 0 to AH3 and AL0 to AL3, and changes stepwise. Therefore, the output impedances ZoutH and ZoutH
utL and the characteristic impedance Zo have a relatively small probability of completely matching, but the output M constituting the output buffer OB is relatively small.
Gate widths W0 and W0 'of OSFETs N10 and N20
And a gate width W which is a basic unit of the gate widths of the other output MOSFETs N11 to N14 and N21 to N24.
By appropriately selecting Wout and W ′, the step width of the output impedances ZoutH and ZoutL can be reduced, and the output impedances ZoutH and ZoutL and the characteristic impedance Zo can be matched to values that are sufficiently close.

On the other hand, the impedance matching as described above is performed based on the AC reflected potential at the output external terminal out of the output circuit OC with an impedance adjustment function, and furthermore, the output circuit OC with an impedance adjustment function, that is, logic. The present invention can be implemented with the integrated circuit device or a system including the same in a normal operation state. In addition, the impedance matching can be performed for each output external terminal out of the logic integrated circuit device, that is, for each output circuit OC with an impedance adjustment function. For that purpose, a specific output external terminal out is prepared, and an external resistor is connected. No need to connect. As a result, the output impedances ZoutH and ZoutL at the time of high-level and low-level output of each output circuit OC with the impedance adjustment function are output.
Is the characteristic impedance Z due to the process variation of the MOSFETs constituting it, the wiring form of the transmission line L, etc.
o can be optimized by eliminating the influence of the variation of o, thereby improving the interface performance of a logic integrated circuit device equipped with an output circuit OC with an impedance adjustment function, and reducing the required number of external terminals and required elements. Higher speed and lower cost of the logic integrated circuit device can be achieved.

The functions and effects obtained from the above embodiments are as follows. That is, (1) an output buffer of an output circuit mounted on a logic integrated circuit device or the like having a CMOS logic gate as a basic element is provided in a parallel form between, for example, an output power supply voltage and an output external terminal; N output MOSFETs selectively turned on in response to the valid level of the corresponding bit of the impedance control signal of the first and second output control terminals, and an output external terminal and a ground potential of the circuit provided in parallel. N second output MOSFETs selectively turned on in response to the valid level of the corresponding bit of the second impedance control signal
, And for each output circuit,
When one of the input terminals is coupled to a corresponding output external terminal, the other input terminal receives a predetermined reference voltage, and a predetermined pulse signal is output via a corresponding output buffer, the high level signal is output. Or an input buffer that selectively inverts the logic level of the output signal when the reflected potential at the external terminal for output during the period until the reflected signal at the far end of the transmission line of the low level change reaches the reference voltage, The count value is used as the first or second impedance control signal, and after the count value is reset in the initial state so that the output impedance of the output circuit becomes the maximum value, the level of the output signal of the input buffer in the above period is obtained. By providing an impedance adjustment circuit including first and second counter circuits that are selectively counted up in response to inversion, -The output impedance of each output circuit can be automatically and efficiently adjusted without the need for special output external terminals for dance matching and external resistors, and with the output circuit and the system containing it in a normal operating state. The effect of matching and optimizing the characteristic impedance of the corresponding transmission line is obtained.

(2) According to the above item (1), the output MOSF
An effect is obtained that an output circuit capable of automatically optimizing the output impedance can be realized by coping with the ET process variation and the variation in the characteristic impedance of the transmission line. (3) According to the above items (1) and (2), the interface performance of a logic integrated circuit device including an output circuit is improved, the required number of external terminals and the number of external components are reduced, and the speed and cost are reduced. The effect that it can be achieved is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the block configuration of the output circuit OC with an impedance adjustment function, the effective level of each internal signal and control signal, and the polarity and absolute value of the power supply voltage and the power supply voltage for output can take various embodiments. In FIG. 2, the number and combination of output MOSFETs constituting the output buffer OB are not restricted by this embodiment, and the specific circuit configuration of the output buffer OB and the MOSFE
The same applies to the conductivity type of T and the like. In FIG. 3, the number of bits of the counter circuits CTRLH and CTRL can be arbitrarily set according to the required number of output MOSFETs provided in the output buffer OB. 5 and 6, and FIGS. 8 and 9, the absolute level and time relationship of each internal signal and control signal do not affect the gist of the present invention.

In the above embodiment, the far end of the transmission line L is set to a high impedance state during impedance adjustment. For example, the far end of the transmission line L has a resistance value corresponding to the characteristic impedance Zo. Adjustment can also be performed in the state terminated by a resistor. In this case, since there is no reflection at the far end of the transmission line L, it is necessary to individually adjust the output impedance at the time of high-level output and at the time of low-level output.

On the other hand, in the above embodiment, the output circuit OC with the impedance adjustment function mounted on the logic integrated circuit device is used.
, An input buffer IB, a delay circuit DL, flip-flops FF1 and FF2, and a counter circuit C
An impedance adjustment circuit including TRH and CTRL is provided. Such an impedance adjustment circuit divides an output circuit with an impedance adjustment function into groups, for example, using a predetermined number as a unit, and a predetermined number of impedance adjustment functions forming each group. The output circuits may be provided one by one. In this case, it is difficult to optimize the output impedance for each output circuit with an impedance adjustment function.However, an output circuit with an impedance adjustment function that may be close to the output circuit or that may have similar characteristics of the transmission line is used. By grouping, the output impedance of the output circuit with the impedance adjustment function can be matched to the AC characteristics of the output circuit with the impedance adjustment function or the transmission line while suppressing the variation.

In the above description, mainly the case where the invention made by the present inventor is applied to an output circuit mounted on a logic integrated circuit device, which is a field of application as a background, has been described. Instead, for example, the present invention can be applied to an output circuit formed as a single unit or a similar output circuit mounted on various memory integrated circuit devices. INDUSTRIAL APPLICABILITY The present invention can be widely applied to an output circuit requiring impedance matching with at least a transmission line, and an apparatus or a system including the same.

[0067]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an output buffer of an output circuit mounted on a logic integrated circuit device or the like having a CMOS logic gate as a basic element is provided in parallel between, for example, an output power supply voltage and an output external terminal, and is provided with a first impedance control. A second output MOSFET which is provided in parallel between an n first output MOSFET selectively turned on in response to an effective level of a corresponding bit of a signal, and an output external terminal and a ground potential of the circuit; And n second output MOSFETs selectively turned on in response to the effective level of the corresponding bit of the impedance control signal. For each output circuit, one input terminal is coupled to a corresponding output external terminal, the other input terminal receives a predetermined reference voltage, and a predetermined output voltage is output via a corresponding output buffer. When the reflected signal at the external terminal for output during the period until the reflected signal at the far end of the transmission line of the change of the high level or the low level reaches the reference voltage reaches the reference voltage, the logic of the output signal is output. An input buffer for selectively inverting the level, the count value of which is used as a first or second impedance control signal, and in the initial state, the count value is reset to maximize the output impedance of the output circuit; A special output external terminal for impedance matching is provided by providing an impedance adjustment circuit including first and second counter circuits selectively counting up in response to the level inversion of the output signal of the input buffer during the period. And the output circuit and the system including the output circuit are in a normal operating state without the need for an external resistor. The output impedance of each output circuit automatically matched to the characteristic impedance of the transmission line efficiently corresponding, can be optimized. As a result, it is possible to realize an output circuit capable of automatically optimizing the output impedance by coping with the process variation of the output MOSFET and the variation of the characteristic impedance of the transmission line. Interface performance and the required number of external terminals and external components can be reduced, and the speed and cost of the logic integrated circuit device and the like can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an output circuit with an impedance adjustment function to which the present invention is applied.

FIG. 2 is a circuit diagram showing one embodiment of an output buffer included in the output circuit with an impedance adjustment function of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a counter circuit included in the output circuit with an impedance adjustment function of FIG. 1;

FIG. 4 is a connection diagram showing an embodiment at the time of high-level output impedance adjustment of the output circuit with the impedance adjustment function of FIG. 1;

5 is a signal waveform diagram showing one embodiment of the output circuit with impedance adjustment function of FIG. 1 at the time of high-level output impedance adjustment.

FIG. 6 is an enlarged signal waveform diagram showing an embodiment of the output circuit with the impedance adjustment function of FIG. 1 at the time of high-level output impedance adjustment.

FIG. 7 is a connection diagram showing an embodiment at the time of low-level output impedance adjustment of the output circuit with the impedance adjustment function of FIG. 1;

8 is a signal waveform diagram showing one embodiment of the output circuit with impedance adjustment function of FIG. 1 at the time of low-level output impedance adjustment.

FIG. 9 is an enlarged signal waveform diagram showing an embodiment when adjusting the low-level output impedance of the output circuit with the impedance adjustment function of FIG. 1;

[Explanation of symbols]

OC: Output circuit with impedance adjustment function, L:
Transmission line, OB output buffer, IB input buffer, DL delay circuit, FF1 to FF2 flip-flop, CTRH, CTRL counter circuit, ZSC
K: impedance adjustment clock signal, ZSEN ...
Impedance adjustment enable signal, RST ... reset signal, na to ni ... internal node or internal signal, ou
t: external output terminal, Vref (VTT / 2): reference voltage, AH0 to AH3, AL0 to AL3, impedance control signal. V1 to V3 ... Inverters, G1 to G
2, G31 to G34, G41 to G44 ... AND (AN
D) Gates, N10 to N14, N20 to N24 ... N-channel MOSFET, W to 8W, W 'to 8W' ... M
Gate width of OSFET, VTT ... Power supply voltage for output, V
DD: power supply voltage, VSS: ground potential. FF11-F
F14 ... Flip-flop. IC …… Input circuit, Zo
ut: output impedance of output buffer and output circuit with impedance adjustment function, Zo: characteristic impedance of transmission line, tpdo, tpdi, tpdL: transmission delay time. VH0 to VH3, VL0 to VL3... Reflected potential.

Claims (6)

[Claims] 1. An output circuit whose output impedance is selectively switched based on an AC reflected potential at an output terminal in a state where a transmission line is coupled. 2. The output circuit according to claim 1, wherein a plurality of the output circuits are mounted on one semiconductor substrate surface, and each of the output circuits measures the AC reflection potential at its output terminal. An output circuit comprising an impedance adjustment circuit for identifying and selectively switching its output impedance. 3. The output circuit according to claim 1, wherein a plurality of the output circuits are mounted on one semiconductor substrate surface, and an output impedance of the output circuit is determined by the AC reflection at a predetermined output terminal of the output circuit. The predetermined output circuit selectively recognizes the AC reflected potential at its output terminal and selectively outputs a corresponding predetermined number of output impedances of the output circuits. An output circuit comprising an impedance adjustment circuit for switching. 4. The first impedance control signal according to claim 1, wherein each of the output circuits is provided in parallel between a first power supply voltage and an output terminal thereof. Are provided in parallel with each other between n output terminals and a second power supply voltage, the n first output MOSFETs each being selectively turned on by setting a corresponding bit of the output to a valid level. An output buffer including n second output MOSFETs each of which is selectively turned on when a corresponding bit of a second impedance control signal is set to a valid level. The circuit has one input terminal coupled to the corresponding output terminal, the other input terminal receiving a predetermined reference voltage, and the predetermined input via the corresponding output buffer. When a pulse signal is output, the AC reflected potential at the output terminal during a period until the reflected signal of the high level or low level change at the far end of the transmission line reaches the output terminal is equal to the reference voltage. And an input buffer for selectively inverting the logical level of the output signal when the output signal reaches the first or second impedance control signal, and in the initial state, the count value is the output of the output circuit. And a first and a second counter circuit selectively counting up in response to the level inversion of the output signal of the input buffer during the period after the impedance is reset to a maximum value. Output circuit. 5. The device according to claim 4, wherein each of the first and second output MOSFETs has a capacity of 2
An output circuit having an on-resistance of a 0-th power to an (n-1) -th power ratio. 6. The output circuit according to claim 1, wherein the output circuit is included in a predetermined logic integrated circuit device having a CMOS logic gate as a basic element. Wherein the first and second output MOSFETs are N-channel MOSFETs.