JPH05249942A - Picture sampling device of computer output image - Google Patents

Abstract

PURPOSE:To provide a picture sampling device of a computer output image capable of sampling a good quality image without receiving any influence of a clock jitter component by controlling the phase of a sampling pulse sampling an input computer image signal. CONSTITUTION:A computer output image 7a is input to an image signal input portion, is synchronized to the horizontal synchronizing signal 7b of a computer output image signal, and is converted digitally by an A/D conversion circuit 10 with a clock signal having an equal frequency to a pixel dot frequency. The generated image signal data 7g thereby, and the absolute value sum of the amplitude difference data of an image signal at a same position being apart one field or more of the image signal data 7h in an area including horizontal direction edge out of the image signal data 7g, are compared each other. The clock phase of a sampling pulse is controlled so that the absolute value sum takes the minimum value. Thereby the input computer output image is converted digitally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is optimally applied to image processing of high quality computer output video, for example, for computer output video displaying high quality images on display devices of different systems. .. More specifically, the output image of the computer is A /
In the image processing method in which D conversion is performed, some image processing is performed on the converted digital video signal data, D / A conversion is performed, and an image is displayed on a display device of a different method, a sampling issued from a sampling clock generation unit of a computer. The present invention relates to an image sampling device for computer output video, which controls the phase of a clock signal so as to obtain high quality image data close to the original video.

[0002]

2. Description of the Related Art An image output from a computer is one in which image data written in an image memory in the computer is sequentially read based on a dot clock of the computer, D / A converted, and output. Is. In the output image of the computer, the data of each pixel is independent,
Moreover, the bandwidth of the D / A-converted video signal is somewhat limited by the conversion speed of the D / A converter, but it is close to 100% even at a frequency half the dot frequency. The signal has a very wide band, which can have amplitude characteristics and also has harmonic components.

As a method of sampling and digitally converting such a wide band image, (1) a low frequency band that satisfies the Nyquist sampling theorem with respect to the sampling lock frequency as in the case of sampling a general video signal. There is a method of sampling after passing through a pass filter. However, according to this method, the sampling frequency must be set to at least a frequency higher than the dot lock frequency, but the attenuation characteristic of the Nyquist filter (filter whose pass band is a frequency lower than 1/2 the sampling frequency) is used. Considering this, unless a very high sampling frequency is set, the sampled image has a bad condition as compared with the original image. In addition, the output image of the computer has many different dot frequencies because the horizontal frequency is different even if the number of dots is the same. Therefore, a Nyquist filter with different characteristics must be used for each image. There is something wrong.

Further, as the image sampling method (2), when sampling a computer output video, a clock signal having a frequency equal to the dot frequency of the pixel of the output video is generated, and each clock of the computer output video is generated using this clock signal. There are devices that sample a well-defined stable level region of a pixel. According to this device, if the sampling phase is properly managed, the output image of the computer
It can be digitized into a form very close to the original image information.

[0005]

However, according to the image sampling apparatus of (2) described above, since the sampling clock signal has a jitter component, the sampled pixel is not clear as shown in FIG. There is no inconvenience when it is in the stable level range having an area including edges, but when it is at the change level of the boundary with adjacent pixel dots, the sampling level fluctuates with time and the image quality of the displayed image Is deteriorated.

Therefore, when the image sampling device of (2) is used, the phase must be managed so that the stable level region of pixel dots can be sampled at all times. In order to achieve such an object, it is generally considered that the sampling clock phase is controlled to sample a stable level by manual operation. However, the manual operation causes the operation accuracy to depend on an individual's visual ability and experience. Depending on the individual, the operation result varies from person to person. In addition, there is a problem in that a great amount of labor is required because the adjustment must be performed according to the change of the video signal by the human power and the change with time of the device.

Therefore, the present invention eliminates the above-mentioned drawbacks in the image sampling apparatus for computer output video, and the clock phase of the dot frequency of the pixel for sampling the computer output video without depending on human visual characteristics or experience. It is an object of the present invention to provide an image sampling apparatus for a computer output video that automatically controls the phase to obtain image data extremely close to the original video information.

[0008]

In order to achieve the above object, an image sampling device for computer output video of the present invention is synchronized with a horizontal synchronizing signal of a computer output video and has a frequency equal to a dot frequency of the computer output video. Sampling clock signal generating means (hereinafter abbreviated as "CK signal generating means") for generating the clock signal (hereinafter abbreviated as "CK signal") of
CK phase varying means for switching the clock phase of the sampling clock signal generated from the signal generating means in several stages,

Further, one of the A / D converting means for digitally converting the video signal output from the computer by the sampling clock signal switched by the CK phase varying means, and the video signal data digitally converted by the A / D converting means. An image memory for storing a copy;
The video signal data digitally converted by the D / D conversion means and the video signal data stored in the image memory are separated from the video signal data of the pixel by at least one field in a region including at least a horizontal edge. Difference data detection means for detecting the sum of absolute values of amplitude difference data between video signal data of pixels at the same position,

The absolute value sums of the amplitude difference data detected by the difference data detecting means are compared, the phase of the sampling clock signal output from the CK phase varying means which minimizes the absolute value sum is selected, and the CK And phase control means for switching the phase to the phase varying means.

[0011]

According to the image processing apparatus for computer output video of the present invention, the video signal data obtained by digitally converting the clock phase for sampling the computer output video by the A / D conversion means and the video signal stored in the image memory. A sampling clock that minimizes the sum of absolute values of amplitude difference data between video signal data of pixels at the same position temporally separated by one field or more of video signal data of pixels in an area including at least a horizontal edge of data. In addition to selecting the phase, the phase control means controls the clock phase varying means to automatically switch the phase of the sampling clock signal to the clock phase that minimizes the sum of absolute values of the selected amplitude difference data.
Therefore, since the optimum phase is controlled without being affected by the difference in visual characteristics between individuals and the difference in experience, image processing can be performed so as to display a high quality image.

[0012]

Embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of an image sampling apparatus for computer output video according to this embodiment. In FIG. 2, 8 is a sampling clock signal generating PLL circuit, and 9 is a sampling clock signal generating PLL circuit 8.
The clock phase control circuit (hereinafter abbreviated as "CK phase control circuit") capable of changing the clock phase of the sampling clock signal generated in step S10 by 10 is an output image of a computer input to an image signal input unit (not shown). An A / D conversion circuit for converting the signal 7a into a digital signal, and 4 is an image memory for storing video signal data of pixels in a region including a horizontal edge of the video signal data 7g digitally converted by the A / D conversion circuit 10. Is.

Reference numeral 11 denotes video signal data 7h of a pixel area including at least a horizontal edge of the computer output video data stored in the image memory 4, and a video signal digitally converted by the A / D conversion circuit 10. The amplitude difference data between the video signal data of the pixel at the same position separated from the data 7g by one field or more in time is compared,
It is a difference data detection circuit that detects the sum of absolute values of the amplitude difference data. 12 is a CK based on the absolute value of the amplitude difference data detected by the difference data detection circuit 11.
It is a phase control circuit that switches the phase of the sampling clock signal generated by the CK signal generation circuit 8 by the phase variable circuit 9 to a clock phase that minimizes the sum of absolute values of the amplitude difference data. 7b and 7c are each C
A horizontal sync signal and a vertical sync signal of the computer output video input to the K signal generation circuit 8 and the phase control circuit, and 10d is a signal indicating the number of dots of one line of the computer output video.

First, the CK signal generating PLL circuit 8 and C
The K phase control circuit 9 will be described. When the horizontal synchronizing signal 7b of the output image of the computer (not shown) is input to the CK signal generating PLL circuit 8 and the 1-line dot information of the computer output image is set, it becomes the horizontal synchronizing signal of the input computer output image. After the clock signal 7e that is locked and has a frequency equal to the number of dots of one line of the computer output video that has been input is subjected to phase selection control by the CK phase variable circuit 9, the conversion clock 7f of the A / D conversion circuit 10 and the system lock. Become a signal.

As shown in FIG. 3, the CK signal generating PLL circuit 8 includes a voltage control oscillator (Voltage Controll Oscilla).
The clock signal output 7e of tor (hereinafter, abbreviated as "VCO") 8-1 is input to the frequency divider 8-2. Frequency divider 8-2
Is set separately, the dot information 10d of the output image of the computer is set, the clock signal 7e is frequency-divided into a predetermined frequency division ratio, and then the horizontal comparator 7b of the input computer output image is input by the phase comparator 8-3. Compare the phase between and. The output of the phase comparator 8-3 is the loop filter 8-4.
A clock signal 7e which is input to the VCO 8-1 through the VCO 8-1 and is synchronized with the horizontal synchronizing signal of the output image of the computer by controlling the oscillation frequency of the VCO 8-3, and which is equal to the dot frequency of the pixel of the input output image. To occur. The generated clock signal 7e is then sent to the CK phase variable circuit 9 and the phase thereof is controlled. The clock signal 7f is sent to the A / D conversion circuit 10 to convert the computer output video signal 7a into a digital signal.

The CK phase variable circuit 9 described above supplies the clock signal 7e generated from the CK signal generating PLL circuit 8 as shown in FIG. 4, to n delay elements τ1, τ2 ,.
τn is sent to the delay element group 9-1 formed by vertically connecting. The clock signal 7e phase-delayed by each of the delay elements τ1, τ2, ..., τn is sent to the selector 9-2, and phase selection is performed by the phase selection signal 10i sent from the phase control circuit 12, and A / D conversion is performed. It becomes the digital conversion clock signal of the circuit 10 and the basic clock signal 7f of the system.

Next, the differential data detection system and the optimum phase control system for setting the clock phase of the clock signal for sampling the computer output video to the optimum phase so as to obtain the sampled image data faithful to the original video information will be described. To do. In the computer output video signal 7a, the absolute value sum of the amplitude difference data is detected by the difference data detection circuit 11, is input to the phase control circuit 12 (see FIG. 2), and is output from the phase control circuit 12. The phase of the clock signal 7f sent to the A / D conversion circuit 10 is changed to the optimum phase by the phase selection signal 10i (see FIG. 4) that minimizes Then, the computer output video signal is digitally converted by the A / D conversion circuit 10,
The video signal becomes 7 g. This digital video signal data 7
g is sent to the image signal processing system and the image memory 4 and the difference data detection circuit 11.

In the differential data detection circuit 11, as shown in FIG. 2, the video signal data 7g digitally converted by the A / D conversion circuit 10 and at least the video signal data 7g stored in the image memory 4 are stored. The video signal data 7h of the pixel area including the edge area in the horizontal direction is input, and the video signal data 7g digitally converted by the A / D conversion circuit 10 is located at the same position as one field away from the video signal data 7g. The absolute value sum of the amplitude difference data is compared with that of the video signal data, the absolute value sum of the amplitude difference data is obtained, and the obtained absolute value sum of the amplitude difference data is sent to the phase control circuit 12. The phase control circuit 12 selects the optimum clock phase of the sampling clock 7f that minimizes the sum of the absolute values of the amplitude difference data obtained for each clock phase of the clock signal 7f.

The differential data detection circuit 11 and the phase control circuit 12 in this embodiment have the configuration shown in FIG.
The generation of the phase selection signal 10i in the phase control circuit 12 is processed by software using the microcomputer 12-1 and the rest is processed by hardware. Figure 5
In the phase control, in the phase control, the first clock phase 7f is selected as the clock phase of the A / D conversion according to a command from the microcomputer 12-1 in the phase control circuit 12,
The amplitude difference data in the time direction is detected at the phase 7f. Most of the amplitude difference data is detected by hardware, and the microcomputer 12-1 fetches and writes the amplitude difference data at a predetermined timing. Reference numerals 12-5, 12-6, and 12-7 denote a counter circuit and a signal synthesizing circuit that create a designation signal of a two-dimensional area for detecting the amplitude difference data, respectively.
At 5, a horizontal area designation signal 4a is generated based on the horizontal synchronization signal, and at a counter 12-6, a vertical area designation signal 4b is generated based on the vertical synchronization signal. These area designating signals 4a and 4b are combined by the signal combining circuit 12-7 to become the two-dimensional area specifying signal 4c.

Then, the image memory 4 is written and read by the two-dimensional area designation signal 4c.
The image memory 4 may be, for example, a FIFO (first in, first out Fi
It is composed of a rst-in first-out memory and enables writing and reading by the secondary area designation signal 4c (en
control) to write only the image data of the area specified in each field to the image memory 4, and read the image data of the same area written at least one field before in time from the image memory 4 to obtain the difference. Corresponding video signal data 7g and 7h from which the difference data in the time direction can be detected are obtained for the data detection circuit 11.
However, in the first field after changing the setting of the clock phase, the video data at that clock phase has not yet been written in the image memory 4, so after setting the phase,
After the lapse of one field or more, it is necessary to capture the sum of absolute values of the amplitude difference data.

Corresponding video data 7g capable of detecting amplitude difference data in the direction away from one field by time,
7h is the subtracter 11- in the difference data detection circuit 11
1, the amplitude difference data between the video data 7g and 7h is obtained, and the amplitude difference data is input to the absolute value circuit 11-2 to be subjected to absolute value processing, and then the register 1 is added via the adder 11-3.
Input to 1-4. The output 4d of the register 11-4 is fed back as an input to the other of the adder 11-3. A register having an output clear function is used as the register 11-4, and the clock signal which clears the output of the register 11-4 at the vertical synchronization timing of each field and which is given to the register 11-4 is supplied to the clock gate 12-9. Is controlled so that only the area designation signal 4c becomes effective, and in order from the sampling start point of the area,
The data absolute value of the amplitude difference of each video data is feedback-added.

At the end of the designated area of each field, the sum of absolute values 4d of the amplitude difference data of the pixels at the same position in the designated two-dimensional area temporally separated by one or more fields is obtained at the output of the register 11-4. The microcomputer 12-1 in the phase control determination circuit 12 checks the detection end signal (for example, the vertical area selection signal 4b) in a predetermined field, fetches the amplitude difference data 4d in the field, and then in the microcomputer 12-1. Stored in the memory area of. Thereafter, the clock phase is updated to the next clock phase by the clock phase selection signal 10i, and the same differential data detection operation is sequentially repeated. The number of fields for detecting the difference data for each clock phase is determined only by how many times the difference information is fetched in one clock phase, and the summation or averaging process thereof can be easily processed by software. Generally, the detection accuracy increases as the amplitude difference data of a large number of fields is used, but the processing speed becomes slower. Therefore, both are determined in consideration of the actual situation.

After the detection of the amplitude difference data for each clock phase is completed, the microcomputer 12-1 compares the sum of the absolute data values of the amplitude differences stored in each phase, and determines the optimum clock phase. Basically, when the optimum clock phase is in the stable region a shown in FIG. 7, the amplitude difference data in the time direction does not appear so much, and the sum of absolute values of the amplitude difference data is small. However, in the change region b, the value increases due to the jitter component of the clock signal. Therefore, the optimum sampling clock phase can be obtained by selecting the clock phase with the smallest sum of absolute values of the amplitude differences. Further, it is possible to determine a stable clock phase in consideration of the dot frequency of the computer output video pixel and the phase delay unit amount of the CK phase variable circuit 12 and taking into consideration the information on the adjacent phases.

As the area for detecting the amplitude difference data in the time direction, as shown in FIG. 6A, the information of the area covering the boundary edge between the blacking period in one horizontal period and the effective display period of the image is used. You can also When this area is used, even in the case of a simple image where there is no horizontal edge in the input computer output video or there are very few edges, it is effective as amplitude difference information in the time direction unless the effective display area is at the black level. Information can be obtained. In this case, the width of the horizontal region may be set to a fixed width that covers the edge to some extent regardless of the input, and the position may be preliminarily considered according to the type of the output image of the computer in consideration of the scanning period of the horizontal synchronizing signal to the edge of the stable region. It is possible to register uniquely. The number of lines in the vertical direction may be determined based on the memory capacity used.

As another area for detecting the amplitude difference data in the time direction, there is also a method of using a two-dimensional block area that is movable within the effective display area, as shown in FIG. 6B. The setting values of the horizontal and vertical position counters may be changed by a microcomputer or the like. In this case, an operation switch that can be operated from the outside and an area table function that allows the operator to see the selected area are required, which complicates the configuration, but displays a landscape or characters on a black background. It is possible to detect even on such an image screen, and in an image having a complicated area with many horizontal edges, there is an advantage that the detection accuracy can be improved by selecting the area. As a method of displaying the above-mentioned selected area, for example, a circuit for adding / subtracting a constant level to / from a digital output image signal 7g shown in FIG. Can be realized by inserting.

[0026]

As is apparent from the above description, according to the computer output image processing apparatus of the present invention, a sampling clock signal equal to the dot frequency for sampling the computer output image input to the image signal input section is provided. An image memory for utilizing, and capable of switching the clock phase in several stages, A / D converting the computer output video input by the sampling clock signal, and storing a part of the converted digital video signal; The amplitude difference data in the time direction of the area including at least the horizontal edge is detected for each clock phase between the video signal read from the image memory and the digital video signal, and based on the sum of the absolute values of the detected data. Computer output video to select the clock phase that minimizes that value. Since it is possible to automatically sampled at the optimum clock phase can be sampled by the optimal phase sampling clock signal of the computer output image.

[Brief description of drawings]

FIG. 1 is a basic configuration block diagram of an image sampling apparatus for computer output video according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an image sampling device for a computer output image according to an embodiment of the present invention.

FIG. 3 is a detailed block configuration diagram of a clock signal generation circuit of the image sampling apparatus for the computer output video shown in FIG.

FIG. 4 is a detailed block diagram of a CK signal generating PLL circuit of the computer output video image sampling apparatus shown in FIG.

5 is an enlarged detailed block diagram of a differential data detection circuit and a phase control circuit in the image sampling apparatus for computer output video shown in FIG.

FIG. 6 is a configuration explanatory diagram of an image data reading and image display processing system of an image processing system of a computer output video.

FIG. 7 is a characteristic diagram showing a phase relationship between a video signal and a sampling clock in the computer output video image sampling apparatus of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CK signal generating means 2 CK phase varying means 3 A / D converting means 4 Image memory 5 Differential data detecting means 6 Phase control means 8 CK signal generating PLL circuit 9 CK phase varying circuit 10 A / D converting circuit 11 Differential data detecting means Circuit 12 Phase control circuit 7a Computer output video signal 7b Computer output video horizontal sync signal 7c Computer output video vertical sync signal 7f Phase change clock signal 7g Computer output video signal digitally converted by the A / D converter circuit Signal data

Claims (1)

[Claims] 1. A sampling clock signal generating means for generating a clock signal having a frequency equal to a dot frequency of a computer output video in synchronization with a horizontal synchronizing signal of a computer output video, and a sampling clock signal generated by the sampling clock signal generating means. Clock phase varying means for switching the clock phase of the computer in several stages, A / D converting means for digitally converting the output video signal of the computer by the sampling clock signal switched by the clock phase varying means, and the A / D converting means. An image memory for storing a part of the video signal data digitally converted by the above, the video signal data digitally converted by the A / D conversion means, and at least the horizontal direction of the video signal data stored in the image memory. Area containing the edges of In the difference data detecting means, a difference data detecting means for detecting the sum of absolute values of the amplitude difference data between the video signal data of the pixel and the video signal data of the pixel at the same position temporally separated by one field or more. A phase that compares the sum of absolute values of the detected amplitude difference data, selects the phase of the sampling clock signal output from the clock phase varying means that minimizes the sum of absolute values, and causes the clock phase varying means to switch the phase An image sampling apparatus for computer output video, comprising: a control means.