JPH05236429A - Device and method for reproducing image - Google Patents

Abstract

PURPOSE:To store still images and moving images while distinguishing them according to the information of images added to image data and to store image data for one scene of moving images as still images even when a freeze command is applied by controlling the frame rate of moving image display corresponding to a frame number added to image data read from a CD-ROM or the like. CONSTITUTION:Two image memories M1 AND M2 for the image data of moving images, and an image memory M3 for the image data of still images are prepared. Compressed image data read from the CD-ROM are extended by an extension circuit 13. The image data of moving images are alternately written in either the memory M1 or the memory M2. The image data of moving images are alternately and successively read from the memories M1 and M2 and displayed at a display device 17. When image data read from the CD-ROM and extended are still images, they are written in the memory M3. Even when the freeze command is applied, the image data are similarly written in the memory M3 as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reproducing apparatus and method, and more particularly to image reproducing which is preferably used for reading compressed image data recorded on a recording medium such as an optical disk and giving this image data to a display device. Apparatus and method.

[0002]

2. Description of the Related Art Recent optical recording media such as optical discs called CD-ROMs are used for many purposes because they can store a huge amount of data.
Especially, the image data has a very large amount of data, so CD-
The characteristics of ROM can be fully exhibited.

Compressed recording of moving image data on a CD-ROM, etc.
As a reproducing technique, there is an MPEG method. This is for predicting and reproducing a frame in the front-back direction by intra-frame coding, inter-frame coding, and motion compensation using a motion vector. In the MPEG system, the compression efficiency is improved, but the decoding unit requires an arithmetic circuit and an image memory, which increases the hardware scale.

As a technique for compressing and reproducing still images,
There is a JPEG method using intraframe coding. JPE
Even in the G system, a pseudo moving image can be reproduced by continuously decoding still image data. In other words, assuming a fixed frame rate at the time of decoding, if the amount of information is limited so that the reading and decoding time of one frame of data is less than or equal to the frame rate, a moving image can be displayed at that frame rate. However, the amount of information may be small depending on the type and size of the image, in which case the frame
Such a fixed frame rate is not desirable because it is better to increase the rate, and even if the frame rate is decreased, high-quality images are sometimes required.

[0005]

Therefore, when a moving image is intraframe-encoded at an arbitrary frame rate that can be decoded according to the amount of information, the period in which the frames are thinned is detected and the image data is decoded. We need a way to display at the original frame rate.

If the time from reading from the CD-ROM to decoding is delayed for some reason, it is necessary to take a solution for continuing the display on the display device without interruption.

Further, still image data may be read from the CD-ROM mixed with image data of a moving image. There is also a user's request to freeze (freeze) one scene of the displayed moving image as a still image.

[0008]

An image reproducing apparatus according to the present invention outputs image data frame by frame together with its frame number and image type data, and outputs when the output of image data for one frame is completed. An image data generator that generates an end signal, first and second image memories that alternately store image data of the moving image output from the image data generator for each frame, and output from the image data generator. A third image memory for storing image data of a still image, image data alternately read from the first and second image memories, or the third image memory.
A display device for displaying the image data read from the image memory, the image type / data of the image data newly generated from the image data generating device when an output end signal is generated for the previous image data represents a moving image. sometimes,
Image data of a moving image newly generated from the image data generating device is alternately written in the first or second image memory, and the image data is always written from either one of the first or second image memory. Control for controlling writing of image data to the first or second image memory and reading of image data to be displayed on the display device from the first or second image memory so that Means for writing the image data to the third image memory when the image type data of the image data generated from the image data generating device represents a still image,
Further, writing and reading of the third image memory are performed so that the image data can be read from the third image memory when a still image output end signal is generated from the image data generator. The still image control means for controlling is provided.

In one embodiment of the present invention, there is further provided switching means for selectively providing the display device with the image data read from the first or second image memory or the third image memory. There is.

According to another embodiment of the present invention, the still image control means writes the image data of the moving image output from the image data generator when a freeze command is given to the third image memory. To be crowded.

In a preferred embodiment of the present invention,
The moving image control means writes the image data in the first image memory and reads the image data from the second image memory in a first operation mode, and only reads the image data from the second image memory. A second operation mode to perform, reading image data from the first image memory, and
Third operation mode for writing image data to the image memory of
And a fourth operation mode in which only image data is read from the first image memory, writing of image data to either one of the first and second image memories is completed, and The value obtained by adding the number of frame synchronization signals appearing after the end to the frame number of the image data of the other image memory being read is equal to the frame number of the image data written in the one image memory, or When it is larger, the first or second operation mode is changed to the third operation mode, or the third or fourth operation mode is changed to the first operation mode.

In a preferred embodiment of the present invention, the still image control means also has a fifth operation mode for writing image data in the third image memory, and reading the image data from the third image memory. Outputting a still image from the sixth operating mode to the fifth operating mode when the image type data representing the still image is given or the freeze command is given. When the signal is applied, the fifth operation mode transits to the sixth operation mode.

In another embodiment of the present invention, the moving picture control means is responsive to a reset signal being applied in the first to fourth moving picture modes, and at least one of the first and second image memories. It has a clear operation mode in which data representing a constant value is written.

The still image control means writes the data representing a constant value in the third image memory in response to the reset signal being applied in the fifth or sixth operation mode. I have

In the image reproducing method according to the present invention, the image data of a moving image or a still image given together with its frame number and image type data is written in the image memory and the image data written in the image memory is read out. The method is to prepare two first and second image memories for writing and reading moving image data, and a third for writing and reading still image data.
When the image data of the previously given image data has been written into any of the above image memories, and the image type data of the newly given image data represents a moving image, Alternately write image data of a new moving image into the first or second image memory,
Further, the image data is always read from either one of the first or second image memories, and when the image type data of the given image data represents a still image, the image data of the still image is changed to the third image data. When writing to the image memory and writing of the image data of the still image are completed, the image data can be read from the third image memory.

[0016]

When the writing of the previously given image data to any of the image memories is completed and the image type data of the newly given image data represents a moving image, the image data of this new moving image Are alternately written to the first or second image memory. Further, the image data is always read from either one of the first and second image memories.

When the image type data of the supplied image data represents a still image, the image data of the still image is written in the third image memory. When the writing of the image data of the still image is completed, the third image memory enters the read mode.

First or second image memory or third
The image data read from the image memory is selectively supplied to the display device, and the image represented by the image data is displayed.

When the freeze command is given, the image data of the given moving image is written in the third image memory.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the overall structure of an image reproducing apparatus.

On an optical recording medium such as a CD-ROM, digital image data is recorded in frame units by data compression by a technique such as DCT (Discrete Cosine Transform) and encoding at an arbitrary frame rate that allows decoding. .. Further, as the additional information, a frame No. (number) and data representing the image type are recorded as a header for each frame.

The reading device 11 includes an optical head, reads compressed image data for each frame from an optical recording medium,
The compressed image data is stored in the buffer memory 12.

The decompression circuit 13 decodes the compressed image data temporarily stored in the buffer memory 12 and decompresses the compressed image data by a method such as inverse DCT, and outputs the image data in frame units.

The image reproducing apparatus comprises two frame memories M1 and M2 for moving images and a frame memory M3 for still images. The image data of one frame of moving picture decompressed by the decompression circuit 13 is passed through the gate circuit 21 or 23 under the memory control described later,
The data is alternately supplied to the memory M1 or M2 and stored.
Further, the image data of one frame of the still image expanded by the expansion circuit 13 is given to the frame memory M3 via the gate circuit 25 and stored therein.

The moving image data stored in the frame memories M1 and M2 are alternately read out one frame at a time through the gate circuit 22 or 24, and the switching circuit 18
To the display device 17. Frame memory M
The image data of the still image stored in 3 is the gate circuit.
It is read out via 26 and given to the display device 17 through the switching circuit 18.

The user of this image reproducing apparatus can input a freeze command for taking in image data of one scene (one frame) of a moving image as a still image. This freeze command may be input using a push button or switch.
When the freeze command is input, the freeze signal FRZ is generated from the CPU that controls the overall operation of the image reproducing apparatus. When this freeze signal FRZ is generated,
As will be described later in detail, one frame of moving image data output from the decompression circuit 13 is stored in the frame memory M3 as still image data.

It is possible through the switching circuit 18 to select whether to display the still image including the freeze image or the moving image on the display device 17. The switching control of the switching circuit 18 is most commonly performed in conjunction with the read / write control of the memories M1, M2, M3, but is executed by the CPU in response to the display selection input by the user. Sometimes

Writing of image data in the frame memories M1, M2, M3 is performed by memory write signals M1W, M
Controlled by 2W and M3W, the reading of image data is controlled by memory read signals M1R, M2R and M3R.

These memory write signals M1W and M2
W, M3W, memory read signals M1R, M2R, M3
R is generated in the memory control circuit 16. The image data output from the expansion circuit 13 and various timing signals generated in the timing generation circuit 15 are also applied to the memory control circuit 16. The timing generation circuit 15 is
Frame synchronization signal provided from the synchronization signal generation circuit 14 *
A timing signal to be given to the memory control circuit 16 is generated based on F (inverted signal is indicated by * instead of bar), the horizontal synchronizing signal * HS and various signals input from the expansion circuit 13. Details of these circuits 15 and 16, especially the memory control circuit 16, will be described later.

FIG. 2 shows a format of image data output from the expansion circuit 13.

Frame No. and data relating to the image type are attached to the beginning of the image data for one frame. In principle, frame numbers are assigned serial numbers. However, since some frames may be thinned out and recorded on an optical recording medium such as a CD-ROM, a frame number may be missing. The image type data represents whether the image data is a moving image or a still image.

Generally, one frame of image data is output during one frame period (1/30 seconds). However, when the decompression processing in the decompression circuit 13 takes time, it may take two frame periods (2/30 seconds) or more to output the image data for one frame.

Further, in principle, image data is continuously output from the decompression circuit 13 in each frame cycle. However, as shown by hatching in FIG. 2, the image data is output over one frame cycle or more. It may not be output. This is due to, for example, a temporary interruption of the reading process in the reading device 11.

Image data of a still image for one frame may be inserted between image data of continuous moving images. Even in such a case, as will be described later, still image data is written in the memory M3 without interruption of reproduction and display of moving image data.

FIG. 3 shows image data (data on the data bus) output from the decompression circuit 13, frame NO. Enable signal * FNE, image type enable signal * TYP.
E and the data enable signal * DATAE are shown.

The expansion circuit 13 has a system clock signal C.
K, the frame synchronizing signal * F and the horizontal synchronizing signal * HS output from the synchronizing signal generating circuit 14 are given. The expansion circuit 13 outputs the frame No. data, the image type data and the image data on the data bus (for example, 8 bits) in synchronization with the system clock signal CK.
Frame No. data consists of 3 bytes and is output over 3 clock cycles. Image type data is 1
It consists of bytes. This image type data is followed by image data.

The frame No. enable signal * FNE becomes L level when the frame No. data is being output. The image type enable signal * TYPE becomes L level when image type data is being output. The data enable signal * DATAE becomes L level when image data is being output. These various enable signals * FNE, * TYPE and * DATAE are given to the timing generation circuit 15.

The decompression circuit 13 further ends when the output of the image data for one frame is completed, the end signal We indicating the fact.
nd is generated, and this signal Wend is given to the timing generation circuit 15. Video output end signal MWend for end signal Wend
And a still image output end signal SWend.

Referring to FIGS. 4 to 8, a memory control circuit
The write / read control of the memories M1, M2, M3 by 16 will be described.

FIG. 6 shows an outline of the configuration of the memory control circuit 16. First, memory control of moving image data will be described.

The memory control circuit 16 has two registers REG.
1 and REG2 are included. These registers REG
1 and REG 2 alternately store the frame No. data of the image data given from the expansion circuit 13. One of the registers REG1 and REG2 is the selector SE
The frame No. selected by and stored in the selected register is loaded into the frame counter CN when the frame synchronization signal * F is given. When the counter clock signal (synchronized with the frame synchronization signal * F) is given, the frame counter CN adds 1 to the previously loaded value.

The comparison circuit 30 has a count value (C
N) is compared with the frame No. (REG) stored in the register (register REG1 or REG2) selected by the selector SE, and (CN) ≧ (R
EG) produces an output.

The moving image sequencer 31 is supplied with the output of the comparison circuit 30, the sequencer clock signal FCLK synchronized with the frame synchronization signal * F, the moving image end signal MWend and the moving image input signal MW. The moving image input signal MW is output from the latch circuit 33. Clock signal FC for sequencer
Image type enable signal * when LK is at L level
When TYPE (L level) is input, the image type data supplied from the decompression circuit 13 at this point is latched by the latch circuit 33.
And the moving image input signal MW or the still image input signal SW is generated according to the image type and data. Based on these input signals, the moving picture sequencer 31 follows the transition conditions shown in FIG.
It outputs 2W and memory read signals M1R and M2R.

FIG. 8 shows the operation of the memory control circuit 16 shown in FIG. In this figure, the frame sync signal *
The width of the L level is exaggerated in F. Also,
The frame synchronization signal * F shown in FIG.
8 is equivalent to the sequencer clock signal FCLK given to the moving picture sequencer 31.
In order to make it easy to understand, the clock signal FC
That is, the frame synchronization signal * F is shown instead of LK.

Further, A to K shown in FIG. 8 represent the frame number of the image data or the count value of the counter CN. A to K are consecutive numbers that increase by 1, and A +
1 = B, B + 1 = C, C + 1 = D, D + 1 = E, E + 1
= F, F + 1 = G, G + 1 = H, H + 1 = I, I + 1 =
J and J + 1 = K. Here, only the image data of frame No. J is for still images, and the rest is moving image data.

Moving picture memory M in the memory control circuit 16
The basic purpose and operation of the write / read control of 1 and M2 are as follows.

Moving image data A to I (C, E and H)
(Except for) is continuously output (focus only on the image data A to I of the moving image). As shown in FIG. 8, first, in the first frame period, the decompression circuit 13 outputs the image data of the frame No. B, and then the second frame.
The image data of frame No. D is output in the frame period of No. 5, the image data is not output in the third frame period, the image data of frame No. F is output in the fourth frame period, and the fifth frame period is output. No image data is output, the image data of frame No. G is output in the sixth frame cycle, and the image data of frame No. I is output over two frame cycles of the seventh and eighth frame cycles. To do.

The frame numbers of the image data output from the decompression circuit 13 are not continuous like B, C, D, E, F, G, and H and have a missing number. Further, when there is a missing number, there is a period in which the image data is not output during a period corresponding to the missing number such as the third and fifth frame cycles (the missing frame N
The image data with the frame No. next to O. is sent first). Further, one frame of image data may be output over two frame periods such as the seventh and eighth frame periods.

Even in such a case, the image data of the moving image is surely read out from one of the memories M1 and M2 in every frame period, and the moving image is continuously displayed on the display device 17 in the order of the frame No. Is displayed, the moving image data output from the expansion circuit 13 is written into the memories M1 and M2, and the written image data is read out from the memories M1 and M2.

In order to perform such memory read / write control, the moving picture sequencer 31 basically makes a transition between states 1 to 4 under the transition conditions shown in FIG.

In the state 1, the moving picture sequencer 31 writes the moving picture image data output from the decompression circuit 13 into the memory M1 (memory M1 write: outputs a memory write signal M1W), and the image data stored in the memory M2 is written. Read (memory M2 read: memory read signal M2R is output).

In contrast to this, in the state 3, the moving picture sequencer 31 writes the moving picture image data output from the decompression circuit 13 in the memory M2 (write memory M2: outputs memory write signal M2W) and stores it in the memory M1. The read image data is read (memory M1 read: memory read signal M1R is output).

In state 2, the moving picture sequencer 31 only reads the image data in the memory M2 (read memory M2: outputs memory read signal M2R). Memory M1
Is not written to.

In state 4, the moving picture sequencer 31 only reads the image data in the memory M1 (read memory M1: outputs memory read signal M1R). Memory M2
The image data is not written to.

When the moving picture image data output from the expansion circuit 13 is written in the memory M1, the frame number of the image data is stored in the register REG1. Expansion circuit 13
When writing the image data of the moving image output from the memory M2, the frame number of the image data is stored in the register RE.
It is stored in G2.

The state of the video sequencer 31 is state 1.
Alternatively, the frame No. stored in the register REG1 or REG2 immediately before the transition to the state 3 is loaded into the counter CN.

The counter CN is incremented for each frame synchronization signal * F.

In the period when the frame synchronization signal * F is at L level, the increment / comparison circuit of the counter CN
The fetching of the comparison result at 30, the transition between states, and the loading of the frame NO. Data of the register REG1 or REG2 into the counter CN are performed in this order.

In the transition from the state 1 to the state 3, the moving picture end signal MWend and the moving picture input signal MW are given while the frame synchronizing signal * F is at the L level (that is, image data to be inputted next is It is determined that it is a moving image), and the output of the comparison circuit 30 is (CN) ≧ (R
EG1) is satisfied (when the count value of the counter CN is stored in the register REG1, that is, greater than or equal to the frame No. of the image data written in the memory M1).

In state 1, the video end signal MWend
However, if the other conditions are not satisfied, first move to state 2 and then the frame synchronization signal * F.
In the period of L level, when the moving image input signal MW is given and (CN) ≧ (REG1) is satisfied, the state 2 is transited to the state 3.

In the state 1, the moving image end signal
When MWend is not given (for example, when the image data of the frame No. I is being written over two frame periods), the state 3 is not transited even if the frame synchronization signal * F is L level.

In the transition from the state 3 to the state 1, the moving picture end signal MWend and the moving picture input signal MW are given while the frame synchronizing signal * F is at the L level (that is, the image data to be inputted next is (Judged to be a moving image), and the output of the comparison circuit 30 is (CN) ≧ (R
EG2) is satisfied (the count value of the counter CN is stored in the register REG2, that is, the memory M).
2 is larger than or equal to the frame number of the image data written in 2.).

In state 3, the video end signal MWend
However, if the other conditions are not satisfied, first move to state 4 and then the frame synchronization signal * F.
When the video input signal MW is given and (CN) ≧ (REG2) is satisfied during the period when L is at L level, the state transits from the state 4 to the state 1.

In the state 3, the moving picture end signal
When MWend is not given, frame sync signal * F
Is at L level, it does not transit to state 1.

In addition to the basic operation described above, when still image data is input, the moving image sequencer 31 is in a read-only operation state even in state 1 or 3, and then moving image data is input. Wait until.

For example, in FIG. 8, assuming that the image data of the still image of frame No. J is given from the expansion circuit 13 after the image data of the moving image of frame No. I, the still image is input instead of the moving image input signal MW. Since the signal SW is detected, even if the video end signal MWend is given and (CN)
Even if ≧ (REG1) (specifically G + 2 ≧ I) is satisfied, the state 1 does not transit to the complete state 3,
The process waits in an incomplete state 3 in which the image data (frame No. I) is only read from the memory M1 (the image data is not written to the memory M2).

Then, the moving image data (frame
Only when the moving image input signal MW is detected by the input of NO. K), the state transits to the complete state 3 (reading of the memory M1 and writing of the memory M2). After that, if the input of the image data of the moving image continues, the transition between the states 1 and 3 (via the state 2 or 4 as necessary) is repeated.

When still image data is input, updating of the frame No. of the registers REG1 and REG2 and switching of the register by the selector SE are of course not performed.

In this way, even if still image data for a frame is input while moving image data is continuously input, the moving image is displayed on the display device 17 without interruption. .. Further, the applied still image data is written in the memory M3 as described below.

Referring again to FIG. 6, the still image sequencer 32
Includes a sequencer clock signal FCLK, a still image input signal SW, a freeze signal FRZ, and a still image end signal SW.
end inputs. The still image input signal SW is generated from the latch circuit 33 as described above and is given to the still image sequencer 32 through the gate circuit 36 which is disabled by the freeze signal FRZ. The gate circuit 36 functions to prohibit the input of a still image during the freeze. Latch circuit
33 is reset by the rising edge of the still image end signal SWend detected by the edge detection circuit 35, and returns to the original state. NA of freeze signal FRZ and still image end signal SWend
Freeze end signal * by ND logic (logic circuit 37)
FRZEND is created. The freeze end signal * FRZEND is used to reset the freeze signal REZ output from the CPU or a circuit in place of it.

Based on such an input signal, the memory M3
Image sequencer to control read / write of
Reference numeral 32 is a transition condition shown in FIG. 5, and transitions between states 5 and 6.

In state 5, the still image sequencer 32 writes the still image (or moving image in the case of freeze) image data output from the expansion circuit 13 into the memory M3 (memory M3 write: memory write signal M3W is output). ).

In state 6, the still image sequencer 32 reads out image data from the memory M3 (memory M).
3 read: Outputs memory read signal M3R).

The transition from state 5 to state 6 is performed in synchronization with the sequencer clock signal FCLK in response to the input of the still image end signal SWend. The transition from state 6 to state 5 is performed in synchronization with the sequencer clock signal FCLK when the still image input signal SW or the freeze signal FRZ is input.

For example, in FIG. 8, when the still image input signal SW is input at the time of inputting the still image data of the frame No. J, the still image sequencer 32 transits to state 5 to generate the memory write M3W. As a result, the input still image data is written in the memory M3. Next, when the still image end signal SWend is input, the still image sequencer 32 transits to state 6. As a result, the still image data written in the memory M3 can be read. As described above, since the moving image is displayed on the display device 17, the reading and display of the still image data from the memory M3 will not be actually performed. Input of still image display command from user or C
The display of still image data (reading from the memory M3 and switching control of the switching circuit 18) will be controlled according to the program of the PU.

The operation of the still image sequencer 32 when the freeze command is given is shown in the form of a timing chart in FIG.

When the freeze command is given, the still image sequencer 32 enters the state 5 in synchronization with the next sequencer clock signal FCLK, and the memory write signal M
3W occurs (becomes H level). The memory read signal M3R becomes L level. The image data for one frame output from the decompression circuit 13 is written in the memory M3.

Since the expansion circuit 13 outputs the moving image data as still image data when the freeze command is given, it generates the still image end signal SWend at the end of the image data output. In response to this signal SWend, the NAND circuit 37 outputs a freeze end signal * FRZEND, and the freeze signal FRZ is reset. In addition, the still image sequencer is synchronized with the next sequencer clock signal FCLK.
32 shifts to the state 6, the memory write signal M3W falls and the memory read signal M3R falls.

Generally, when a freeze command is input, when one frame of image data to be frozen is output, the reading device 11 stops reading the image data from the optical recording medium, and the decompression circuit 13 thereafter. Does not output image data. The image data written in the memory M3 is read out in the state 6 and given to the display device 17 via the switching circuit 18, so that the frozen still image will be displayed on the display device 17.

The timing generation circuit 15 is composed of a combination of a frequency divider circuit, a logic circuit, etc., and has a system clock signal C.
K, frame sync signal * F and horizontal sync signal * HS given from sync signal generation circuit 14 and various signals * FNE, * TYPE, * DAT given from decompression circuit 13.
Based on AE and Wend (MWend, SWend), the above-mentioned various signals for controlling the memory control circuit 16 are generated.

The timing generation circuit 15 further includes the memory write signals M1W and M1 supplied from the memory control circuit 16.
Data at the rising edge of either 2W or M3W
The request signal RQ is generated. The data request signal RQ is an OR of the memory write signals M1W, M2W and M3W. This data request signal RQ has the following 1
It is given to the decompression circuit 13 as a request to output the image data of the frame. The data request signal RQ is the end signal Wend (MWend given from the expansion circuit 13
, SWend).

Next, the operation to which the memory clear processing is added will be described.

FIG. 9 shows transition conditions between states when memory clear processing is added to the transition conditions between states in the moving picture sequencer 31 shown in FIG. FIG. 10 shows transition conditions between states when memory clear processing is added to the transition conditions between states in the still image sequencer 32 shown in FIG.

The memory clear processing in the moving picture sequencer 31 is the memory M when the reset command is given.
This is a process of writing (writing) a constant value (for example, all 0s) to 1 and reading (reading) the data of the memory M2. The memory clear process in the still image sequencer 32 is the memory M3 when a reset command is given.
Write (write) a constant value (for example, all 0s) to
Processing. Reset input from the reset input button,
In response to power-on or the like, the CPU that controls the overall operation of the image reproducing device gives a reset command to the moving image sequencer 31.

In FIG. 9, states 7 to 9 are added.

In state 7, the moving picture sequencer 31 writes data 0 in the memory M1 (write memory M1: outputs memory write signal M1W), and writes the image data (frame NO. Z data) stored in the memory M2. Read (memory M2 read: memory read signal M2R is output).

In state 8, the moving picture sequencer 31 reads the data (all 0s in this case) stored in the memory M1 (memory M1 read: memory read signal M1R is output), and the image given from the expansion circuit 13 is read. Data (data of frame No. A) is written in the memory M2 (memory M2 write: memory write signal M2W is output).

In state 9, the moving picture sequencer 31 stores the data stored in the memory M1 (all 0 in this case).
Is read only (memory M1 read: memory read signal M1R is output). State 9 is not always necessary and can be omitted.

When the reset command is given, the moving picture sequencer 31 always moves to the state 7 in any of the states 1 to 4, 8 and 9.

In FIG. 10, the state 10 is added. In state 10, the still image sequencer 32 uses the memory M3
Data 0 is written to (memory M3 write: memory write signal M3W is output).

When the reset command is given, the still picture sequencer 32 always moves to the state 10 in any of the states 5 and 6.

In these clearing processes, the CPU can specify any area of the memory M1 or M3 to clear the data.

FIG. 11 is a time chart corresponding to FIG. 8, and the operation of states 7 to 9 and 10 will be described with reference to this figure.

When the reset command is given, the moving picture sequencer 31 and the still picture sequencer 32 transit to state 7 and state 10, respectively.

The still image sequencer 32 processes the state 10
That is, the clear process of the memory M3 is executed, and when the clear process is completed, the clear end signal SClend is generated, the memory write signal M3W is lowered, and the state 10 is changed to the state 6.

The moving picture sequencer 31 executes the processing of the state 7, that is, the clear processing of the memory M1, and when the clear processing is completed, the clear end signal MClend is generated and the memory write signal M2W is raised, and the state 7 to the state 8 are entered. Transition to. At the rising edge of the memory write signal M2W, the timing generation circuit 15 generates the data request signal RQ, which is supplied to the expansion circuit 13. As a result, the expansion circuit 13 outputs the image data (frame No. A data). In state 8, this image data is written in the memory M2.

When the writing of the image data to the memory M2 is completed in the state 8, the decompression circuit 13 outputs the end signal MW.
Since the end is given, the video sequencer 31 is in state 8
To state 9.

In state 9, when one frame period elapses, the moving picture sequencer 31 outputs the memory write signal M1.
Start W and go to state 1. Memory write signal M
The data request signal RQ is generated from the timing generation circuit 15 by 1 W and is given to the decompression circuit 13, so that the decompression circuit 13 outputs the image data (frame No. B data). This image data is written in the memory M1. In state 1, the image data (frame No. A data) stored in the memory M2 is read out and displayed on the display device.
Displayed on 17.

The end signal MWend is output and A + 1 ≧
Since B is satisfied, the state 1 transits to the state 3. When the memory write signal M2W rises, the timing request circuit 15 outputs the data request signal RQ to the expansion circuit.
Given to 13.

In response to this, image data (frame NO.
When (D data) is output from the expansion circuit 13, this image data is written in the memory M2. In state 3, the image data (frame No. B data) in the memory M1 is read and displayed.

[0101]

As described above, according to the present invention, image data of a given moving image is alternately written in the first and second image memories for each frame. When image data of a still image is given, the image data is written in the third image memory. In addition, the image data stored in the first or second image memory is read out from either one of the image memories without interruption, except for a special case where a still image is displayed. Images are always displayed on the display device at a rate.

Therefore, even when the still image data is read from the CD-ROM or the like mixed with the moving image data, the still image data is surely written in the third image memory. ， In addition, the display of moving image data is not interrupted.

Further, according to the present invention, when the freeze command is given, the image data of the moving image is written in the third image memory as the image data of the still image, so that only one scene of the displayed moving image is fixed. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an image reproducing device.

FIG. 2 shows a format of image data.

FIG. 3 shows image data and signals associated therewith.

FIG. 4 is an operation state transition diagram of a moving picture sequencer.

FIG. 5 is an operation state transition diagram of a still image sequencer.

FIG. 6 is a block diagram showing a configuration example of a memory control circuit.

FIG. 7 is a timing chart showing the operation of the memory control circuit.

FIG. 8 is a timing chart showing a read / write processing operation of image data.

FIG. 9 is an operation state transition diagram of a moving picture sequencer including a clear operation.

FIG. 10 is an operation state transition diagram of the still image sequencer including a clear operation.

FIG. 11 is a timing chart corresponding to FIG. 8 including a clear operation.

[Explanation of symbols]

 13 Expansion circuit 15 Timing generation circuit 16 Memory control circuit 17 Display device 30 Comparison circuit 31 Video sequencer 32 Still image sequencer 33 Image type input signal generation circuit (latch circuit) M1, M2, M3 Image memory REG1, REG2 register SE selector CN counter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/92 H 8324-5C

Claims (12)

[Claims] 1. An image data generator for outputting image data in units of frame together with its frame number and image type data, and generating an output end signal when output of image data for one frame is completed, said image First and second image memories for alternately storing the image data of the moving image output from the data generator for each frame, and a third image for storing the image data of the still image output from the image data generator. A memory, a display device for displaying the image data alternately read from the first and second image memories or the image data read from the third image memory, and an output end signal is generated for the previous image data and When the image type data of the image data newly generated from the image data generator represents a moving image, Image data of a moving image newly generated from the data generating device is alternately written in the first or second image memory, and the image data is always written from either one of the first or second image memory. Moving image control means for controlling writing of image data to the first or second image memory and reading of image data to be displayed on the display device from the first or second image memory so as to be read out. ，
Also, when the image type data of the image data generated from the image data generating device represents a still image, the image data is written in the third image memory, and the output of the still image from the image data generating device is completed. Image reproduction including still image control means for controlling writing and reading of the third image memory so that the image data can be read from the third image memory when a signal is generated. apparatus. 2. The image according to claim 1, further comprising switching means for selectively providing the display device with the image data read from the first or second image memory or the third image memory. Playback device. 3. A first operation mode in which the moving image control means writes image data in the first image memory and reads image data from the second image memory, and an image from the second image memory. A second operation mode in which only data is read, a third operation mode in which image data is read from the first image memory and image data is written in the second image memory, and from the first image memory Has a fourth operation mode in which only the image data is read out, the writing of the image data into either one of the first and second image memories is completed, and the frame synchronization signal which appears after the completion of the writing. The value obtained by adding the number of is added to the frame number of the image data of the other image memory being read is
When the frame number of the image data written in the one image memory is equal to or larger than the frame number, the first or second operation mode is changed to the third operation mode, or the third or fourth operation mode is changed to the third operation mode. The image reproducing apparatus according to claim 1, wherein the image reproducing apparatus transits to the operation mode 1. 4. The still image control means has a fifth operation mode for writing image data into the third image memory and a sixth operation mode for reading image data from the third image memory. , When image type data representing a still image is given,
Alternatively, when the freeze command is given, the sixth operation mode is changed to the fifth operation mode, and when the still image output end signal is given, the fifth operation mode is changed to the sixth operation mode. The image reproducing apparatus according to claim 1, wherein 5. The still image control means writes the image data of the moving image output from the image data generator in the third image memory when a freeze command is given. Image playback device. 6. The moving image control means writes data representing a constant value in at least one of the first and second image memories in response to a reset signal being applied in the first to fourth moving image modes. 4. The image reproducing apparatus according to claim 3, which has a clear operation mode. 7. The still image control means is a fifth or sixth device.
5. The image reproducing apparatus according to claim 4, which has a clear operation mode for writing data representing a constant value in the third image memory in response to a reset signal being applied in the operation mode. 8. A method for writing image data of a moving image or a still image, which is given together with its frame number and image type data in frame units, into an image memory and reading the image data written in the image memory. Two first for writing and reading the image data of
And a second image memory are prepared, and a third image memory is prepared for writing and reading the image data of the still image, and the writing of the image data given previously to one of the above image memories is completed. And the image type data of the newly provided image data represents a moving image, the image data of this new moving image is added to the first or second image data.
Alternately writing to the image memory of
The image data is always read out from either one of the image memories, and when the image type data of the given image data represents a still image, the image data of the still image is read as the third image data.
The image reproducing method, in which the image data can be read from the third image memory when the writing of the image data of the still image is finished in the image memory. 9. The image data read from the first or second image memory or the third image memory is selectively applied to a display device to display an image represented by the image data. Image playback method. 10. When a freeze command is given,
The image reproducing method according to claim 8, wherein image data of a given moving image is written in the third image memory. 11. A first operation mode in which image data is written in the first image memory and image data is read out from the second image memory, and only image data is read out from the second image memory. Second operation mode, third image mode for selecting image data from the first image memory and writing image data to the second image memory, only reading image data from the first image memory And a fifth operation mode for writing image data into the third image memory, and a sixth operation mode for reading image data from the third image memory. And the number of frame sync signals appearing after the writing of the image data to either one of the second image memory is completed and the writing of the image data is completed. A value obtained by adding the frame number data,
When the condition that the frame number of the image data written in the one image memory is equal to or larger than the condition is satisfied, the operation mode is changed from the first or second operation mode to the third operation mode or the third or fourth operation mode. When transitioning from the operating mode to the first operating mode and image type data representing a still image is given,
Alternatively, when the freeze command is given, the sixth operation mode transits to the fifth operation mode, and when the still image output end signal is given, the fifth operation mode transits to the sixth operation mode. The image reproducing method according to claim 8. 12. A data representing a constant value is provided to at least one of the first and second image memories and a third image memory in response to a reset signal being applied in the first to sixth operation modes. The image reproducing method according to claim 8, wherein a transition is made to a writing clear operation mode.