JPH05235295A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a highly integrated high-performance DRAM cell from a more simplified production process in the manufacture of the DRAM cell provided with an information storing capacitor located directly below a transfer transistor by a wafer adhering technique. CONSTITUTION:On a p-type silicon semiconductor substrate, an information storing capacitor comprising a storage electrode, a capacitor insulating film 30 and a cell plate electrode film 31 is formed via insulating film 25 made of Si3N4. And N-type silicon semiconductor substrate 32 is adhered to a cell plate electrode film 31 flattened by polishing, and the exposed surface of a p-type silicon semiconductor substrate is polished by using an insulating film 24 for element separation. And an information staring transistor where a n-type source region 35 came into contact with the storage electrode is formed in the p-type silicon semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a dynamic random access memory (DR) having an information storage capacitor.
AM).

[0002]

2. Description of the Related Art Currently, highly integrated and large capacity DRAM
This memory cell is composed of one transfer transistor and one information storage capacitor. When the DRAM is highly integrated, how to reduce the occupied area of the memory cell while maintaining the capacitance value of the information storage capacitor is an important issue. At the same time, there is also a problem of how to suppress the short channel effect caused by the miniaturization of the transfer transistor.

In recent years, a trench structure and a stack structure have been proposed with respect to these points. However, there are problems with the trench structure in terms of cleaning, uniform oxidation, filling, etc. inside the trench. On the other hand, the stack structure has its own problems such as a limit in terms of surface flattening. Therefore, a method has been proposed in which the information storage capacitor is formed directly below the transfer transistor by a wafer bonding technique. According to this, since the memory cell occupies only about one transfer transistor area in a plan view, it is smaller than the conventional one, and the capacity of the information storage capacitor can be maintained. You can This technique is described in Japanese Patent Laid-Open No. 3-218664.

A method of manufacturing a semiconductor memory device according to a conventional example will be described below in the order of steps with reference to the drawings. See FIG. 14: The P-type silicon semiconductor substrate (2) is attached to the glass substrate (1), and then the semiconductor substrate (2) is surface-polished to a predetermined thickness.

Referring to FIG. 15, a recess is formed in the semiconductor substrate (2) by selective etching, and then an n ⁺ type storage electrode film (3) of an information storage capacitor made of silicon containing impurities is formed by CVD. .. 16 See the silicon selective thermal oxidation method to form an element isolation oxide film composed of SiO ₂ (4), forming a subsequent dielectric layer of the information storage capacitors formed of SiO ₂ by thermal oxidation (5) .. Subsequently, the cell plate electrode film (6) of the information storage capacitor made of polycrystalline silicon is formed by the CVD method.

Referring to FIG. 17, a flattening film (7) made of SiO ₂ is formed by a CVD method, and the flattening film (7) is polished so as to be close to a mirror surface. Then, the silicon semiconductor substrate (8) is attached to the flattening film (7). See FIG. 18: The glass substrate (1) is etched and removed by applying a dipping method using hydrofluoric acid as an etchant.

See FIG. 19: By the silicon selective oxidation method,
An oxide film (9) for element isolation is formed on the surface of a silicon semiconductor substrate (2), and a gate insulating film (10) is formed by a thermal oxidation method.
To form. Then, the gate electrode (11) of the transfer transistor made of polycrystalline silicon is formed. And
An n ⁺ type source region (12) and an n ⁺ type drain region (13) are formed by ion implantation. The n ⁺ type source region (12) is in contact with the protruding portion of the storage electrode film (3) of the information storage capacitor located therebelow.

Referring to FIG. 20, an insulating film (14) made of SiO ₂ covering the gate electrode (11) is formed by a thermal oxidation method. After that, the interlayer insulating film (15) made of a PSG film, the bit line (16) made of an aluminum film and the PSG in contact with the n ⁺ -type drain region (13) are formed as usual.
A cover film (17) made of a film is formed.

[0009]

However, in the semiconductor memory device manufactured by the above-described manufacturing method,
There are the following problems. In order to manufacture one finished product wafer, it is necessary to prepare three substrates and attach these substrates.
The manufacturing process is long and complicated. . That is, the glass substrate (1) according to the conventional example, the silicon semiconductor substrate (2), it is necessary to third substrate of the silicon semiconductor substrate (8 n ⁺ -type drain region (13) and the lower stress -
Since it is only separated from the storage electrode film (3) via the P-type silicon semiconductor substrate (2), when a voltage is applied to the storage electrode film (3), a punch-through shock is generated.
It may cause a malfunction and cause a malfunction. When polishing the silicon semiconductor substrate (2) adhered to the glass substrate (1), the finished thickness is likely to vary, and when the finished thickness is thicker than the desired thickness, the n ⁺ type source region (12) and the storage layer are formed. The contact with the di-electrode film (3) cannot be made, resulting in a disconnection. The structure of the transfer transistor is a normal structure formed on the silicon semiconductor substrate (2), and the structure of the SOI (Si
Since the structure is not a Licon On Insulator structure, it is difficult to obtain a high current driving force while suppressing the short channel effect when miniaturization is advanced.

[0010]

The present invention has been made in view of the above-mentioned problems, and includes a step of forming an element isolation oxide film (24) on a P-type silicon semiconductor substrate (21) and the semiconductor. A step of forming an insulating film (25) on the substrate (21), a step of selectively etching the insulating film (25) to form a storage electrode contact window (25a), and an insulating film (25) A step of forming a polysilicon film (26) which becomes a part of the storage electrode film by burying the storage electrode contact window (25a) thereon, and a capacitor insulating film (30) on the polysilicon film (26). ) Forming step, forming a flattened cell plate electrode film (31), and adhering an N-type silicon semiconductor substrate (32) to the cell plate electrode film (31), P-type silicon semiconductor substrate ( 21) polishing the exposed surface until the surface of the element isolation oxide film (24) is exposed,
The n ⁺ -type source region (35) contacting the polysilicon film (26) in the storage electrode contact window (25a), and the n insulated from the polysilicon film (26) through the insulating film (25) ^And a step of forming a transfer transistor having a ⁺ type drain region (36).

[0011]

According to the above-described means, the information storage capacitor is formed immediately below the transfer transistor by the sticking technique of the P-type silicon semiconductor substrate (21) and the N-type silicon semiconductor substrate (31). The cells can be highly integrated, and the number of bonded wafers required to obtain one DRAM completed wafer can be reduced to two.

An insulating film (2) is provided between the n ⁺ type drain region (36) and the polysilicon film (26) therebelow.
Since 5) is interposed, the punch through in the conventional example-
It is possible to prevent the short state caused by. Furthermore, a P-type silicon semiconductor substrate (2
Since the thickness of 1) is accurately controlled by the thickness of the oxide film for element isolation (24) which serves as a stopper during polishing, the n ⁺ type source region (35) and the polysilicon film are 26) can be reliably contacted.

Furthermore, the transfer transistor has an SOI (Silicon On Insu) having a thin active layer.
(lator) structure, the current drive capacity is improved,
And the short channel effect can be reduced.

[0014]

1 to 13 are process sectional views showing an embodiment of a method for manufacturing a semiconductor memory device according to the present invention, which will be described in detail below with reference to the drawings. Referring to FIG. 1: First, a P-type silicon semiconductor substrate (21) is prepared, and the pad oxide film (22) made of SiO ₂ and having a thickness of about 500 Å is formed into a P-type by thermally oxidizing it at a temperature of 950 ° C. and HBW + HCl oxidation. Silicon semiconductor substrate (21)
Form on top. Then, a silicon nitride (Si ₃ N ₄ ) film (23) having a thickness of about 1500 Å is deposited on this by a low pressure CVD method. Then, by applying a photo-etching technique, the silicon nitride film (23) is patterned to leave the silicon nitride film (23) only in the region where the transfer transistor and the information storage capacitor are formed.

See FIG. 2: By using the silicon nitride film (23) as an oxidation resistant mask and performing selective silicon thermal oxidation under conditions of a temperature of 1000 ° C. and wet O ₂ oxidation,
An oxide film (24) for element isolation having a thickness of about 5000Å is formed. See FIG. 3: By a dipping method using phosphoric acid as an etchant, a silicon nitride film (2
3) is removed. Further, the pad oxide film (22) may be removed thereafter by an immersion method using hydrofluoric acid as an etchant. Then, a thickness of about 300 is obtained by the low pressure CVD method.
An insulating film (25) made of 0Å Si ₃ N ₄ is formed. This insulating film (25) is a storage electrode film (29) described later.
Is for ensuring electrical insulation between the n ⁺ type drain region (36) and the n ⁺ type drain region (36).

Referring to FIG. 4, the storage electrode contact window (25a) is opened by selectively etching the pad oxide film (22) and the insulating film (25) by applying a photo-etching technique. See FIG. 5: A low pressure CVD method is used to deposit a polysilicon film (26) having a thickness of about 3000 Å and to fill the storage electrode contact window (25a). And P
By the impurity diffusion method using OCl ₃ as a source, phosphorus is doped into the polysilicon film (26) to reduce the resistance.

Referring to FIG. 6, a SiO ₂ film having a thickness of about 2 μm is deposited by the low pressure CVD method. Then, a photolithography technique is applied to selectively etch the SiO ₂ film to leave the columnar film (27) only in the region where the information storage capacitor is formed. Here, the area of the columnar film (27) when viewed in a plane is selectively etched so as to be, for example, a circular area.

See FIG. 7: A low pressure CVD method is used to deposit a polysilicon film (28) having a thickness of about 2000 Å which covers the columnar film (27) and the polysilicon film (26). Then, phosphorus is doped into the polysilicon film (28) by an impurity diffusion method using POCl ₃ as a source to reduce the resistance.

Referring to FIG. 8, the polysilicon film (28) is etched by applying an anisotropic etching method (anisotropic etchback method) without using a photoresist, and only the side surface of the columnar film (27) is etched. , Cylindrical polysilicon film (28
leave a). As a result, the polysilicon film (26) is connected to one end surface of the polysilicon film (28a), and the polysilicon film (26) and the cylindrical polysilicon film (28a) are integrated to form a storage electrode film. (29) is formed.
As described above, the storage electrode (29) has the cylindrical polysilicon film (28a) having a large surface area.
The capacity of the information storage capacitor can be increased.

See FIG. 9: The columnar film (27) is removed by a dipping method using hydrofluoric acid as an etchant. Then, by the low pressure CVD method on the surface of the storage electrode (29),
A Si ₃ N ₄ film having a thickness of about 120Å is formed, and then the temperature is set to 9
The surface of the Si ₃ N ₄ film is oxidized under dry oxidation conditions at 00 ° C. to form a capacitor insulating film (30).

Referring to FIG. 10, a cell plate electrode film (31) of a storage electrode film (29) made of a polysilicon film having a thickness of about 2 μm is formed by a low pressure CVD method. The cell plate electrode film (31) is used for the storage electrode (2
It is formed so as to fill the recess of 9). And POCl
_By the impurity diffusion method using ₃ as a source, phosphorus is doped into the cell plate electrode film (31) to reduce the resistance. Then, polishing is performed to flatten the surface of the cell plate electrode film (31).

See FIG. 11: Cell plate electrode film (31)
Then, the N-type silicon semiconductor substrate (32) is attached. Since the conductivity type of the cell plate electrode film (31) is N type, the ohmic electrical connection with the N type silicon semiconductor substrate (32) is made by sticking. Therefore, the external connection electrode of the cell plate electrode film (31) can be taken out from the back surface of the N-type silicon semiconductor substrate (32). Then, the P-type silicon semiconductor substrate (21) is thinly polished until the surface of the element isolation oxide film (24) is exposed, and the surface is finished to be a mirror surface.

Referring to FIG. 12, a gate insulating film (33) having a thickness of about 170 Å is formed on the surface of the P-type silicon semiconductor substrate (21) by a thermal oxidation method. After this, for example, a gate electrode (34) in which polysilicon and silicide (WSi _2, etc.) are laminated is formed. And the gate electrode (34)
Phosphorus or arsenic is implanted into the surface of the P-type silicon semiconductor substrate (21) by an ion implantation method using as a mask,
n ⁺ type source region (35) and n ⁺ type drain region (3
6) is formed. Here, n ⁺ type source region (35)
Adjusts the acceleration voltage and dose of ion implantation so that the storage electrode contact window (24a) is in contact with the buried polysilicon film (26). Note that P
The thickness of the type silicon semiconductor substrate (21) uses the element isolation oxide film (24) as a stopper as described above, so that the variation can be controlled very small, and the acceleration voltage and the dose amount of the ion implantation can be controlled. Adjustment can be done easily.

As a result, a transfer transistor in which the n ⁺ type source region (35) is electrically connected to the storage electrode film (29) is completed. See FIG. 13: Then, as in a conventional method, the bit line (3) made of an aluminum film or the like is contacted with the interlayer insulating film (37) made of the BPSG film and the n ⁺ type drain region (36).
8), PSG film or Si ₃ N ₄ film
Forming an ionization film (39).

In the semiconductor memory device manufactured by the manufacturing process as described above, since the information storage capacitor is formed immediately below the transfer transistor by the wafer sticking technique, the memory cell is viewed as a plane. Since it occupies an area of approximately one transfer transistor, it is possible to reduce the size of the memory cell while maintaining the capacitance value of the information storage capacitor.

Moreover, the number of wafers required to complete one wafer is the P-type silicon semiconductor substrate (21).
Also, the number of the N-type silicon semiconductor substrates (32) is only two, which is one less than that of the conventional example, so that the manufacturing process can be shortened. Since the storage electrode film (29) is composed of the polysilicon film (26) and the cylindrical polysilicon film (28a), the cylindrical polysilicon film (28) is formed.
The capacitance value can be freely set by increasing the height of a).

The transfer transistor is formed on the pad oxide film (22) and the insulating film (25), and is a so-called SOI (Silicon On Insulator).
or) structure. Moreover, the thickness of the P-type silicon semiconductor substrate (21), which is the active layer of the transfer transistor, must be accurately controlled by the thickness of the element isolation oxide film (24) that serves as a stopper during polishing. SO that has a thin active layer of about 2000Å
An I-type transfer transistor can be manufactured. This allows
The current driving capability of the transfer transistor can be improved and the short channel effect can be reduced. Although the element isolation oxide film (24) is formed to a thickness of about 5000Å in the present embodiment, the active layer can be formed to a thickness of about 1000Å by making it thinner. ..

Further, since the transfer transistor is formed after the information storage capacitor is formed, the heat treatment amount after forming the transfer transistor can be small. Thus n ⁺ -type source - it is possible to shallow source region (35) and n ⁺ -type drain diffusion depth of the region (36), it is possible to promote miniaturization of the transfer transistor. In the above-described embodiment, the storage electrode film (29) is the polysilicon film (26) and the cylindrical polysilicon film (28a).
And a cylindrical polysilicon film (2
8a) may be formed into a polysilicon film having another shape (for example, fin-shaped polysilicon film), or a step of forming a cylindrical polysilicon film (28a) portion having a reduced capacitance value. Can be omitted.

[0029]

According to the method of manufacturing a semiconductor memory device of the present invention, the following effects can be obtained, so that a highly integrated and highly integrated DRAM cell can be manufactured by a more simplified manufacturing process. it can. The number of wafers required to complete two DRAM wafers can be reduced from three in the conventional example to two, and the number of wafer bonding steps can be reduced from twice to once. n ⁺ -type drain region (36) and the underlying storage region
Since the insulation between the di-electrode film (29) and the di-electrode film (29) is made by the thick insulating film (25), it is possible to prevent the short state due to the punch through in the conventional example. The thickness of the P-type silicon semiconductor substrate (21) which becomes the active layer of the transfer transistor is accurately controlled by the thickness of the element isolation oxide film (24) which serves as a stopper during polishing. The n ⁺ type source region (35) and the storage electrode film (29) can be reliably contacted. Since the transfer transistor has the SOI structure having the thin active layer, the current driving capability can be improved and the short channel effect can be reduced.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 3 is a third cross-sectional view showing the method for manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 5 is a fifth cross-sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 6 is a sixth cross-sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 7 is a seventh cross-sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 8 is an eighth cross-sectional view showing the method for manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 9 is a ninth cross-sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the invention.

FIG. 10 is a tenth sectional view showing the method of manufacturing the semiconductor memory device according to the example of the present invention.

FIG. 11 is an eleventh sectional view showing the method for manufacturing the semiconductor memory device according to the example of the present invention.

FIG. 12 is a twelfth sectional view showing the manufacturing process of the semiconductor memory device according to the example of the present invention.

FIG. 13 is a thirteenth sectional view showing the manufacturing process of the semiconductor memory device according to the example of the present invention.

FIG. 14 is a first cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional example.

FIG. 15 is a second cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional example.

FIG. 16 is a third cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional example.

FIG. 17 is a fourth cross-sectional view showing the manufacturing process of the conventional semiconductor memory device.

FIG. 18 is a fifth cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional example.

FIG. 19 is a sixth cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional example.

FIG. 20 is a seventh cross-sectional view showing the manufacturing process of the semiconductor memory device according to the conventional example.

Claims (2)

[Claims] 1. A step of forming an element isolation oxide film (24) on a first conductivity type first semiconductor substrate (21), and a step of forming an insulating film (25) on the semiconductor substrate (21). When,
A step of selectively etching the insulating film (25) to form a storage electrode contact window (25a); and a step of forming the storage electrode contact window (25a) on the insulating film (25).
A step of forming a polysilicon film (26) which becomes a part of the embedded storage electrode film, and the polysilicon film (26)
A step of forming a capacitor insulating film (30) thereon, a step of forming a flattened cell plate electrode film (31), and a second semiconductor having a conductivity type opposite to that of the cell plate electrode film (31). The step of attaching the substrate (32), and the exposed surface of the first semiconductor substrate (21) on the oxide film (24) for element isolation.
Polishing until the surface of the polysilicon film is exposed, and the polysilicon film (26) is contacted with the polysilicon film (26) via the source region (35) and the insulating film (25) in the storage electrode contact window (25a). 26) and a step of forming a transfer transistor having an insulated n ⁺ type drain region (36). 2. A step of forming an element isolation oxide film (24) on a one-conductivity type first semiconductor substrate (21), and a step of forming an insulating film (25) on the semiconductor substrate (21). When,
A step of selectively etching the insulating film (25) to form a storage electrode contact window (25a); and a step of forming a polysilicon film (26) filling the storage electrode contact window (25a). And the polysilicon film (2
6) SiO ₂ is formed on the area where the information storage capacitor is formed.
A step of forming a columnar film (27) made of, a step of forming a polysilicon film (26) and a polysilicon film (28) covering the columnar film (27), and the polysilicon film (2
By performing anisotropic etching of 8), the columnar film (2
A cylindrical polysilicon film (28a) is formed on the side surface of 7), and the polysilicon film (26) and the cylindrical polysilicon film (28a) are integrated to form a storage electrode film (2).
9), a step of forming a capacitor insulating film (30) on the storage electrode film (29) after removing the columnar film (27), and a storage electrode film (29).
A step of forming a flattened cell plate electrode film (31) by burying the recesses of the second step, and a second semiconductor substrate (3) having an opposite conductivity type with respect to the cell plate electrode film (31).
2) is attached, a step of polishing the exposed surface of the first semiconductor substrate (21) until the surface of the element isolation oxide film (24) is exposed, and a storage electrode film (29). The source region (35) to contact, and the insulating film (2
5) The step of forming a transfer transistor having a drain region (36) insulated from the polysilicon film (26) through 5).