JP3981851B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device including a transistor using a high dielectric film or a ferroelectric film as a gate insulating film.
[0002]
At present, the thinning of the gate insulating film in a transistor is becoming a limit, so a transistor that achieves the same effect as the thinning is realized by forming the gate insulating film using a material with high dielectric constant. However, in the case of using a material having a high dielectric constant, that is, a high dielectric material or a ferroelectric material, since the self-alignment method that has been widely used in the past cannot be adopted, the present invention solves this problem. Means are disclosed.
[0003]
[Prior art]
In general, in the field of manufacturing an integrated circuit device including a transistor, a memory cell, and the like, a self-alignment method has been frequently used when forming a transistor.
[0004]
This self-alignment method is a very well-known technique and does not need to be explained. However, it is meaningful to clarify that the present invention is different from the conventional technique. Will be described.
[0005]
FIG. 18 and FIG. 19 are side sectional views showing a principal part of a semiconductor device in a process point for explaining a conventional example. In the semiconductor device described here, element isolation is performed by a LOCOS (local oxidation of silicon) method.
[0006]
Refer to FIG.
18- (1)
An active element (transistor) region in the Si semiconductor substrate 101 is covered with a silicon nitride film 102 which is an oxidation resistant film, and then thermal oxidation is performed to form a field insulating film 103.
[0007]
Refer to FIG.
18- (2)
The gate insulating film 104 is formed by removing the silicon nitride film 102 to expose the active element region in the Si semiconductor substrate 101 and then performing thermal oxidation.
[0008]
18- (3)
After forming the conductor material film, patterning is performed to form the gate electrode 105.
[0009]
Refer to FIG.
18- (4)
Ions are implanted using the gate electrode 5 and the field insulating film 3 as a mask to form a low impurity concentration region 106 having an LDD (lightly doped drain) structure.
[0010]
Refer to FIG.
19- (1)
An insulating film is formed on the entire surface and then anisotropic etching is performed to form side walls 107 on the side surfaces of the gate electrode 105.
[0011]
19- (2)
Ions are implanted using the side wall 107, the gate electrode 105, and the field insulating film 103 as a mask to form a high impurity concentration region 108 having an LDD structure.
[0012]
19- (3)
High-temperature heat treatment is performed to activate the ion-implanted impurities, and a low impurity concentration source region 106S, a high impurity concentration source region 108S, a low impurity concentration drain region 106D, and a high impurity concentration drain region 108D are formed.
[0013]
See FIG. 19 (B)
19- (4)
After the insulating film 109 is formed, an electrode contact window is formed, and a source electrode 110S that contacts the high impurity concentration source region 108S, a drain electrode 110D that contacts the high impurity concentration drain region 108D, and the like are formed.
[0014]
In the above-described conventional example, the element isolation is performed by the field insulating film 3 formed by the LOCOS method, but it is also performed by using the STI (shallow trench isolation) method.
[0015]
FIG. 19C is a cutaway side view showing a main part of a semiconductor device having a field insulating film 111 formed by the STI method. The same symbols as those used in FIG. 18 to FIG. Express or have the same meaning.
[0016]
Since the step of forming the field insulating film 111 by the STI method is exactly the same as that of the second embodiment of the present invention described later with reference to FIG. 7, the description should be referred to.
[0017]
According to the conventional example, there is no positional deviation between the gate electrode and the source region or the drain region. Therefore, the transistor characteristic variation is small, and the performance of the integrated circuit device is improved. The alignment method is now an indispensable technique for manufacturing transistors.
[0018]
By the way, in the integrated circuit device, since the degree of integration is improved, and accordingly, the transistor size is required to be reduced, the gate insulating film must also be thinned. However, the thinning is no longer the physical limit. In place of the conventional gate insulating film formed of, for example, an oxide film, an insulating film having a high dielectric constant, that is, a high dielectric film or a ferroelectric film is being used.
[0019]
Currently, SiO₂The thickness of the thinnest gate insulating film using silicon is about 15 [Å], which is only about 3 layers in the atomic layer, and if there is a slight variation in the distribution of atoms, there are two atomic layers or A portion of one layer is generated locally, and if this is the case, naturally a leakage current easily flows.
[0020]
In order to solve this problem, the gate insulating film should be thickened within a range that does not affect the lithography technique, but in such a case, sufficient capacity cannot be obtained between the channel and the gate electrode. Therefore, it is necessary to use a high dielectric material or a ferroelectric material as the material of the gate insulating film.
[0021]
If the dielectric constant in the material of the gate insulating film is high, even a thick film is electrically equivalent to a thin film, so it is necessary to reduce the thickness of the gate insulating film according to the transistor size reduction rule. Therefore, reliability can be improved in terms of leakage current resistance.
[0022]
At present, various research and development are being conducted to put a nonvolatile memory element into practical use in place of a volatile memory element such as a DRAM (dynamic random access memory) that has been widely used.
[0023]
In particular, research and development have been conducted on a one-transistor type memory device having a 1-bit storage function using a ferroelectric film as a gate insulating film and using only one transistor.
[0024]
If such a memory element can be realized, the following advantages can be obtained when compared with a DRAM having one transistor and one capacitor as one memory element.
(1) The degree of integration can be increased more than twice.
{Circle around (2)} Since it is a non-volatile memory, it does not require power for storage and can save energy and use it for a long time.
(3) Since the battery can be reduced in size, the entire system can be reduced in size.
(4) Since the memory can be always kept, the system can be used immediately when necessary. By the way, in the current personal computer, it is necessary to write information from the hard disk to the DRAM after turning on the power, and it takes 2 [minutes] to [3 minutes] to start up. Convenience is not good.
[0025]
As described above, the one-transistor type memory element has various excellent points, but is not yet in a state of mass production of practical ones. It is that the self-alignment method cannot be applied when forming the transistors to be formed.
[0026]
That is, when the activation heat treatment is performed on the source region and the drain region formed by the self-alignment method, it is natural that the gate insulating film already exists under the gate electrode. If the insulating film is an oxide film as in the prior art, no problem occurs. However, a high dielectric material or a ferroelectric material cannot withstand the heat treatment temperature, resulting in the following problems.
(1) Leakage current increases remarkably.
(2) Hysteresis (irreversible) characteristics are lost in the case of a ferroelectric.
[0027]
In order to avoid this problem related to the gate insulating film, the conventional self-alignment method may be abandoned and the gate insulating film may be formed after the impurity activation heat treatment of the source region and the drain region. On the other hand, it is difficult to form the source region and the drain region without misalignment, and it becomes impossible to make a fine transistor uniformly and achieve high integration.
[0028]
[Problems to be solved by the invention]
In the present invention, when a transistor having a gate insulating film made of a high dielectric material or a ferroelectric material is manufactured, the number of steps is slightly increased, but the self-alignment method is performed without causing any damage to the gate insulating film. To be able to apply.
[0029]
[Means for Solving the Problems]
The present invention forms a source region and a drain region by applying a self-alignment method in a state where a gate insulating film dummy is formed, and after completing the activation heat treatment of implanted ions, the gate insulating film dummy Is basically replaced with a gate insulating film made of a high dielectric material or a ferroelectric material.
[0030]
The gate insulating film dummy used in the present invention is a material that can withstand high temperatures because only the gate insulating film dummy needs to be selectively removed after ion activation heat treatment at high temperature. Then, it is necessary to have a property that can be easily and selectively removed thereafter.
[0031]
In addition, the gate insulating film dummy is not formed on the entire lower surface of the gate electrode, but only on a part of the gate insulating film dummy as long as the source region and the drain region can be formed by applying the self-alignment method. I must.
[0032]
The reason for adopting such a configuration is that if the gate insulating film dummy is selectively removed in a state where it is formed on the entire lower surface of the gate electrode, the gate electrode thereon is lifted off.
[0033]
The gate insulating film dummy does not need to be formed specifically for the purpose. For example, when forming a field insulating film by the LOCOS method, a nitride film which is an oxidation-resistant film covering the active element region is used. Alternatively, when a field insulating film is formed by the STI method, it is convenient to use a nitride film used for protecting the surface from CMP (Chemical Mechanical Polishing) and the like.
[0034]
FIG. 1 and FIG. 2 are side sectional views of a principal part showing a semiconductor device at a process point for explaining the principle of the present invention, which will be described below with reference to these drawings.
[0035]
Refer to FIG.
1- (1)
A gate insulating film dummy 2 that can be selectively removed is formed in the active element region of the Si semiconductor substrate 1.
[0036]
The gate insulating film dummy 2 is formed with a width substantially equal to the width of the source region and drain region to be formed later. Here, “width” means a width in a direction orthogonal to the channel length.
[0037]
Refer to FIG.
1- (2)
After the gate electrode 5 is formed on the gate insulating film dummy 2, ion implantation is performed to form a low impurity concentration region 6 to be a low impurity concentration source region and a low impurity concentration drain region of the LDD structure.
[0038]
Since the gate electrode 5 is formed so that its width extends beyond the width of the gate insulating film dummy 2, both ends thereof, that is, both ends in the direction perpendicular to the paper surface exceed the active element region, for example, field insulation. Located on the membrane.
[0039]
In this case, even if the gate insulating film dummy 2 is used, the low impurity concentration region 6 to be the source region and the drain region is formed by self-alignment with respect to the gate electrode 5, which is a conventional manufacturing process. No change at all.
[0040]
See Fig. 1 (C)
1- (3)
After the side wall 7 is formed on the side surface of the gate electrode 3, ion implantation is performed to form a high impurity concentration region 8 to be a high impurity concentration source region and a high impurity concentration drain region of the LDD structure.
[0041]
Refer to FIG.
2- (1)
A heat treatment for activating the implanted ions is performed to form a low impurity concentration source region 6S, a high impurity concentration source region 8S, a low impurity concentration drain region 6D, and a high impurity concentration drain region 8D. At this time, the gate insulating film dummy 2 is also exposed to a high temperature.
[0042]
2- (2)
The gate insulating film dummy 2 is selectively removed to form a cavity 2A under the gate electrode 5.
[0043]
Refer to FIG.
2- (3)
A gate insulating film 9 made of a high dielectric material or a ferroelectric material is formed and patterned as necessary.
[0044]
There is no difficulty in forming the gate insulating film 9 so as to fill the cavity 2A if the current film forming technique is appropriately selected. Incidentally, when the integration degree of the semiconductor device is low, that is, when the gate length is long, a case where a high dielectric material or a ferroelectric material cannot enter under the gate electrode 5 may occur, but the integration degree is improved. At the same time, since the gate length is shortened, it is easy for a high dielectric material or a ferroelectric material to enter the gate electrode 5 sufficiently. In practice, for a gate length of 0.8 [μm] or less. There is no problem.
[0045]
After the gate insulating film 9 is formed as described above, high-temperature heat treatment is not performed in the manufacturing process of the current semiconductor device, so that the high dielectric or ferroelectric does not deteriorate.
[0046]
By the way, there are several options for performing the step of removing the gate insulating film dummy that can be selectively removed, and the embodiment differs depending on how the step is performed. Can point in time.
[0047]
{Circle around (1)} After removing the gate electrode material film to form a gate electrode, it is removed.
{Circle around (2)} A side wall is formed on the side surface of the gate electrode and then removed.
(3) The gate insulating film dummy is also removed when the side walls are removed (see Embodiment 6).
{Circle around (4)} Remove from the back side of the element formation substrate through openings formed in the element formation substrate and the field insulating film (see Embodiments 7 and 8).
[0048]
In addition, the heat treatment for activating the impurities implanted to form the source region and the drain region is between the time of ion implantation and before the formation of the high dielectric film or the ferroelectric film. At any stage, there are two types: (1) performing an impurity activation heat treatment before removing the gate insulating film dummy, and (2) performing an impurity activation heat treatment after removing the gate insulating film dummy. Based on this, there are the following five options.
[0049]
(1) “Impurity ion implantation” → “impurity activation heat treatment” → “gate insulation film dummy removal” → “high dielectric or ferroelectric gate insulation film formation”.
(2) "Impurity ion implantation"-> "Gate insulation film dummy removal"-> "Impurity activation heat treatment"-> "High dielectric or ferroelectric gate insulation film formation".
(3) “Dummy removal of gate insulating film” → “impurity ion implantation” → “impurity activation heat treatment” → “impurity activation heat treatment” → “high dielectric or ferroelectric gate insulation film formation”.
(4) "Partial removal of gate insulating film dummy"-> "Impurity ion implantation"-> "Impurity heat treatment"-> "Remove all gate insulating film dummy"-> "High dielectric or ferroelectric gate insulation Film formation ".
(5) "Partial removal of gate insulating film dummy"-> "Impurity ion implantation"-> "Removal of all gate insulating film dummy"-> "Impurity activation heat treatment"-> "High dielectric or ferroelectric gate insulation Film formation ".
[0050]
  From the foregoing, in the method of manufacturing a semiconductor device according to the present invention,
(1)
  A gate electrode (for example, gate electrode 25) is formed having both ends on a field insulating film (for example, field insulating film 24) and other portions on a gate insulating film dummy (for example, Si nitride film 23) that can be selectively removed. And thenSaidGate electrode andSaidImpurities using field insulating film as maskTheIon implantationDoProcessAnd noteEnteredSaidA source region (for example, a low impurity concentration source region 26S and a high impurity concentration source region 28S) and a drain region (for example, a low impurity concentration drain region 26D and a high impurity concentration drain region 28D) are formed by performing an impurity activation heat treatment.ProcessWhen,SaidRemove the gate insulating film dummySaidDirectly on the gate electrodeUnderCreating a cavity (eg, cavity 23A) and then at leastSaidA step of forming a gate insulating film (for example, gate insulating film 29) made of a high dielectric material or a ferroelectric material filling the cavity, and then a source electrode (for example, source electrode 31S) and a drain electrodevery(Eg drain electrode 31D)TheOr forming a process, or(2)
  A gate electrode (for example, gate electrode 25) is formed having both ends on a field insulating film (for example, field insulating film 24) and other portions on a gate insulating film dummy (for example, Si nitride film 23) that can be selectively removed. A step of removing impurities other than the portion in contact with the gate electrode of the gate insulating film dummy, and then ion-implanting impurities using the gate electrode and the field insulating film as a mask, and an activation heat treatment of the impurities Forming a source region (for example, a low impurity concentration source region 26S and a high impurity concentration source region 28S) and a drain region (for example, a low impurity concentration drain region 26D and a high impurity concentration drain region 28D), and forming the gate insulating film dummy Removing and generating a cavity (for example, cavity 23A) immediately below the gate electrode; Next, a step of forming a gate insulating film (for example, the gate insulating film 29) made of a high dielectric material or a ferroelectric material filling at least the cavity, and then a source electrode (for example, the source electrode 31S) and a drain electrode (for example, the drain electrode 31D). Or the step of forming
(3)
  Forming a gate electrode having both ends on the field insulating film and other portions on the gate insulating film dummy that can be selectively removed; and then removing all the gate insulating film dummy and immediately below the gate electrode Forming a cavity, and then implanting impurities with the gate electrode and the field insulating film as a mask, and then performing activation heat treatment of the implanted impurities to form a source region and a drain region, Then, the method includes a step of forming a gate insulating film made of a high dielectric material or a ferroelectric material that fills at least the cavity, and then a step of forming a source electrode and a drain electrode. Or
(4)
  In any one of the above (1) to (3), a step of forming a side wall on the side surface of the gate electrode is included, or
(5)
  In the above (4), the method includes the step of performing ion implantation for the source region and the drain region at least once before and after the side wall formation. Or
(6)
  Both ends are field insulating films(For example, field insulating film 44)Gate dielectric dummy that is on top and can be selectively removed from other parts(For example, Si nitride film 43)Upper gate electrode(Eg, gate electrode 46)Forming a side wall on the side surface of the gate electrode(Eg side wall 47)And forming an insulating film by exposing a top surface of the side wall.(Eg, insulating film 49)And forming the cavity by removing the side wall and gate insulating film dummy(For example, cavities 43A and 47A)Generating A step of implanting impurity ions using the gate electrode and the field insulating film as a mask, and an activation heat treatment of the implanted impurity are performed to form a source region (for example, source region 48S) and a drain region (for example, drain region 48D). Or a step of forming a gate insulating film (for example, the high dielectric film 50) made of a high dielectric material or a ferroelectric material filling at least the cavity, or
(7)
  A gate electrode (for example, gate electrode 65) having both ends on a field insulating film (for example, field insulating film 64) and another portion on a gate insulating film dummy (for example, Si nitride film 63) that can be selectively removed is formed. Next, an impurity is ion-implanted, and then the impurity activation heat treatment is performed to perform a source region (for example, a low impurity concentration source region 66S and a high impurity concentration source region 68S) and a drain region (for example, a low impurity concentration drain region 66D). And a step of forming a high impurity concentration drain region 68D), a step of flattening by forming an insulating film (for example, an insulating film 69) thick enough to fill the gate electrode sufficiently on the surface side, After the planarized insulating film surface and the supporting substrate (for example, the supporting-side Si semiconductor substrate 70) are bonded together, the source regions are aligned. Polishing the side where the drain region is present and thinning the field insulating film until the field insulating film is exposed, and then opening from the thinned side to the gate insulating film dummy (for example, opening 71A, opening 64A, opening 61A and the like, then removing the gate insulating film dummy through the opening to form a cavity (for example, cavity 63A) immediately below the gate electrode, and then at least filling the cavity A step of forming a gate insulating film (for example, a high dielectric film 72) made of a dielectric or a ferroelectric, and a step of forming a source electrode (for example, a source electrode 73S) and a drain electrode (for example, a drain electrode 73D) thereafter. It is characterized by comprising.
[0060]
By adopting the above means, the high temperature of the heat treatment is not applied to the gate insulating film while maintaining the advantage of the self-alignment method that automatically aligns the source region and the drain region with respect to the gate electrode. Therefore, when a high dielectric material or a ferroelectric material is used as the material, there is no possibility that they will deteriorate.
[0061]
Therefore, even when the transistor size is reduced in accordance with the reduction rule of the transistor size, only the gate insulating film can be formed thick enough to obtain a required breakdown voltage while maintaining a high dielectric constant. Therefore, it can contribute to miniaturization of transistors and high integration of semiconductor devices.
[0062]
In addition, since a transistor having a ferroelectric gate insulating film has hysteresis characteristics, a FeRAM (ferroelectric random access memory) including a one-transistor type memory element can be manufactured by applying a self-alignment method.
[0063]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 3 to 6 are a fragmentary cut-away side view and a fragmentary cut-away explanatory view (FIG. 4) showing a semiconductor device in a process essential point for explaining the first embodiment of the present invention. Hereinafter, description will be given with reference to these drawings.
[0064]
Refer to FIG.
3- (1)
By applying the thermal oxidation method, an oxidized Si film 22 having a thickness of about 10 nm is formed on the Si semiconductor substrate 21.
[0065]
The Si oxide film 22 is called a so-called pad oxide film, and plays a role in preventing the Si nitride film from coming into direct contact with the surface of the Si semiconductor substrate 21 to adversely affect it.
[0066]
3- (2)
By applying the CVD method, a Si nitride film 23 having a thickness of about 100 nm is formed on the pad oxide film 22 to act as an oxidation resistant film. The thickness of the Si nitride film 23 can be selected in the range of 30 [nm] to 100 [nm].
[0067]
Refer to FIG.
3- (3)
Resist process and etching gas in lithography technology CF_Four+ CHF_ThreeBy applying a dry etching method of + Ar, patterning of the Si nitride film 23 is performed, and other portions are removed while leaving a portion covering the active element region.
[0068]
Refer to FIG.
3- (4)
By applying the thermal oxidation method, a field insulating film 24 having a thickness of about 100 nm to 600 nm is formed on the Si semiconductor substrate 21 other than the active element region covered with the Si nitride film 23. .
[0069]
Thereafter, the Si nitride film 23 is usually removed, but in this embodiment, this is left as a “selectable and removable gate insulating film dummy”.
[0070]
See FIG. 4 (A) and FIG. 4 (B).
4- (1)
By applying the CVD method, an impurity-containing polycrystalline Si film having a thickness of 150 [nm] is formed.
[0071]
For this impurity-containing polycrystalline Si film, other gate electrode materials, for example, a composite film in which the lower layer is an impurity-containing polycrystalline Si film and the upper layer is a tungsten silicide film may be used.
[0072]
4- (2)
Resist process in lithography technology and etching gas is HBr + O₂The gate electrode 25 is formed by patterning the impurity-containing polycrystalline Si film by applying the dry etching method.
[0073]
Refer to FIG.
4- (3)
By applying the ion implantation method, when the thickness of the Si nitride film is 50 [nm], the ion acceleration energy is 70 [keV] and the dose is 1 × 10.¹⁴〔cm^-2Then, P ions are implanted using the gate electrode 25 and the field insulating film 24 having a thickness of 300 nm as a mask to form a low impurity concentration region 26 to be a low impurity concentration source region and a low impurity concentration drain region of the LDD structure. Form.
[0074]
Refer to FIG.
5- (1)
By applying the CVD method, SiO having a thickness of about 30 nm to 300 nm.₂A film is formed on the entire surface. This film thickness depends on the gate width and is usually selected to be about 1/4 of the gate width.
[0075]
5- (2)
Etching gas CF_Four+ Ar + CHF_ThreeBy applying the dry etching method₂Sidewalls 27 are formed by anisotropic etching of the film.
[0076]
Refer to FIG.
5- (3)
Since the Si nitride film 23 has finished its role as a gate insulating film dummy, it is entirely removed in the hot phosphoric acid to remove the entire portion including the portion directly under the gate electrode 25 to form a cavity 23A. Let
[0077]
It is desirable to leave the pad oxide film 22 underlying the Si nitride film 23, but it is preferable to form a thin oxide film or nitride film again by removing all of the pad oxide film 22 and then oxidizing or nitriding again.
[0078]
This is because a high dielectric film or a ferroelectric film formed later directly contacts the surface of the Si semiconductor substrate 21 to increase the interface state, or the leakage current of the high dielectric film or the ferroelectric film increases. This is to prevent this.
[0079]
As a result, a cavity is formed immediately below the gate electrode 25, and both ends of the gate electrode 25 are on the field insulating film 24. Therefore, the gate electrode 25 forms a bridge hung on the cavity.
[0080]
Refer to FIG.
5- (4)
By applying the ion implantation method, the ion acceleration energy is 20 [keV], and the dose is 5 × 10.¹⁵〔cm^-2Then, P ions are implanted using the side wall 27, the gate electrode 25, and the field insulating film 24 as a mask to form a high impurity concentration region 28 to be a high impurity concentration source region and a high impurity concentration drain region of the LDD structure. .
[0081]
Refer to FIG.
6- (1)
A heat treatment at a temperature of 1000 ° C. and a time of 10 seconds is performed to activate the ion-implanted impurity P, and a low impurity concentration source region 26S, a high impurity concentration source region 28S, and a low impurity concentration drain region. 26D and high impurity concentration drain region 28D are formed.
[0082]
Refer to FIG.
6- (2)
By applying the CVD method, Ta is a high dielectric material.₂O_FiveA gate insulating film 29 made of is formed. As another technique for forming a high dielectric film, a spin coating method can be applied, and the high dielectric material is Ta.₂O_FiveBesides, for example, BST ((Ba, Sr) TiO_Three) May be used.
[0083]
The gate insulating film 29 is formed on the entire surface and, of course, is buried in the cavity immediately below the gate electrode 25, and the thickness thereof is about 5 nm which is the thickness of the Si nitride film 23 which is the gate insulating film dummy. After the formation and filling is completed, it is not necessary to form a film thicker than that.
[0084]
6- (3)
In order to reduce the leakage current, a heat treatment is performed at a temperature of 700 ° C. for a time of 3 minutes in an oxygen atmosphere, and the gate insulating film 29 which is a high dielectric material is crystallized to some extent.
[0085]
This heat treatment is sufficiently lower than the temperature at the time of the heat treatment for activating the ion-implanted impurities for forming the source regions 26S and 28S and the drain regions 26D and 28D, and the high dielectric is destroyed. Thus, there is no fear that the leakage current increases, but rather, the crystallization of the gate insulating film 29 is promoted, which is effective in reducing the leakage current.
[0086]
Refer to FIG.
6- (4)
SiO having a thickness of 200 nm by applying the CVD method₂An interlayer insulating film 30 made of is formed.
[0087]
6- (5)
Resist process and etching gas in lithography technology CF_Four+ Ar + CHF_ThreeBy applying the dry etching method, the interlayer insulating film 30 is etched to form an opening.
[0088]
6- (6)
After forming the Al film by applying the sputtering method, the resist process and the etching gas in the lithography technology are changed to Cl + BCl._ThreeThe Al film is patterned by applying the dry etching method as described above to form the source electrode 31S, the drain electrode 31D, and other wirings.
[0089]
In the first embodiment described above, the LOCOS method is applied to form the field insulating film 24 for element isolation. Needless to say, this may be replaced with the STI method. Next, a manufacturing process to which the STI method is applied will be described as a second embodiment.
[0090]
FIG. 7 is a sectional side view showing a principal part of a semiconductor device at a process point for explaining the second embodiment of the present invention. The same symbols as those used in FIGS. The same part or the same meaning will be described below and will be described with reference to FIG. 7 until the formation and patterning of the Si nitride film 23 acting as an oxidation resistant film on the Si semiconductor substrate 21. Since the steps are the same as those in the first embodiment, they will be omitted, and the following steps will be described.
[0091]
Refer to FIG.
7- (1)
After patterning the Si nitride film 23, the etching gas is subsequently changed to CF._Four+ Ar + CH_Three(SiO₂For use) and HBr + O₂By applying a dry etching method (for Si), the pad oxide film 22 and the Si semiconductor substrate 21 are etched to form a recess in a field insulating film formation scheduled portion.
[0092]
In this case, the etching depth of the Si semiconductor substrate 21 is, for example, 500 [nm].
[0093]
Refer to FIG.
7- (2)
By applying the thermal oxidation method, the exposed surface of the Si semiconductor substrate 21 is oxidized to form an oxidized Si film 22A having a thickness of about 10 nm.
[0094]
7- (3)
By applying the high-density plasma CVD method, the thickness is 1000 nm.₂A film is formed.
[0095]
Refer to FIG.
7- (4)
Applying the CMP method, and using the Si nitride film 23 as a polishing stopper, the SiO formed in step 7- (3)₂The film is polished, and only in the recess of the Si semiconductor substrate 21 is SiO.₂The film is left as a field insulating film 24A.
[0096]
In this case as well, the Si nitride film 23 is not removed, but remains as a “selectable and removable gate insulating film dummy”.
[0097]
Thereafter, the semiconductor device is completed through steps similar to those of the first embodiment.
[0098]
In the first and second embodiments, a ferroelectric material such as lead zirconate titanate (PbTiO 2) is used instead of the high dielectric gate insulating film._Three-PbZrO_Three: PZT), Y1 (trade name: US Symmetrics), etc. can be used, and this will be described as Embodiment 3.
[0099]
Ferroelectrics can be formed by applying CVD and spin coating methods, as with high dielectrics. When a voltage higher than a predetermined voltage is applied between the front and back of a ferroelectric film, it is generated internally. The polarization state has a so-called hysteresis characteristic that is maintained even after the voltage application is stopped.
[0100]
Therefore, when the gate insulating film of the transistor is made of a ferroelectric material, it is not different from a normal transistor in that it is turned on by applying a gate voltage higher than the threshold value. It will not turn off even if it is lowered.
[0101]
Therefore, the transistor has a memory holding capability and can be used as a memory. In order to turn it off, it is necessary to apply a reverse bias voltage of a predetermined value or more to the gate electrode.
[0102]
In the first to third embodiments, the LDD structure is adopted as the structure of the source region and the drain region. However, the low impurity concentration source region and the low impurity concentration drain region, or the high impurity concentration source region and the high impurity concentration drain region. Either of the above may be omitted. If the low impurity concentration source region and the low impurity concentration drain region are omitted, the side wall is diffused by diffusing impurities in the high impurity concentration source region and the high impurity concentration drain region. It is necessary to widen to reach just below the interface between the gate electrode and the gate electrode. This modification is referred to as a fourth embodiment.
[0103]
FIG. 8 is a cutaway side view of a principal part showing a semiconductor device at a process point for explaining the fifth embodiment of the present invention. The same symbols as those used in FIGS. The same parts are assumed to have the same meaning or have the same meaning, and will be described below with reference to FIG. 8. However, the steps until the gate electrode 25 is formed on the Si semiconductor substrate 21 are the same as those in the first embodiment, and thus omitted. The following process will be described.
[0104]
Refer to FIG.
8- (1)
By immersing the whole in hot phosphoric acid, the entire Si nitride film 23 (see FIGS. 3 to 5) including the portion immediately below the gate electrode 25 is removed.
[0105]
After the above steps, a cavity 23A is generated immediately below the gate electrode 25, and both ends of the gate electrode 25 are on the field insulating film 24. Therefore, the gate electrode 25 forms a bridge over the cavity 23A. Yes.
[0106]
Refer to FIG.
8- (2)
By applying the ion implantation method, the ion acceleration energy is 20 [keV], and the dose is 3 × 10.¹³〔cm^-2Then, P ions are implanted using the gate electrode 25 and the field insulating film 24 as a mask to form a low impurity concentration region 26 to be a low impurity concentration source region and a low impurity concentration drain region.
[0107]
Refer to FIG.
8- (3)
A heat treatment is performed at a temperature of 1000 ° C. for a time of 10 seconds to activate the ion-implanted P, thereby forming a low impurity concentration source region 26S and a low impurity concentration drain region 26D.
[0108]
8- (4)
A gate insulating film 29 made of a high dielectric material or a ferroelectric material is formed by applying the CVD method. As another technique for forming the gate insulating film 29A, a spin coating method can be applied.
[0109]
8- (5)
In order to reduce the leakage current, a heat treatment is performed in an oxygen atmosphere at a temperature of 700 [° C.] and a time of 3 [min] to crystallize the gate insulating film 29 which is a high dielectric or a ferroelectric.
[0110]
8- (6)
Thereafter, in the same manner as in the first embodiment, the interlayer insulating film is formed, the openings are formed, the electrodes and the wiring are formed, and the like is completed.
[0111]
In the semiconductor device obtained according to the fifth embodiment, the high impurity concentration source region and the high impurity concentration drain region are not provided. A memory or the like that does not require much high speed operation is useful in that it is easy to manufacture and has no performance problems.
[0112]
FIGS. 9 to 11 are cutaway side views showing the principal part of the semiconductor device at the main points of the process for explaining the sixth embodiment of the present invention. Since the process until the field insulating film 44 is formed on the semiconductor substrate 41 is the same as that of the first embodiment, it will be briefly described.
[0113]
Refer to FIG.
9- (1)
A Si semiconductor substrate 41 is provided with a Si oxide film 42 as a pad oxide film, a Si nitride film 43 as a gate insulating film dummy that can be selectively removed as an oxidation resistant film, and SiO₂A field insulating film 44 made of is formed.
[0114]
9- (2)
By applying the CVD method, an impurity-containing polycrystalline Si film having a thickness of 150 [nm] is formed.
[0115]
9- (3)
SiO having a thickness of 50 [nm] to 100 [nm] by applying the CVD method₂An insulating film made of is formed. This insulating film may be omitted.
[0116]
9- (4)
Resist process and etching gas in lithography technology CF_Four+ Ar + CH_Three(SiO₂For use) and HBr + O₂By applying the dry etching method (for Si), SiO₂The insulating film and the impurity-containing polycrystalline Si film are anisotropically etched to form the insulating film cap 45 and the gate electrode 46.
[0117]
Refer to FIG.
9- (5)
Etching gas CF_Four+ Ar + CH_ThreeThe exposed Si nitride film 43 is anisotropically etched to have the same pattern as the insulating film cap 45 or the gate electrode 46 by applying the dry etching method. In this etching, SiO such as the insulating film cap 45 and the field insulating film 44 is used.₂Will damage
It is preferable to select etching conditions that will not be affected.
[0118]
If an LDD structure is used, a low impurity concentration impurity source region and a low impurity concentration impurity drain region must be formed at this stage.
[0119]
Refer to FIG.
9- (6)
By applying the CVD method, a Si nitride film having a thickness of 100 nm is formed on the entire surface.
[0120]
9- (7)
Etching gas CF_Four+ Ar + CH_ThreeIs applied to the side surfaces of the insulating film cap 45, the gate electrode 46, and the Si nitride film 43 by anisotropic etching of the Si nitride film formed in Step 9- (6). -Wall 47 is formed.
[0121]
The Si nitride film 43 is anisotropically etched in Step 9- (5) to have the same pattern as the insulating film cap 45 and the like, but may be anisotropically etched after the side wall 47 is formed. In such a case, the bottom of the side wall 47 is on the Si nitride film 43. In any case, it suffices if the Si nitride film 43 and the side wall 47 made of Si nitride are connected. Further, the side wall 47 and the gate insulating film dummy which is the Si nitride film 43 are not necessarily made of the same material, and different materials may be used unless it is necessary to increase the number of steps for removing the etching. it can.
[0122]
9- (8)
By applying the ion implantation method, the ion acceleration energy is 20 [keV], and the dose is 5 × 10.¹⁵〔cm^-2The high impurity concentration region 48 to be the high impurity concentration source region and the high impurity concentration drain region is formed by implanting P ions using the side wall 47, the gate electrode 46, the insulating film cap 45, and the field insulating film 44 as a mask. Form.
[0123]
After that, the side wall 47 and the Si nitride film 43 may be selectively removed to form a structure as shown in FIG. 8A. In that case, the source region and the drain region with high impurity concentration are used. As shown in FIG. 8B, if a low impurity concentration source region and drain region of the LDD structure are formed, a normal LDD structure can be obtained. Can do.
[0124]
Refer to FIG.
10- (1)
The source region 48S and the drain region 48D are formed by performing the activation heat treatment of the ion-implanted P at a temperature of 1000 ° C. and a time of 10 seconds. This heat treatment is preferably performed so that the channel facing side of the source region 48S and the drain region 48D is diffused so as to reach directly below the interface between the side wall 47 and the gate electrode 46.
[0125]
10- (2)
By applying the CVD method, SiO with a thickness of 200 [nm]₂An insulating film 49 made of is formed.
[0126]
10- (3)
By applying the CMP method, the insulating film 49 is polished and stopped when the top surface of the side wall 47, and hence the top surface of the insulating film cap 45, is exposed. Note that an etching method may be applied to reduce the thickness of the insulating film 49.
[0127]
Refer to FIG.
10- (4)
Immersion in hot phosphoric acid removes the side walls 47 made of Si nitride, and also removes the Si nitride film 43 that was a gate insulating film dummy under the gate electrode 46 to generate cavities 43A and 47A. Let
[0128]
Refer to FIG.
10- (5)
By applying the CVD method, BST or Ta fills the cavity 47A generated by removing the side wall 47 and the cavity 43A generated by removing the Si nitride film 43.₂O_FiveA high dielectric film 50 made of is formed. The high dielectric film 50 may be replaced with a ferroelectric film.
[0129]
It goes without saying that the portion of the high dielectric film 50 that is directly under the gate electrode 46 functions as a gate insulating film.
[0130]
See FIG.
11- (1)
In order to reduce the leakage current, heat treatment is performed in an oxygen atmosphere at a temperature of 700 ° C. for a time of 3 minutes, and the high dielectric film 50, part of which forms a gate insulating film, is crystallized.
[0131]
11- (2)
Thereafter, the electrode contact openings are formed in the insulating film 49 and the high dielectric film 50, and the electrodes and wirings 51 are formed.
[0132]
In each of the embodiments described above, the semiconductor device using the Si semiconductor substrate has been described. However, an SOI structure semiconductor device can be formed by implementing the present invention.
[0133]
There are various types of SOI structures. For example, after a device is formed to some extent on an element side substrate, a method is known in which an entire structure is attached to a support side substrate to form an SOI structure. If necessary, refer to “Patent No. 9603828”), and this means can be used effectively in the present invention.
[0134]
FIG. 12 to FIG. 14 are main part cutting explanatory views showing the semiconductor device in the main points of the process for explaining the seventh embodiment in the present invention. A main part cutting side surface, (B) is a main part cutting plane.
[0135]
Hereinafter, a description will be given with reference to the drawings. Since the steps until the high impurity concentration source region 68S and the high impurity concentration drain region 68D are formed in the element formation side Si semiconductor substrate 61 are the same as those in the first embodiment, the description will be simplified. Explained.
[0136]
See FIG.
12- (1)
On the element forming side Si semiconductor substrate 61, a Si oxide film 62 as a pad oxide film, a Si nitride film 63 as a gate insulating film dummy that can be selectively removed as an oxidation resistant film, a field insulating film 64, an impurity-containing polycrystalline Si gate electrode 65, a low impurity concentration region which becomes a low impurity concentration source region and a low impurity concentration drain region of an LDD structure, SiO₂A high impurity concentration region that becomes a high impurity concentration source region and a high impurity concentration drain region of an LDD structure is formed.
[0137]
12- (2)
The heat treatment for activating the ion-implanted impurities is performed at a temperature of 1000 ° C. and a time of 10 seconds, and the low impurity concentration source region 66S, the low impurity concentration drain region 66D, the high impurity concentration region 68S, and the high impurity concentration. A region 68D is generated.
[0138]
12- (3)
By applying the CVD method, SiO whose thickness is 1 [μm] on the entire surface₂An insulating film 69 made of is formed.
[0139]
12- (4)
By applying the CMP method, the insulating film 69 is polished to flatten the surface and the thickness of the insulating film 69 is set to 0.5 [μm].
[0140]
12- (5)
By applying means such as a thermocompression bonding method, the support side Si semiconductor substrate 70 is attached to the surface of the insulating film 69.
[0141]
12- (6)
By applying the CMP method, the back surface of the element forming side Si semiconductor substrate 61 is polished, and the thinning is continued until the field insulating film 64 is exposed, whereby the Si island surrounded by the field insulating film 64 is obtained. Is generated.
[0142]
See FIG.
13- (1)
By applying the CVD method, the SiO 2 having a thickness of 200 nm is formed on the exposed surface of the element forming side Si semiconductor substrate 61.₂An interlayer insulating film 71 made of is formed.
[0143]
13- (2)
Resist process and etching gas in lithography technology CF_Four+ Ar + CH_ThreeThe opening 71A is formed in the interlayer insulating film 71 by applying the dry etching method.
[0144]
13- (3)
Etching gas as HBr + O₂By applying the dry etching method, the element formation side Si semiconductor substrate 61 is etched through the opening 71A to form the opening 61A.
[0145]
13- (4)
The silicon oxide film 62, which is a pad oxide film, is removed by dipping in an etching solution made of diluted hydrofluoric acid.
[0146]
13- (5)
Immersion in hot phosphoric acid removes all of the Si nitride film 63, which is a gate insulating film dummy made of Si nitride, to generate a cavity 63A.
[0147]
See FIG.
14- (1)
By applying the CVD method, Ta can be sufficiently passed to the opening 61A and the cavity 63A.₂O_FiveAlternatively, a high dielectric film 72 made of BST is formed. The high dielectric film 72 may be replaced with a ferroelectric film.
[0148]
If necessary, annealing for crystallizing the high dielectric film 72 is performed. This crystallization annealing step is performed at a temperature of 700 [° C.] and a time of about 3 [minutes].
[0149]
It goes without saying that a portion of the high dielectric film 72 that is directly under the gate electrode 65 functions as a gate insulating film.
[0150]
14- (2)
By applying a resist process and a dry etching method in the lithography technique, the high dielectric film 72 and the interlayer insulating film 71 are etched to form the source electrode contact opening and the drain electrode contact opening. To do.
[0151]
The etching gas used for high dielectric dry etching is selected according to the type of high dielectric, and SiO₂CF as an etching gas_Four+ Ar + CH_ThreeYou can choose.
[0152]
14- (3)
By applying a vacuum deposition method or a sputtering method, a resist process in a lithography technique, and a dry etching method, a source electrode 73S and a drain electrode 73D made of a laminate of an Al film and a barrier film made of TiN or WN are formed. Form.
[0153]
The semiconductor device fabricated according to the seventh embodiment has the advantages of the SOI structure in addition to the advantages of the present invention, and immediately reduces the parasitic capacitance between 00000, and thus is effective for high speed operation and low power consumption. It goes without saying that there is.
[0154]
In any of the above-described embodiments, as a gate insulating film dummy that can be selectively removed, a Si nitride film that is an oxidation resistant film when a field insulating film is formed by applying the LOCOS method is used. Yes.
[0155]
However, various materials other than the Si nitride film can be used for the gate insulating film dummy that can be selectively removed, and it is preferable to use materials other than Si nitride in relation to the material used for the semiconductor device. In some cases.
[0156]
When a dedicated gate insulating film dummy that can be selectively removed is provided separately, the structure of the semiconductor device itself needs to be slightly modified in order to suppress an increase in the number of processes as much as possible.
[0157]
FIGS. 15 to 17 are sectional views for explaining a main part of the semiconductor device at the process steps for explaining the eighth embodiment of the present invention. In any of the drawings, FIG. A main part cutting side surface, (B) is a main part cutting plane.
[0158]
In the following, a description will be given with reference to the drawings. However, the steps until the field insulating film 64 is formed on the element formation side Si semiconductor substrate 61 are the same as those in the first embodiment, and thus are described briefly.
[0159]
See FIG.
15- (1)
After the field insulating film 64 is formed by the LOCOS method, after removing the Si oxide film as the pad oxide film and the Si nitride film as the oxidation resistant film, for example, alumina (Al₂O_ThreeThe gate insulating film dummy 81 that can be selectively removed is formed. The material of the gate insulating film dummy 81 is Al.₂O_ThreeBesides, TiN or WN can also be used.
[0160]
15- (2)
Resist process and etching gas in lithography technology CF_Four+ Ar + CH_ThreeBy applying the dry etching method, the gate insulating film dummy 81 is patterned to remove the remaining part of the area covering the active element region and the part of the field insulating film 64.
[0161]
15- (3)
By applying the CVD method, a polycrystalline Si film having a thickness of 150 nm is formed.
[0162]
15- (4)
Resist process in lithography technology and etching gas is HBr + O₂The gate electrode 65 is formed by patterning the polycrystalline Si film by applying the dry etching method.
[0163]
15- (5)
By applying the ion implantation method, the ion acceleration energy is 70 [keV] and the dose is 1 × 10.¹⁴〔cm^-2Then, P ions are implanted using the gate electrode 65 and the field insulating film 64 as a mask to form a low impurity concentration region which becomes a low impurity concentration source region and a low impurity concentration drain region of the LDD structure.
[0164]
15- (6)
By applying the CVD method, SiO having a thickness of about 100 [nm]₂A film is formed on the entire surface.
[0165]
15- (7)
Etching gas CF_Four+ Ar + CH_ThreeThe SiO formed in step 15- (6) by applying the dry etching method₂Sidewalls 67 are formed by anisotropic etching of the film.
[0166]
15- (8)
By applying the ion implantation method, the ion acceleration energy is 70 [keV], and the dose is 5 × 10.¹⁵〔cm^-2Then, P ions are implanted using the side wall 67, the gate electrode 65, and the field insulating film 64 as a mask to form a high impurity concentration region to be a high impurity concentration source region and a high impurity concentration drain region of the LDD structure.
[0167]
15- (9)
The temperature is set to 1000 [° C.] and the time is set to 10 [seconds]. An activation heat treatment is performed on the impurity P ion-implanted earlier, so that the low impurity concentration source region 66S, the low impurity concentration drain region 66D, and the high impurity concentration source region. 68S and a high impurity concentration drain region 68D are formed.
[0168]
15- (10)
By applying the CVD method, SiO whose thickness is 1 [μm] on the entire surface₂An insulating film 69 made of is formed.
[0169]
15- (11)
By applying the CMP method, the insulating film 69 is polished to flatten the surface and the thickness of the insulating film 69 is set to 0.5 [μm].
[0170]
15- (12)
The supporting side Si semiconductor substrate 70 is attached to the surface of the insulating film 69 by applying a thermocompression bonding method or the like.
[0171]
15- (13)
By applying the CMP method, the back surface of the element forming side Si semiconductor substrate 61 is polished, and the thinning is continued until the field insulating film 64 is exposed, whereby the Si island surrounded by the field insulating film 64 is obtained. Is generated.
[0172]
See FIG.
16- (1)
By applying the CVD method, the SiO 2 having a thickness of 200 nm is formed on the exposed surface of the element forming side Si semiconductor substrate 61.₂An interlayer insulating film 71 made of is formed.
[0173]
16- (2)
Resist process and etching gas in lithography technology CF_Four+ Ar + CH_ThreeThe opening 71A is formed in the interlayer insulating film 71 by applying the dry etching method.
[0174]
16- (3)
Etching gas CF_Four+ Ar + CH_ThreeThe field insulating film 64 is etched through the opening 71A to form the opening 64A.
[0175]
16- (4)
Immerse in hot sulfuric acid solution and add Al₂O_ThreeAll of the gate insulating film dummy 81 made of the above is removed to generate a cavity 81A.
[0176]
See FIG.
17- (1)
By applying the CVD method, Ta can be sufficiently passed to the opening 64A and the cavity 81A.₂O_FiveAlternatively, a high dielectric film 72 made of BST is formed. The high dielectric film 72 may be replaced with a ferroelectric film.
[0177]
Annealing for crystallizing the high dielectric film 72 is performed as necessary. As an example of the conditions in this case, the temperature may be selected as 700 [° C.] and the time as 3 minutes.
[0178]
Of course, the portion of the high dielectric film 72 directly below the gate electrode 65 functions as a gate insulating film.
[0179]
17- (2)
By applying a resist process and a dry etching method in the lithography technique, the high dielectric film 72 and the interlayer insulating film 71 are etched to form the source electrode contact opening and the drain electrode contact opening. To do. When the dry etching method is performed, it is necessary to change the etching gas for the high dielectric depending on the type of the high dielectric.
[0180]
17- (3)
By applying a vacuum deposition method, a resist process in a lithography technique, or a dry etching method, a source electrode 73S and a drain electrode 73D made of a laminate of an Al film and a barrier film made of TiN or WN are formed.
[0181]
Similar to the seventh embodiment, the semiconductor device fabricated according to the eighth embodiment has the advantages of the SOI structure in addition to the advantages of the present invention.
[0182]
In the first to eighth embodiments described above, Si nitride is mainly used as the gate insulating film dummy that can be selectively removed.₂O_ThreeA coating such as (alumina), TiN, WN, or the like can be used.
[0183]
The present invention is not limited to the above-described embodiment, and various other modifications can be realized.
[0184]
For example, after performing activation heat treatment of the ion-implanted impurity to form the source region and the drain region, the gate insulating film dummy is removed to form a gate insulating film made of a high dielectric material or a ferroelectric material. Instead of the process, the gate insulating film dummy may be removed prior to the activation heat treatment of the ion-implanted impurity.
[0185]
Also, after removing the gate insulating film dummy other than the gate insulating film dummy that is in contact with the gate electrode, impurity ion implantation is performed to form the source region and the drain region, and then all the remaining gate insulating film dummy is removed. From the above, after the activation heat treatment of the ion-implanted impurities, a gate insulating film made of a high dielectric material or a ferroelectric material can be arbitrarily formed.
[0186]
Both of the above modifications have the common point that the gate insulating film dummy is removed before the activation heat treatment of the ion-implanted impurities. In this case, the gate insulating film dummy is high. Since heat resistance is not required, material selection becomes easy.
[0187]
Needless to say, the present invention is not limited to the application in the case of manufacturing the n-channel transistor described above, but can be applied to the manufacture of a p-channel transistor.
[0188]
In each of the above embodiments, as the gate insulating film dummy, the oxidation-resistant mask film or the CMP stop film used when the elements are separated by the LOCOS method or the STI method is used. After removal, a configuration may be adopted in which a film is formed and processed again and left directly under the gate electrode.
[0189]
【The invention's effect】
In the method of manufacturing a semiconductor device according to the present invention, a gate electrode having both ends on a field insulating film and another portion on a gate insulating film dummy that can be selectively removed is formed. Impurity ions are implanted using the insulating film as a mask, and the implanted impurities are subjected to an activation heat treatment to form a source region and a drain region. The activation heat treatment is performed by removing the gate insulating film dummy and directly under the gate electrode. Any of the stages before the formation of a high dielectric or ferroelectric gate insulating film that fills the generated cavity and where no heat is applied to the high dielectric or ferroelectric gate insulating film After that, the source electrode and the drain electrode are formed.
[0190]
By adopting the above-mentioned configuration, the high temperature of the heat treatment is not applied to the gate insulating film while maintaining the advantage of the self-alignment method that automatically aligns the source region and the drain region with respect to the gate electrode. Therefore, when a high dielectric material or a ferroelectric material is used as the material, there is no possibility that they will deteriorate.
[0191]
Therefore, even when the transistor size is reduced in accordance with the reduction rule of the transistor size, only the gate insulating film can be formed thick enough to obtain a required breakdown voltage while maintaining a high dielectric constant. Therefore, it can contribute to miniaturization of transistors and high integration of semiconductor devices.
[0192]
In addition, since a transistor having a ferroelectric gate insulating film has hysteresis characteristics, a FeRAM (ferroelectric random access memory) including a one-transistor type memory element can be manufactured by applying a self-alignment method.
[Brief description of the drawings]
FIG. 1 is a cut-away side view of a principal part showing a semiconductor device at a process point for explaining the principle of the present invention;
FIG. 2 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining the principle of the present invention.
FIG. 3 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining the first embodiment of the present invention;
FIG. 4 is a cutaway explanatory view of a main part showing a semiconductor device at a process key point for explaining the first embodiment in the present invention;
FIG. 5 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining the first embodiment in the present invention;
FIG. 6 is a cutaway side view showing a main part of the semiconductor device at the main points of the process for explaining the first embodiment of the present invention.
FIG. 7 is a cutaway side view showing a main part of a semiconductor device in a process key point for explaining a second embodiment in the present invention;
FIG. 8 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining a fifth embodiment of the present invention;
FIG. 9 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining a sixth embodiment of the present invention.
FIG. 10 is a cutaway side view showing a principal part of a semiconductor device at a process point for explaining a sixth embodiment of the present invention.
FIG. 11 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining a sixth embodiment of the present invention.
FIG. 12 is a cutaway explanatory view showing a main part of a semiconductor device at a process point for explaining a seventh embodiment of the present invention.
FIG. 13 is a fragmentary cutaway explanatory view showing a semiconductor device in a process essential point for explaining a seventh embodiment of the present invention.
FIG. 14 is a fragmentary cutaway explanatory view showing a semiconductor device at a process essential point for explaining a seventh embodiment of the present invention.
FIG. 15 is a fragmentary cutaway explanatory view showing a semiconductor device at a process essential point for explaining an eighth embodiment in the present invention;
FIG. 16 is a fragmentary cutaway explanatory view showing a semiconductor device in a process essential point for explaining an eighth embodiment of the present invention.
FIG. 17 is a fragmentary cutaway explanatory view showing a semiconductor device at a process essential point for explaining an eighth embodiment of the present invention.
FIG. 18 is a cutaway side view of a main part showing a semiconductor device in a process key point for explaining a conventional example.
FIG. 19 is a cutaway side view showing a main part of a semiconductor device at a process point for explaining a conventional example;
[Explanation of symbols]
21 Si semiconductor substrate
22 Oxide Si film
23 Si nitride film (gate insulating film dummy that can be selectively removed)
24 Field insulating film
25 Gate electrode
26S low impurity concentration source region
26D Low impurity concentration drain region
27 Side wall
28S high impurity concentration source region
28D drain region with high impurity concentration
29 Gate insulation film (high dielectric)
30 Interlayer insulation film
31S source electrode
31D Drain electrode

Claims (7)

Forming both gate electrodes on the field insulating film and forming a gate electrode on the gate insulating film dummy that can be selectively removed at other portions;
Then, a step of impurity ions are implanted using the gate electrode and the field insulating film as a mask,
Forming a source region and a drain region by performing heat treatment for activating Note input by said impurities,
A step of generating a cavity under direct said gate electrode by removing the gate insulating film a dummy,
Then, a step of forming a high dielectric or strongly gate insulating film made of a dielectric fills at least the cavity,
Then, a method of manufacturing a semiconductor device characterized by comprising contains a step of forming a source electrode and a drain electrodes. Forming both gate electrodes on the field insulating film and forming a gate electrode on the gate insulating film dummy that can be selectively removed at other portions;
Next, after removing portions other than the portion in contact with the gate electrode of the gate insulating film dummy, a step of ion-implanting impurities using the gate electrode and the field insulating film as a mask,
Performing a heat treatment for activating the impurities to form a source region and a drain region;
Removing the gate insulating film dummy to generate a cavity directly under the gate electrode;
Next, a step of forming a gate insulating film made of a high dielectric material or a ferroelectric material filling at least the cavity;
And forming a source electrode and a drain electrode . A method for manufacturing a semiconductor device, comprising: Forming both gate electrodes on the field insulating film and forming a gate electrode on the gate insulating film dummy that can be selectively removed at other portions;
Next, removing all of the gate insulating film dummy and generating a cavity immediately below the gate electrode, and then implanting impurities with the gate electrode and the field insulating film as a mask,
Next, a step of performing activation heat treatment of the implanted impurities to form a source region and a drain region;
Next, a step of forming a gate insulating film made of a high dielectric material or a ferroelectric material filling at least the cavity;
And forming a source electrode and a drain electrode . A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising a step of forming a side wall on a side surface of the gate electrode . The semiconductor according to claim 4, comprising the step of performing ion implantation for the source region and the drain region at least once before and after the side wall formation. Device manufacturing method. Forming both gate electrodes on the field insulating film and forming a gate electrode on the gate insulating film dummy that can be selectively removed at other portions;
Next, forming a side wall on the side surface of the gate electrode;
Exposing the top surface of the side wall to form an insulating film;
Removing the side wall and gate insulating film dummy to generate a cavity;
Implanting impurity ions using the gate electrode and the field insulating film as a mask;
Performing activation heat treatment of the implanted impurities to form a source region and a drain region;
Then, the high dielectric or strong manufacturing method of a semi-conductor device shall be the step of forming a gate insulating film made of a dielectric material, characterized in that <br/> made it contains fill at least the cavity. Forming both gate electrodes on the field insulating film and forming a gate electrode on the gate insulating film dummy that can be selectively removed at other portions;
Next, a process of forming a source region and a drain region by ion-implanting impurities and then activating heat treatment of the impurities;
Next, a step of flattening by forming an insulating film thick enough to fill the gate electrode on the surface side;
Next, after the surface of the planarized insulating film and the support substrate are bonded together, the side where the source region and the drain region are present is polished and thinned until the field insulating film is exposed;
Next, forming an opening reaching the gate insulating film dummy from the thinned side;
Next, removing the gate insulating film dummy through the opening to generate a cavity directly below the gate electrode;
Next, a step of forming a gate insulating film made of a high dielectric material or a ferroelectric material filling at least the cavity;
Then, a manufacturing method of a semi-conductor device you characterized by comprising contains <br/> and forming source and drain electrodes.

Images