JPH05235162A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce crosstalk, to decrease noise due to dark current and to improve the quality of image of a sensor by reducing the thickness of an insulating layer directly under a central part of a control electrode thinner than that of an insulating layer except the central part. CONSTITUTION:The thickness of a thin gate insulating layer 108 directly under a gate electrode of a P<+> type region 106 of a second semiconductor region directly under and end of a control electrode is set to 350 to 50Angstrom . The thickness of a gate insulating layer 107 except a part directly under the central part of the gate electrode is desirably set larger by 50Angstrom than that of the film 108. Thus, threshold values of a transistor constituting part is altered at parts directly under an intermediate part and the periphery of the electrode, and biased except a perfect reset period so as to form an inversion layer only under the central part of its control electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a control electrode which electrically connects adjacent element regions.

[0002]

2. Description of the Related Art In recent years, in order to set a semiconductor region of an adjacent element region to a predetermined potential, a gate electrode serving as a control electrode is provided between the element regions via an insulating layer to form a MOS transistor, and the gate electrode is used. A configuration in which the element regions are electrically connected and disconnected has been proposed, and in particular, such a configuration is preferably used in a solid-state imaging device that collectively resets arranged pixels.

FIG. 21 is a plan view of the photoelectric conversion portion of the solid-state image pickup device having the above-mentioned structure, FIG. 22 is a sectional view taken along the line AA ′ of FIG. 21, and FIG.
3 is a BB 'sectional view of FIG.

Each pixel is composed of a bipolar type sensor. Here, the bipolar type sensor has a configuration equivalent to that of a bipolar transistor, in which carriers generated by light irradiation are accumulated in the base region and a signal corresponding to the carrier is taken out from the emitter region.

21 to 23, 101 is an n-type substrate, 102 is an n-type epitaxial growth layer, 103 is a p-type base region, 104 is an n-type emitter region, and 105 is an emitter electrode. Carriers generated by light irradiation are accumulated in the p-type base region 103, and an amplified signal corresponding to the carrier amount is read out from the emitter electrode 105.

At both ends of the p-type base region 103 of each pixel, a high-concentration p-type semiconductor region 1 serving as a source / drain region is formed.
06 is provided and the adjacent high-concentration p-type semiconductor region 106 is provided.
A gate electrode 109 is provided on the n-type epitaxial layer 102 between them with an insulating layer 111 interposed therebetween, and serves as a PMOS transistor constituent portion (broken line region P in the drawing).
When the PMOS transistor structure portion P is turned on, the p-type base regions 103 of the respective pixels are commonly connected and can be collectively reset to a predetermined potential. On the other hand, P
When the MOS transistor constituent part P is turned off, the p-type base region 103 of each pixel is electrically isolated. During the charge accumulation period and the signal reading period of each pixel, the PMOS transistor constituent portion P is in the OFF state.

[0007]

However, the above solid-state imaging device has the following problems because the area under the gate electrode 109 of the PMOS transistor forming portion P is the neutral region during the charge accumulation period. (1) Carriers generated under the gate electrode can travel to either the left or right pixel and cause crosstalk. (2) Carriers leaking under the gate electrode can go to either the left or right pixel, which causes crosstalk. (3) The dark current generated under the gate electrode leaks into the pixel and causes noise.

[0008]

The present invention has been made in view of the above problems, and a control electrode is provided on a first semiconductor region of the first conductivity type via an insulating layer, and both ends of the control electrode are provided. A second conductivity type second in the first semiconductor region under the subordinate
A semiconductor device provided with a semiconductor region is characterized in that the thickness of the insulating layer directly below the central portion of the control electrode is smaller than the thickness of the insulating layer other than the central portion.

[0009]

According to the present invention, the thickness of the insulating layer is reduced only in the central portion directly below the control electrode of the transistor constituent portion for electrically connecting and disconnecting the second semiconductor regions, so that the insulating layer is thinned just below the central portion of the control electrode and directly below the peripheral portion. Change the threshold value of the transistor configuration part with and only under the central part of the control electrode except for a complete reset period (a period in which the transistor configuration parts are all turned on and the potential of the second semiconductor region is reset to a predetermined potential). By biasing the control electrode so that an inversion layer or a depletion layer is formed, carriers generated under the transistor structure portion or spilled under the transistor structure portion are collected in the inversion layer (or depletion layer) to form a pixel. The crosstalk between them is reduced. Further, the dark current immediately below the central portion of the control electrode is also reduced.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings. Although the solid-state imaging device is taken as an example here, the present invention is not limited to such an application.

1 to 3 are schematic configuration diagrams showing a first embodiment of a solid-state image pickup device according to the present invention. FIG. 1 is a plan view of a photoelectric conversion section, and FIG. 2 is a sectional view taken along line AA 'of FIG. Fig. 3 and Fig. 1
It is a BB 'sectional view of. The same members as those shown in FIGS. 21 to 23 are designated by the same reference numerals.

1 to 3, 101 is an n-type substrate,
102 is an n-type epitaxial growth layer to be the first semiconductor region, 103 is a p-type base region, 104 is an n-type emitter region, 105 is an emitter electrode, 106 is a source of a PMOS transistor constituent portion (broken line region P ′ in the figure), The p ⁺ -type region serving as the drain region (the P ⁺ -type region 106 and the p-type base region 103 serve as the second semiconductor region. The second semiconductor region immediately below the end of the control electrode is the P ⁺ -type region 106).
Indicates. ), 107 is a thick gate insulating layer other than directly under the central portion of the gate electrode, 108 is a thin gate insulating layer directly under the central portion of the gate electrode, and 109 is a PMOS transistor constituent portion P ′.
And a reference numeral 110 is an interlayer insulating film.

Thin gate insulating layer (here, SiO ₂ )
The thickness of 108 is 900 Å or less, preferably 500 Å or less, more preferably 350 Å or less, and is set to a thickness at which tunnel current does not flow, specifically, 50 Å or more.
The thickness of the thick gate insulating layer (here, SiO ₂ ) 107 may be thicker than the thickness of the thin gate insulating layer 108, more preferably 10 Å, and optimally 50 Å or more. Note that the specific ratio between the thickness of the thick gate insulating layer 107 and the thickness of the thin gate insulating layer 108 is appropriately selected depending on the design in consideration of the gate voltage.

Using the n-type epitaxial growth layer 102 as a collector, the p-type base region 103 and the n-type emitter region 1 are formed.
And 04 form a bipolar sensor. base,
When the collector is reversely biased, a depletion layer capacitance is formed between the base and the collector. When light is incident on the bipolar sensor unit, the light energy thereof generates photocarriers in the semiconductor layer. Among the generated photocarriers, holes are attracted by the electric field between the base and the collector and trapped in the depletion layer between the base and the collector, causing a change in the base potential according to the value of the depletion layer capacitance. By reading the change in the base potential, an electric signal according to the incident light energy can be extracted.

Here, in the conventional example as shown in FIGS. 21 to 23, the photocarriers generated in the neutral region where no electric field is applied move to another pixel portion by diffusion, and the base and collector of the other pixel. Although crosstalk occurs due to being trapped in the inter-depletion layer, in the present embodiment, the thin gate insulating layer 10 of the PMOS transistor forming portion between pixels is formed.
Since the inversion layer or the depletion layer spreads under 8,
The diffused photocarriers are attracted to and trapped by this electric field, and the leakage into other pixels is suppressed.

Further, the dark current generated at the gate insulating film interface of the PMOS transistor constituent portion P'is also trapped in this depletion layer, and the amount of leakage into the pixel portion is suppressed.

When resetting the carriers in the depletion layer between the base and collector, by further lowering the bias of the gate electrode 109, an inversion layer is formed not only directly under the central portion of the gate electrode but also over the entire surface immediately below the gate electrode. The base regions 103 are electrically connected to each other through the MOS transistor constituent portion P ', and resetting can be performed by the reset power supply in the pixel peripheral portion. Note that such a reset is called a complete reset. Another type of reset is a transient reset in which the base and emitter of the bipolar sensor are forward-biased.

Next, a second embodiment of the present invention will be described.

FIGS. 4 to 7 are schematic configuration diagrams of the second embodiment of the solid-state image pickup device according to the present invention. 4 is a plan view of the photoelectric conversion unit, FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. 4, and FIG. 6 is B of FIG.
-B 'sectional drawing, FIG. 7 is CC' sectional drawing of FIG. The same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted.

In the first embodiment, as shown in FIGS. 2 and 3, the PMOS transistor constituent portion P'according to the present invention is used only for the horizontal separation and the vertical direction is separated by the Locos region. In this embodiment, the PMOS transistor component P'according to the present invention is used for vertical separation as shown in FIGS. 5 and 6, and as shown in FIG.
The s region is made as small as possible.

Note that Si-SiO ₂ under the Locos region is used.
The interface is where stress concentrates and is a large source of dark current.
The dark current can be further reduced by substituting the MOS transistor constituent portion.

Further, in this embodiment, since the channel regions are formed in both the horizontal and vertical directions and the reset can be performed from both directions, the ON resistance of the PMOS transistor constituent portion can be reduced, and as a result, the reset time can be shortened. ..

With respect to the reduction of crosstalk, the same effect as that of the first embodiment can be obtained. 8 to 11 are schematic configuration diagrams of a third embodiment of the solid-state imaging device according to the present invention. 8 is a plan view of the photoelectric conversion unit, and FIG. 9 is AA ′ of FIG.
8 is a sectional view, FIG. 10 is a sectional view taken along the line BB ′ of FIG. 8, and FIG.
6 is a cross-sectional view taken along line CC ′ of FIG. The same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted.

In FIGS. 10 and 11, reference numeral 301 is a second gate electrode layer. In this embodiment, the vertical PMO
The S-transistor component is configured by using two gate electrode layers (in the figure, a broken line region P ″), and
All four vertical directions are separated by the PMOS transistor component according to the present invention. First gate electrode 109 and second
The gate electrodes 301 have the same potential, and work similarly during resetting and storage. By providing two gate electrode layers as in this embodiment, in addition to the effects of the second embodiment,
The flatness of the photoelectric conversion portion can be improved, and the filter process after the wafer process can be easily performed.

12 to 14 are schematic configuration diagrams of the fourth embodiment of the solid-state image pickup device according to the present invention, in which the drain region is provided in the second embodiment. 12 is a plan view of the photoelectric conversion unit, FIG. 13 is a sectional view taken along line AA ′ of FIG. 12, and FIG.
FIG. 13 is a sectional view taken along line BB ′ of FIG. 12. The same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted.

Reference numeral 401 denotes a drain region (which becomes a third semiconductor region) of a PMOS transistor (a broken line region Q in the figure), and the drain region 401 is formed under the thin gate insulating layer 108 at the end of the gate electrode 109 in the length direction. It is provided.
When the gate electrode 109 is biased to form an inversion layer under the thin gate insulating layer 108, the inversion layer under the thin gate insulating layer 108 and the drain region 401 are electrically connected. ing. Reference numeral 402 denotes a gate electrode (which serves as a second control electrode), 403 denotes a source region (which serves as a fourth semiconductor region), and 404 denotes a source electrode.

Reference numeral 405 is a drain region of the complete reset PMOS transistor constituent portion P ', and 406 is a drain electrode layer connected to a complete reset power supply.

During the charge accumulation period, the gate electrode 109 is formed so that the inversion layer is formed below the thin gate insulating layer 108.
Bias to. The inversion layer is formed so as to extend across the pixels and reach the terminal end of the pixel column (the right end in FIG. 12). In addition, the drain region 401 and the source region 4
The gate electrode 402 is biased so that the transistor 03 is conductive. Unnecessary charges collected in the depletion layer under the gate electrode 109 are discarded to the power supply through the inversion layer under the gate, the drain region 401 and the source region 403.

During the reset period, under the entire surface of the gate electrode of the PMOS transistor constituent portion P '(thick gate insulating layer 107
The gate electrode 109 is biased so that an inversion layer is formed under both the gate insulating layer 108 and the thin gate insulating layer 108.

At this time, the gate electrode 402 is arranged so that the drain region 401 and the source region 403 are not electrically connected.
Bias. The p-type base region 103 is a PMOS
The drain region 405 at the end portion of the pixel column is electrically connected to each other through the inversion layer below the transistor forming portion P ′.
Through, it is completely reset to the power supply voltage for reset.

Also in the third embodiment, it is possible to provide the same structure of the PMOS transistor Q, the drain region 405 and the like.

FIGS. 15 to 17 are schematic configuration diagrams of the fifth embodiment of the solid-state image pickup device according to the present invention, in which the source regions 403 of the fourth embodiment are connected to each other, and the source region 403 thereof is connected.
It is configured such that the pixel array is surrounded by. 15 is a plan view of the photoelectric conversion unit, FIG. 16 is a sectional view taken along line AA ′ of FIG. 15, and FIG. 17 is a sectional view taken along line BB ′ of FIG. The same components as those shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, in addition to the effect obtained in the fourth embodiment, the source region 403 having a fixed potential is provided around the pixel column.
Since it is surrounded by, there is an effect that the number of charges leaked from the periphery of the pixel array can be reduced.

The operation at the time of storage and reset is the same as that of the fourth embodiment. Further, the PMOS transistor Q, the drain region 405, the source region 403, and the like as in the present embodiment can be provided in the same manner as in the third embodiment.

18 to 20 are schematic configuration diagrams of a sixth embodiment of the solid-state image pickup device according to the present invention, in which the drain region for discarding unnecessary charges and the drain region for complete reset are made common, and the drain thereof is made common. The area is configured so as to surround the periphery of the pixel array. FIG. 18 is a plan view of the photoelectric conversion part of the present embodiment, and FIG. 19 is AA ′ of FIG.
A sectional view and FIG. 20 are sectional views taken along the line BB ′ of FIG.

The power supply voltage connected to the drain electrode 406 can be changed at the time of accumulation and reset.

During the charge accumulation period, the gate electrode 109 is formed so that the inversion layer is formed below the thin gate insulating layer 108.
Bias to. The inversion layer is formed so as to extend over the pixels and be connected to the end portions between the pixels. The drain region 405 (the second region immediately below the end of the gate electrode)
By providing a semiconductor region) and connecting it to the power supply through the electrode 406, unnecessary charges collected in the depletion layer under the gate electrode 109 are discarded to the power supply through the inversion layer under the gate electrode and the drain region 405.

During the reset period, the drain electrode layer 406
So as to change the power supply voltage connected to the full reset voltage to a complete reset voltage, and to form an inversion layer under the entire surface of the gate of the PMOS transistor forming portion P '(under both the thick gate insulating layer 107 and the thin gate insulating layer 108). On the gate electrode 1
Bias to 09. Base region 103 is PMOS
The drain region 405 at the end portion of the pixel column is electrically connected to each other through the inversion layer below the transistor forming portion P ′.
Is reset to the power supply voltage for complete reset.

Similar drain regions 405 and drain electrode layers 406 can be provided in the third embodiment.

[0040]

As described above, according to the present invention, the thickness of the central insulating layer immediately below the control electrode of the transistor forming portion is made smaller than the thickness of the peripheral insulating layer, so that the control electrode The crosstalk is changed by changing the threshold voltage of the transistor structure between directly under the central part and under the peripheral part and biasing the inversion layer to be formed only under the central part of the control electrode except during the complete reset period. Can be reduced, the noise due to dark current can be reduced, and the image quality of the sensor can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a photoelectric conversion unit of a first embodiment of a solid-state image pickup device according to the present invention.

FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG.

FIG. 3 is a sectional view taken along line B-B ′ of FIG.

FIG. 4 is a plan view of a photoelectric conversion unit of a second embodiment of the solid-state imaging device according to the present invention.

5 is a cross-sectional view taken along the line A-A ′ of FIG.

6 is a cross-sectional view taken along the line B-B ′ of FIG.

7 is a cross-sectional view taken along the line C-C ′ of FIG.

FIG. 8 is a plan view of a photoelectric conversion unit of a third embodiment of the solid-state imaging device according to the present invention.

9 is a cross-sectional view taken along the line A-A ′ of FIG.

10 is a cross-sectional view taken along the line B-B ′ of FIG.

11 is a cross-sectional view taken along the line C-C ′ of FIG.

FIG. 12 is a plan view of a photoelectric conversion unit of a fourth embodiment of the solid-state image pickup device according to the present invention.

13 is a cross-sectional view taken along the line A-A ′ in FIG.

14 is a cross-sectional view taken along the line B-B ′ of FIG.

FIG. 15 is a plan view of a photoelectric conversion part of a fifth embodiment of the solid-state imaging device according to the present invention.

16 is a cross-sectional view taken along the line A-A ′ of FIG.

17 is a cross-sectional view taken along the line B-B ′ of FIG.

FIG. 18 is a plan view of a photoelectric conversion section of a sixth embodiment of the solid-state imaging device according to the present invention.

19 is a cross-sectional view taken along the line A-A ′ in FIG.

20 is a cross-sectional view taken along the line B-B ′ of FIG. 18.

FIG. 21 is a plan view of a photoelectric conversion unit of a conventional solid-state imaging device.

FIG. 22 is a cross-sectional view taken along the line A-A ′ of FIG. 21.

23 is a cross-sectional view taken along the line B-B ′ of FIG. 21.

[Explanation of symbols]

101 n-type substrate 102 n-type epitaxial growth layer 103 p-type base region 104 n-type emitter region 105 emitter electrode 106 P ⁺ type region 107 thick gate insulating layer 108 thin gate insulating layer 109 gate electrode 110 interlayer insulating film 301 second gate electrode Layer 401 Drain region 402 Gate electrode 403 Source region 404 Source electrode 405 Drain region 406 Drain electrode layer

Claims (6)

[Claims] 1. A control electrode is provided on a first conductive type first semiconductor region via an insulating layer, and a second conductive type second semiconductor region is provided in the first semiconductor region below both ends of the control electrode. The semiconductor device, wherein the thickness of the insulating layer immediately below the central portion of the control electrode is smaller than the thickness of the insulating layer other than the central portion. 2. The semiconductor device according to claim 1, wherein a plurality of the control electrodes are provided. 3. The semiconductor device according to claim 1, wherein the second conductive type third semiconductor region has an end portion disposed under a thin insulating layer immediately below a central portion of an end portion in the length direction of the control electrode. And a fourth semiconductor region of the second conductivity type which is adjacent to the third semiconductor region and is connected to a fixed power source, and an insulating layer is provided between the third semiconductor region and the fourth semiconductor region which are adjacent to each other. A semiconductor device having a second control electrode provided therethrough. 4. The semiconductor device according to claim 1, wherein a second semiconductor region immediately below an end of the control electrode is connected to a variable power source, and a second semiconductor region immediately below a center of an end of the control electrode in a length direction. A semiconductor device, wherein an end portion of the second semiconductor region is arranged under a thin insulating layer. 5. The semiconductor device according to claim 3, wherein the fourth semiconductor region has a structure surrounding the periphery of the semiconductor device. 6. The semiconductor device according to claim 4, wherein the second semiconductor region immediately below the end of the control electrode has a structure surrounding the periphery of the semiconductor device.