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JPH05235087A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH05235087A
JPH05235087A JP4038930A JP3893092A JPH05235087A JP H05235087 A JPH05235087 A JP H05235087A JP 4038930 A JP4038930 A JP 4038930A JP 3893092 A JP3893092 A JP 3893092A JP H05235087 A JPH05235087 A JP H05235087A
Authority
JP
Japan
Prior art keywords
bonding
pellet
loop
integrated circuit
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4038930A
Other languages
Japanese (ja)
Inventor
Yukihiko Ishikawa
幸彦 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP4038930A priority Critical patent/JPH05235087A/en
Publication of JPH05235087A publication Critical patent/JPH05235087A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To form a package thin by a method wherein a bonding plane is provided to the bonding pad of a semiconductor pellet as recessed. CONSTITUTION:A bonding plane 1 is provided to a semiconductor pellet 3 as recessed from the upside 3a of the pellet 3. Therefore, a the height of bonding loop can be lessened by a level difference between the upside 3a and the bonding plane 1. Moreover, when the height of the peripheral part of a pellet is lessened, including the bonding plane 1, the same effect as above can be obtained. By this setup, the loop of a bonding wire 2 becomes low, whereby a package can be made thin by the use of a conventional bonding device without changing the loop of the bonding wire 2 in shape.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体集積回路に関し、
特に半導体集積回路ペレットのボンディングパッド部の
構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to the structure of the bonding pad portion of the semiconductor integrated circuit pellet.

【０００２】[0002]

【従来の技術】従来のボンディングパッドは、図２
（ａ）に示すように半導体ペレット３の平面と同一高さ
位置に配され、このパッド部よりボンディングワイヤー
２を介してパッケージのリード部５へ導出されていた。2. Description of the Related Art A conventional bonding pad is shown in FIG.
As shown in (a), they were arranged at the same height as the plane of the semiconductor pellet 3 and led out from the pad portion to the lead portion 5 of the package via the bonding wire 2.

【０００３】しかし、パッケージの薄型化を行う上で
は、ボンディングワイヤーのループがパッケージに収り
きらない事よりこのボンディングワイヤーのループ形状
を低くする必要があり、低ループ専用のボンダー，ワイ
ヤーを使用して図２（ｂ）に示すようなボンディングが
実施されている。However, in order to reduce the thickness of the package, it is necessary to lower the loop shape of the bonding wire because the loop of the bonding wire cannot fit in the package. Therefore, a bonder and a wire dedicated to the low loop are used. Then, the bonding as shown in FIG. 2B is performed.

【０００４】[0004]

【発明が解決しようとする課題】この従来のボンディン
グパッドは、半導体ペレット平面と同一高さ位置に配さ
れている為、パッケージの薄型化を行う上ではボンディ
ングワイヤーのループがパッケージの中に収まりきらな
い事より、ボンディングワイヤーのループ形状を低くす
る為の低ループ専用のボンダー，ボンディングワイヤー
が必要であるという問題点があった。Since this conventional bonding pad is arranged at the same height as the plane of the semiconductor pellet, the loop of the bonding wire may not fit in the package when the package is thinned. There is a problem that a bonder and a bonding wire dedicated to the low loop are required to lower the loop shape of the bonding wire.

【０００５】本発明の目的は、パッケージの薄型化を図
るために、低ループ専用のボンダー並にボンディングワ
イヤーを用いることなく、それを用いたのと同等のボン
ディングが可能となるパット構造を有する半導体集積回
路装置を提供することにある。An object of the present invention is to provide a semiconductor having a pad structure capable of performing bonding equivalent to that using a bonding wire for a low loop without using a bonding wire in order to make the package thin. An object is to provide an integrated circuit device.

【０００６】[0006]

【課題を解決するための手段】本発明の半導体集積回路
装置は、半導体集積回路ペレットのボンディングパッド
部が、ボンディング面を半導体ペレット平面よりペレッ
ト深部方向に落とし込むという構造を有している。The semiconductor integrated circuit device according to the present invention has a structure in which the bonding pad portion of the semiconductor integrated circuit pellet has its bonding surface dropped from the plane of the semiconductor pellet toward the depth of the pellet.

【０００７】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例のボンディングパッド部の
断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a bonding pad portion according to an embodiment of the present invention.

【０００８】図１に示すように、ボンディングパッドの
ボンディング面１を半導体ペレット平面３ａよりペレッ
ト深部方向に落とし込んでいる。その結果落し込んだ分
だけボンディングループ高さを下げることができる。As shown in FIG. 1, the bonding surface 1 of the bonding pad is dropped from the semiconductor pellet flat surface 3a in the pellet depth direction. As a result, the height of the bonding loop can be reduced by the amount of the drop.

【０００９】なお、本実施例はボンディングパッド部の
ボンディング面のみをペレット深部方向に落し込む構造
について述べたが、ボンディング面を含めてペレット外
周部を同様に落とし込んでも同様の効果が得られるのは
いうまでもない。Although the present embodiment has described the structure in which only the bonding surface of the bonding pad portion is dropped in the direction of the deep portion of the pellet, the same effect can be obtained even if the outer peripheral portion of the pellet including the bonding surface is similarly dropped. Needless to say.

【００１０】[0010]

【発明の効果】以上説明した様に、本発明はボンディン
グパッド部のボンディング面を半導体ペレット平面より
ペレット深部方向に落とし込む事によりボンディングワ
イヤーのループ高さを下げボンディングワイヤーのルー
プ形状を変える事なく、従来のボンディング設備を流用
し、パッケージの薄型化に対応出来るという効果があ
る。As described above, the present invention lowers the loop height of the bonding wire by dropping the bonding surface of the bonding pad portion in the direction of the pellet depth from the semiconductor pellet plane without changing the loop shape of the bonding wire. Utilizing the conventional bonding equipment, there is an effect that it can be applied to thinner packages.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例のボンディング部の断面図で
ある。FIG. 1 is a cross-sectional view of a bonding portion according to an embodiment of the present invention.

【図２】図２は従来のボンディング部の断面図で分図
（ａ）は通常の場合、分図（ｂ）は低ループワイヤーを
用いた場合の図である。2A and 2B are cross-sectional views of a conventional bonding portion, where FIG. 2A is a normal case and FIG. 2B is a view when a low loop wire is used.

【符号の説明】[Explanation of symbols]

１ 本発明のボンディング面 ２ ボンディングワイヤー ３ 半導体ペレット ３ａ ペレット平面 ４ パッケージアイランド部 ５ パッケージリード部 ６ 従来のボンディング面 ７ 低ループを用いたボンディングワイヤー 1 Bonding Surface of the Present Invention 2 Bonding Wire 3 Semiconductor Pellet 3a Pellet Plane 4 Package Island Part 5 Package Lead Part 6 Conventional Bonding Surface 7 Bonding Wire Using Low Loop

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体ペレットのボンディングパッド部
においてボンディング面をペレット深部に落とし込むこ
とを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device having a bonding pad portion of a semiconductor pellet, wherein a bonding surface is dropped into a deep portion of the pellet.
JP4038930A 1992-02-26 1992-02-26 Semiconductor integrated circuit device Withdrawn JPH05235087A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4038930A JPH05235087A (en) 1992-02-26 1992-02-26 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4038930A JPH05235087A (en) 1992-02-26 1992-02-26 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05235087A true JPH05235087A (en) 1993-09-10

Family

ID=12538947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4038930A Withdrawn JPH05235087A (en) 1992-02-26 1992-02-26 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05235087A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2790141A1 (en) * 1999-02-22 2000-08-25 St Microelectronics Sa INTEGRATED LOW-DIMENSIONAL CIRCUIT

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2790141A1 (en) * 1999-02-22 2000-08-25 St Microelectronics Sa INTEGRATED LOW-DIMENSIONAL CIRCUIT

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518