JPH05234972A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05234972A JPH05234972A JP3655592A JP3655592A JPH05234972A JP H05234972 A JPH05234972 A JP H05234972A JP 3655592 A JP3655592 A JP 3655592A JP 3655592 A JP3655592 A JP 3655592A JP H05234972 A JPH05234972 A JP H05234972A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- silicon wafer
- back surface
- adhesive tape
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000002390 adhesive tape Substances 0.000 claims abstract description 10
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 238000005336 cracking Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 description 4
- XTXRWKRVRITETP-UHFFFAOYSA-N Vinyl acetate Chemical compound CC(=O)OC=C XTXRWKRVRITETP-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に裏面研削済みのシリコンウェーハの割れおよ
び欠けを防止する方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing cracking and chipping of a silicon wafer whose back surface has been ground.
【０００２】[0002]
【従来の技術】素子形成工程が終了したシリコンウェー
ハは、拡散・電極形成・表面保護膜形成のあと前工程の
最後で裏面を研削し、厚さが揃えられる。2. Description of the Related Art A silicon wafer which has been subjected to an element forming process is ground to have a uniform thickness by grinding the back surface at the end of the previous process after diffusion, electrode formation and surface protection film formation.
【０００３】リードフレームとの密着性を高めるため、
蒸着またはスパッタによって裏面に金を含む金属膜を形
成することもある。In order to improve the adhesion with the lead frame,
A metal film containing gold may be formed on the back surface by vapor deposition or sputtering.
【０００４】このウェーハ仕上げ厚さは４８５μｍか
ら、４００μｍを経て３５０μｍと、次第に薄くなる傾
向にある。The finished thickness of the wafer tends to gradually decrease from 485 μm to 400 μm and then to 350 μm.
【０００５】[0005]
【発明が解決しようとする課題】パッケージ（容器）の
薄型化への要請に応えて、ウェーハ仕上げ厚さは４８５
μｍから、４００μｍを経て３５０μｍに、次第に薄く
なっている。In response to the demand for thinner package (container), the wafer finish thickness is 485.
The thickness gradually decreases from 400 μm to 350 μm through 400 μm.
【０００６】これはボンディングワイヤのループを低
くする。モールド樹脂に占めるチップ（ダイ）の堆積
を減らすことにより耐湿性が向上する。チップが樹脂
に与える歪が低減する。熱によるストレスを緩和す
る。などの効果がある。This lowers the loop of the bonding wire. Moisture resistance is improved by reducing the accumulation of chips (die) in the mold resin. The strain applied to the resin by the chip is reduced. Relieves heat stress. And so on.
【０００７】しかしウェーハが薄くなると、ウェーハ搬
送中や後工程のハンドリングでウェーハが割れて歩留が
低下するという問題があった。However, when the wafer becomes thin, there is a problem that the wafer is broken during handling of the wafer or in the handling of the subsequent steps and the yield is reduced.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、素子が表面に形成された裏面研削済みのシリ
コンウェーハの裏面に、粘着テープを貼り付けるか、ま
たは樹脂を塗布することにより、前記シリコンウェーハ
の割れおよび欠けを防止するものである。According to the method of manufacturing a semiconductor device of the present invention, an adhesive tape is applied or a resin is applied to the back surface of a back surface ground silicon wafer having elements formed on the front surface. The purpose is to prevent cracking and chipping of the silicon wafer.
【０００９】[0009]
【実施例】本発明の第１の実施例について、図１（ａ）
の断面図と、図１（ｂ）および（ｃ）の斜視図とを参照
して説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described with reference to the sectional views of FIGS. 1A and 1B and the perspective views of FIGS.
【００１０】はじめに図１（ｂ）に示すように、素子が
表面に形成されたシリコンウェーハ１の裏面を研削して
厚さ３００μｍに仕上げたのち、裏面に厚さ５００μｍ
の粘着テープ１を貼り合わせて、図１（ａ）に示す断面
構造を得る。First, as shown in FIG. 1 (b), the back surface of a silicon wafer 1 on which elements are formed is ground to a thickness of 300 μm, and then the back surface has a thickness of 500 μm.
The adhesive tape 1 is attached to obtain the cross-sectional structure shown in FIG.
【００１１】つぎに図１（ｃ）に示すように、ウェーハ
１の外周に沿って粘着テープ２を切り取る。Next, as shown in FIG. 1C, the adhesive tape 2 is cut along the outer periphery of the wafer 1.
【００１２】ここで粘着テープ２として、オオクラ商事
が取り扱っている「エレクトロンテープ（エレクトロン
テープ）ＴＹＰＥ ＴＲ−７」を用いた。Here, as the adhesive tape 2, "Electron Tape (Electron Tape) TYPE TR-7" handled by Okura Trading Co., Ltd. was used.
【００１３】つぎに本発明の第２の実施例について、図
１（ｄ）に示すように素子が表面に形成されたシリコン
ウェーハ１の裏面を研削して厚さ３００μｍに仕上げた
のち、裏面に酢酸ビニル樹脂３を回転塗布してから乾燥
させる。Next, in the second embodiment of the present invention, as shown in FIG. 1 (d), the back surface of the silicon wafer 1 on which the elements are formed is ground to a thickness of 300 μm, and then the back surface is formed. The vinyl acetate resin 3 is spin coated and then dried.
【００１４】シリコンウェーハ１の裏面に粘着テープ２
または酢酸ビニル樹脂３を付けたまま、ウェーハ選別、
ダイシングを行なったのち、細分されたチップをアセト
ンなどの有機系溶剤に浸して剥離することができる。An adhesive tape 2 is provided on the back surface of the silicon wafer 1.
Or with the vinyl acetate resin 3 attached, wafer selection,
After dicing, the finely divided chips can be immersed in an organic solvent such as acetone for peeling.
【００１５】[0015]
【発明の効果】素子が表面に形成されたシリコンウェー
ハの裏面を研削したのち、裏面に粘着テープを貼るか、
または樹脂を回転塗布することにより、ウェーハの割れ
や欠けを減らすことができる。EFFECTS OF THE INVENTION After grinding the back surface of a silicon wafer having an element formed on the front surface, an adhesive tape is attached to the back surface, or
Alternatively, by spin-coating the resin, cracks and chips on the wafer can be reduced.
【００１６】たとえウェーハが割れても、粘着テープま
たは裏面樹脂により、ウェーハの形状が保持できるの
で、ウェーハ状態での選別やダイシングができる。Even if the wafer is broken, the shape of the wafer can be maintained by the adhesive tape or the back surface resin, so that sorting and dicing in the wafer state can be performed.
【００１７】したがって製造装置の仕様を変更すること
なく、ウェーハをより薄く研削することが可能になっ
た。Therefore, it becomes possible to grind the wafer thinner without changing the specifications of the manufacturing apparatus.
【図１】（ａ）は本発明の第１の実施例を示す断面図で
ある。（ｂ）および（ｃ）は（ａ）の製造方法を示す斜
視図である。（ｄ）は本発明の第２の実施例を示す断面
図である。FIG. 1A is a sectional view showing a first embodiment of the present invention. (B) And (c) is a perspective view which shows the manufacturing method of (a). (D) is sectional drawing which shows the 2nd Example of this invention.
１ シリコンウェーハ ２ エレクトロンテープ ３ 酢酸ビニル樹脂 1 Silicon wafer 2 Electron tape 3 Vinyl acetate resin
Claims (1)
シリコンウェーハの裏面に、粘着テープを貼り付ける
か、または樹脂を塗布することにより、前記シリコンウ
ェーハの割れおよび欠けを防止する半導体装置の製造方
法。1. A semiconductor device for preventing cracking and chipping of a silicon wafer by applying an adhesive tape or applying a resin to the back surface of a back surface ground silicon wafer having an element formed on the front surface thereof. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3655592A JPH05234972A (en) | 1992-02-24 | 1992-02-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3655592A JPH05234972A (en) | 1992-02-24 | 1992-02-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05234972A true JPH05234972A (en) | 1993-09-10 |
Family
ID=12473007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3655592A Pending JPH05234972A (en) | 1992-02-24 | 1992-02-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05234972A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130576A (en) * | 2006-11-16 | 2008-06-05 | Disco Abrasive Syst Ltd | Wafer conveying method and processing apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59169811A (en) * | 1983-03-16 | 1984-09-25 | Nitto Electric Ind Co Ltd | Sticking process of adhering film |
| JPS6489355A (en) * | 1987-09-29 | 1989-04-03 | Nec Corp | Manufacture of semiconductor device |
-
1992
- 1992-02-24 JP JP3655592A patent/JPH05234972A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59169811A (en) * | 1983-03-16 | 1984-09-25 | Nitto Electric Ind Co Ltd | Sticking process of adhering film |
| JPS6489355A (en) * | 1987-09-29 | 1989-04-03 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130576A (en) * | 2006-11-16 | 2008-06-05 | Disco Abrasive Syst Ltd | Wafer conveying method and processing apparatus |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990706 |