JPH05234381A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate the danger of an excess erasure, to make the speed of a readout operation fast and to reduce a soft write operation when a power- supply voltage is lowered by a method wherein the voltage of a nonselection word line in a readout operation is set to a negative voltage. CONSTITUTION:When a semiconductor memory device is written, a selection word line is set to, e.g. 12V and a nonselection word line is set to -3V. On the other hand, when it is read out, the selection word line is set to a power- supply voltage (e.g. 5V) and the nonselection word line is set to -3V. When the voltage of the nonselection word line in a readout operation is set to be negative, the following effect is obtained. First, even a cell whose Vth causing an excess erasure in conventional cases is negative does not become conductive. Consequently, the problem of the excess erasure is not caused. A margin on the lower side than an erasure judgment level becomes large. As long as the distribution of the Vth in an erased cell is not especially wide, the change width DELTAVth of the Vth between a write operation and an erasure operation can be made large as compared with that in conventional cases. As a result, the speed of the semiconductor memory device can be made high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to an electrically rewritable stack gate memory MOS transistor type non-volatile semiconductor memory device for writing by injecting electrons into a floating gate.

[0002]

2. Description of the Related Art A stack gate (floating gate) memory MOS transistor type non-volatile memory applies a positive voltage to a control gate to apply electrons to the floating gate, as disclosed in Japanese Patent Laid-Open No. 1-158777. Writing is performed by injecting, and the erasing is performed by the control gate, that is,
It is common practice to apply a negative voltage to the word line to inject holes into the floating gate.

According to such a technique, when reading, a potential of 1 V, for example, is applied to the drain (bit line) of the cell, a potential of 0 V is applied to the source (common line), and
V _CC , for example, 5 V is applied to the control gate (word line) to detect whether or not data is written depending on whether or not the channel current flows. That is, no current flows when writing is performed by injecting electrons into the floating gate, and a current flows in the opposite case, so that data can be read by detecting the presence or absence of current.

By the way, the word line (control gate) must be supplied with V _CC (for example, 5 V) for reading when reading, but must be set to 0 V when not selecting when reading. It goes without saying that it will not happen. When writing, the source (common line) is set to 0 V, the drain (bit line) is set to 5 V, and the control gate, that is, the word line is set to a high positive voltage V _PP (+10 to 12 V, for example, 12 V).
V) is applied to cause a considerably large channel current to flow, and electrons are injected from the drain side into the floating gate by the tunnel effect. Also in this case, the word line must be set to 0 V when it is not selected, which is exactly the same as in the case of reading.

When erasing, the drain (bit line) is opened, the source (common line) is set to 5V, and a high negative voltage V _PP, eg, -10V is applied to the floating gate, that is, the word line. The electrons injected in the floating state are extracted to the source, and the written data is lost. As described above, conventionally, the unselected word line at the time of reading was 0V (the selected word line was 5V).

[0006]

By the way, in the prior art, the unselected word line at the time of reading is 0V, and the voltage applied to the selected word line is the power supply voltage of 5V.
In this case, the voltage amplitude was 5V, and the voltage amplitude of the word line at the time of reading was only 5V. In such an electrically erasable non-volatile semiconductor memory device, a problem that has conventionally been a problem is over-erasing. FIG. 5 illustrates this overerasure.

That is, the unwritten bit (cell) is Vth.
Is low, and the written bit has high Vth. Then, although the Vth of the bit written by the erasing becomes low, the Vth varies depending on the cell and the distribution width of the Vth tends to be wide, so that the Vth lower than 0V may occur. Then, for a bit whose Vth is smaller than 0 V, the voltage of the voltage of the non-selected word line is 0 V at the time of reading, so that there is a disadvantage that a current flows even at the time of non-selection. This is overerasure.

By the way, in the case of erasing, if electrons are extracted from the floating gate to the source even for unwritten bits, Vth becomes considerably lower than 0V, and it is surely over-erased. Therefore, when erasing data, first read the data from all the bits to detect the unwritten bits, and then write the unwritten bits, that is, injecting electrons to all the bits. Must be written and then erased, that is, electrons must be extracted from the floating gate.

As described above, excessive erasing must be avoided because current flows even if it is not selected, that is, control by the control voltage becomes ineffective.
Therefore, the initial erase Vth is increased to 1.5 to 2V, which is sufficiently higher than 0V, so that even if Vth varies, bits (cells) of 0V or less cannot be generated. In this case, the erase determination level is about 3 to 3.5 V or higher, and the read speed is inevitably low. As described above, since the amplitude of the power supply voltage is as small as 5 V in the related art, the erasure determination level must be increased to avoid excessive erasing, resulting in a slower reading speed.

Further, there is a tendency for the power supply voltage to be lowered, and there is a demand for the power supply voltage to be 3V even in an electrically erasable non-volatile semiconductor memory device, and technical development corresponding to this is required. Incidentally, even in the nonvolatile semiconductor memory device in which the power supply voltage is set to 3V, the voltage of the non-selected word line needs to be 0V and the voltage of the selected word line needs to be 5V according to the conventional technical idea. This is because, when considering the margin between the Vth after writing the cell and the Vth after erasing, the amplitude at the time of reading the word line is insufficient at 3V, and at least 5V (5V is sufficient as described above. No.) is necessary.

That is, although the power supply voltage is 3 V, it is necessary to boost the voltage for reading to, for example, 5 V, but this is not preferable because it increases the possibility of soft writing during reading. The soft write by reading does not apply a high voltage to the control gate at the time of writing at the time of reading, but, for example, 5
Since a voltage of about V is applied (1 V to the drain), hot electrons are generated, albeit slightly, and are injected into the floating gate by the FN tunnel. Since this soft write has an extremely large dependency on the gate voltage, the lower the voltage applied to the selected word line at the time of reading, the better. However, the power supply voltage is 3
It is foolish from a soft write point of view to boost the voltage of 5V regardless of V and apply the voltage of 5V to the selected word line.

The present invention has been made to solve such a problem, and is an electrically rewritable stack gate memory MOS transistor type non-volatile semiconductor memory for writing by injecting electrons into the control. To provide a novel nonvolatile semiconductor memory device capable of eliminating the problem of excessive erasing, improving read speed, and reducing soft write at the time of reading when the power supply voltage is reduced in the device. With the goal.

[0013]

The nonvolatile semiconductor memory device of the present invention is characterized in that the voltage of an unselected word line at the time of reading is a negative voltage.

[0014]

According to the non-volatile semiconductor memory device of the present invention, the voltage of the non-selected word line is a negative voltage even if the Vth of the cell becomes slightly lower than 0V due to overerasure.
Unless the absolute value of th becomes larger than the absolute value of the negative voltage of the non-selected word line, no malfunction occurs. Therefore, overerasure is eliminated. And the amplitude of the power supply voltage can be increased,
Difference ΔVt between Vth of write cell and Vth of erase cell
Since h can be increased, higher speed can be achieved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The nonvolatile semiconductor memory device of the present invention will be described in detail below with reference to the illustrated embodiments. FIG. 1 is a circuit diagram showing a main part of one embodiment of a nonvolatile semiconductor memory device of the present invention. The nonvolatile semiconductor memory device is a normal stack gate type Flash E ² PROM, and one cell of one word line is extracted and shown in FIG. 1. The control gate is connected to the word line, the source is connected to the common line, and the drain is connected to the bit line.

T1 and T2 are MOS transistors forming a CMOS inverter that receives a row input signal Rowin produced by converting the level of a signal from an address decoder. T1 is a p-channel MOS transistor and T2 is n.
It is a channel MOS transistor. The source of T1 is the power supply voltage V _ROWP terminal, and the source of T2 is the power supply voltage V _{RO WN}
It is connected to the terminal. The output point of this CMOS inverter is connected to the word line.

FIG. 2 shows an n-channel MOS transistor T
FIG. 2 is a cross-sectional view showing that 2 has a double well structure.
The n-channel MOS transistor T2 has a double well structure, that is, the n-type well 2 is formed in the p-type substrate 1, the p-type well 3 is formed in the n-type well 2, and the p-type well 3 is formed. The structure in which the transistor is formed is to prevent forward bias between the substrate 1 and the drain and leakage of current to the substrate when a negative voltage is applied to the drain of the MOS transistor T2.

The word lines at the time of writing and reading in the nonvolatile semiconductor memory device will be described. At the time of writing, the selected word line is set to 12 V, the non-selected word line is set to -3 V, and at the time of reading, the selected word line is powered. Voltage, that is, 5V if the power supply voltage is 5V,
If the power supply voltage is 3V, it is set to 3V, and the non-selected word line is set to -3V. Incidentally, in the conventional case, when the power supply voltage is 3 V, the selected word line is set to 5 when reading.
It was V. Table 1 below shows changes in each voltage during writing and reading.

[0019]

[Table 1]

In this way, by changing each voltage at the time of reading, the word line can be changed as described above. Then, in the present nonvolatile semiconductor memory device, the voltage of the non-selected word line at the time of reading is set to a negative voltage (in this example, −
3V, but not limited to this, for example, -2V to-
The biggest feature is that it can be 5V. FIG. 3 shows the level (solid line) of the non-selected word line at the time of reading in comparison with the prior art.

As described above, the following effects are inevitably obtained by setting the voltage of the non-selected word line at the time of reading to a negative voltage. First, since the level of the non-selected word line at the time of reading is a negative voltage, V which is over-erased in the conventional case.
Even if th is a negative cell, it does not conduct (of course, it conducts when Vth becomes −3 V or less, but it cannot occur unless a special abnormality occurs). Therefore, the problem of overerasure disappears. Then, the margin below the erase determination level becomes large, and the Vth of the erased cell is increased.
As long as the distribution width of Vth does not become particularly wide, the fluctuation width ΔVth of Vth between writing and erasing can be made larger than that in the prior art, so that the speed can be increased.

Next, when the power supply voltage of the nonvolatile semiconductor memory device is lowered to 3V, the following effects can be obtained by the nonvolatile semiconductor memory device. First, the power supply voltage (3V) is used as it is as the voltage applied to the selected word line at the time of reading, and the insufficient amplitude of the voltage of the word line at the time of reading can be covered by setting the negative voltage of the non-selected word line to the drain.・ By lowering the voltage between the control gates than before, soft writing during reading can be reduced.

As described above, in the conventional case, there is no idea of setting a non-selected word line to a negative voltage at the time of reading,
Since it was set to 0V, Vth after writing and Vth after erasing
Since a minimum voltage of 5V is required for the voltage of the word line at the time of reading in order to secure the margin of th, it is necessary to boost the power supply voltage of the selected word line to 5V. However, in this case, a soft light corresponding to 5V is generated, which means that the soft light is purposely strengthened.

However, according to the nonvolatile semiconductor memory device of the present invention, the voltage of the non-selected word line is set to − when the power supply voltage (3V) is set without increasing the voltage of the selected word line at the time of reading.
By setting a negative voltage such as 3V, the amplitude of the voltage at the time of reading can be secured or expanded. Then, the selected word line that influences the soft write is 3V, and the soft write is reduced.

Secondly, as shown in FIG. 4, there is an effect that the amount of electrons injected into the floating gate at the time of writing can be reduced. That is, in the past,
Writing was performed by injecting a charge of 5 to 6V from the initial state in which the charge amount of the floating gate was 0. However, when the power supply voltage is lowered to 3V in this nonvolatile semiconductor memory device, As shown in FIG. 2, writing can be performed only by charging for 2.5 to 3.5 V from the initial state, the electric field strength applied to the tunnel film (thickness of about 100 angstrom) is reduced, and the stress is reduced.

Assuming that the C ratio (that is, the capacitance between the control gate and the floating gate / the total capacitance around the floating gate) is 0.6, a tunnel film having a thickness of 100 angstroms has a conventional thickness of about 3 to 4 V / c.
Although an electric field of m is applied, it can be weakened to 1.5 to 2 MV / cm by the nonvolatile semiconductor memory device. In other words, this means that in the conventional case, the number of word lines is five.
The amount of charge required to cut off the voltage to V was required, but according to this nonvolatile semiconductor memory device, the word line is set to 3V.
That is, the amount of charge that can be cut off is sufficient, so that the amount of charge can be reduced, and in turn, the strength of the electric field applied to the tunnel film by the charge can be reduced. In the nonvolatile semiconductor memory device of the present invention, erasing (Verify) may be performed under the same conditions as the conventional one.

[0027]

The nonvolatile semiconductor memory device of the present invention is characterized in that the voltage of the non-selected word line at the time of reading is a negative voltage. Therefore, according to the nonvolatile semiconductor memory device of the present invention, the V
No malfunction occurs if th becomes slightly lower than 0V. Therefore, the problem of over-erasure is eliminated. Then, the amplitude of the power supply voltage can be increased, and Vth of the write cell and Vth of the erase cell can be increased.
Since the difference ΔVth from th can be increased, higher speed can be achieved.

When the power supply voltage is lowered, the voltage of the non-selected word line is set to a negative voltage without boosting the voltage of the selected word line at the time of reading, so that the voltage of the word line at the time of reading can be reduced. The amplitude can be ensured to be large enough. Since the voltage of the selected word line at the time of reading can be lowered, read disturb (soft writing at the time of reading) can be reduced, and since it is sufficient to write the amount of electrons to cut off at a low voltage,
The write charge amount can be reduced, and the electric field applied to the tunnel film by the charge can be weakened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of one embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a schematic sectional view of an n-channel MOS transistor T2 of the circuit shown in FIG.

FIG. 3 is a diagram showing the levels of non-selected word lines at the time of reading in the above-mentioned embodiment in comparison with the conventional case.

FIG. 4 is an explanatory diagram of write charge when the power supply voltage is lowered to 3V in the present embodiment.

FIG. 5 is an explanatory diagram of overerasing, which is a conventional problem.

[Explanation of symbols]

 CG control gate FG floating gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (1)

[Claims] 1. In an electrically rewritable stack gate memory MOS transistor type non-volatile semiconductor memory device for writing by injecting electrons into a floating gate, a voltage of a non-selected word line at the time of reading is a negative voltage. Non-volatile semiconductor memory device characterized by