KR0172364B1 - Elimination detecting method using reference cell of non-volatile semiconductor memory - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

Nonvolatile Semiconductor Memory

2. The technical problem to be solved by the invention

An improved erase verification method in a memory of a folded bit line structure is provided.

3. Summary of Solution to Invention

A plurality of memory transistors constitute a single NAND cell string, and the memory transistors are arranged in a matrix form on word lines in a row direction and bit lines in a column direction to form a memory cell array, and the bit lines have a folded bit line structure. And an erase verification method of a nonvolatile semiconductor memory having a selection transistor and a reference cell to provide a reference voltage to the bit line; Applying a second reference voltage of the first and second reference voltages to the control gate of the reference cell after the memory transistor in the memory cell array is erased; Comparing the voltage level of the bit line connected to the erased memory transistor with the second reference voltage; Verifying when the voltage level of the bit line is less than or equal to the second reference voltage.

4. Important uses of the invention

It is suitably used for erasure verification of nonvolatile semiconductor memory.

Description

Erasing Verification Method Using Reference Cell of Nonvolatile Semiconductor Memory

1 is a circuit diagram of a semiconductor memory applied to the prior art.

2 is an operation timing diagram relating to erasure verification of the circuit according to FIG.

3 is a circuit diagram of a semiconductor memory according to the present invention.

4 is an operation timing diagram relating to erasure verification of the circuit according to FIG.

FIG. 5 is a circuit diagram illustrating a method of applying a reference voltage to the reference cell of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile semiconductor memories, such as NAND type EEPROMs, and more particularly to an improved erase verification method in a memory having a folded bit line structure.

In general, in a flash memory of a NAND structure having a cell array composed of string units in which a plurality of memory cells are connected in series among nonvolatile semiconductor memories, a circuit as shown in FIG. 1 has a typical folded bit line structure. In FIG. 1, the reference cell portion includes the reference cell selection transistors 2, 3, and the reference cell 20, and the memory cell portion includes the memory cell selection transistors 21, 31, 22, 32, and the memory cell transistors 10. The sense amplifier 30 is connected between the bit lines BL1 and 2, and the word line is connected to the control gate of the memory cell transistors. The memory cell transistors each include a transistor having a floating gate and a control gate that store electric charges, and have a NAND cell structure to facilitate integration. The memory cell transistors and the selection transistors have a structure connected in series, which is referred to in the art as a NAND cell unit or a memory cell string.

When the program of the memory cell transistors in the memory cell string is completed or erased, electric charges may be present or absent in the floating gate. In other words, the programmed memory cell (data 0, i.e., an off-cell) operates as an enhancement transistor having a threshold voltage of, for example, about 1 volt. On the contrary, the memory cell when the erase is completed is, for example, weak. It operates as a depletion transistor having a threshold voltage.

Here, erase verification is necessary to confirm whether all of the erased memory cell transistors operate as transistors of an established mode (enhanced or depletion mode) after completion of the erase operation.

A conventional erase verification method will be described below with reference to FIG. 1 having the above-described configuration and FIG. 2 showing the operation timing of FIG.

In Fig. 1, the erase verification method is the same as the normal read operation of a general NAND type memory, which is a voltage developed on a corresponding bit line depending on whether an erase state of a cell selected by an enabled word line and a string select transistor is present. The levels of are different. In this case, when the cell is on cell (assuming that it is an erased cell), the corresponding bit line is developed to almost ground level as Vb1-on of waveform 2B of FIG. 2, on the contrary, for example, when the cell is off cell, the power supply is almost The voltage level is maintained at Vcc. Referring to 2b of FIG. 2, it can be seen that there is a reference level Vbl-ref which is an intermediate level between the power supply voltage level and the ground level. The sense amplifier 30 senses a level difference between two bit lines based on the reference level. Erasing verification can be accomplished by performing an operation. Therefore, it can be seen that the conventional erasure verification technique is as follows. That is, a cell corresponding to only a lower level based on the reference level was considered as whether or not the erase was actually performed after the erase operation. Therefore, even if the erase of the selected cell is not complete, it can be seen that the verification passes when the reference level is lowered. However, when the normalization is performed next with the erased cells as described above, there is a problem in that the level difference between the sensing margin, that is, the level difference between the Vbl-on and the reference level Vbl-ref of the waveform 2b is reduced. This is shown in the sections T2 and T4 of FIG. Here, the sections T1 and T3 are erase sections, respectively, and the T2 and T4 are verification sections respectively.

As described above, since the erase verification is conventionally performed by determining a difference between the voltage level of the bit line and one reference level, the sensing margin is reduced during normal read operation, resulting in a decrease in reliability of data. there was.

Accordingly, it is an object of the present invention to provide an improved erasure verification method for a nonvolatile semiconductor memory which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a method capable of stably guaranteeing a read operation of a semiconductor memory device.

According to the method of the present invention for achieving the above object, a plurality of memory transistors constitute a single NAND cell string, the memory transistors are arranged in a matrix form on the word line in the row direction and the bit line in the column direction of the memory A method of erasing and verifying a nonvolatile semiconductor memory, comprising: forming a cell array, the bit line having a folded bit line structure, and having a selection transistor and a reference cell to provide a reference voltage to the bit line; After the memory transistors in the memory cell array are erased, applying a second reference voltage among preset first and second reference voltages to a control gate of the reference cell; Comparing the voltage level of the bit line connected to the erased memory transistor with the second reference voltage; And verifying when the voltage level of the bit line is less than or equal to the second reference voltage.

Hereinafter, with reference to the accompanying drawings, the operation of a preferred embodiment of the present invention will be described in detail. FIG. 3 is a circuit diagram of a semiconductor memory according to the present invention. FIG. 4 is an operation timing diagram related to erasure verification of a circuit according to FIG. 3, and FIG. 5 is a diagram illustrating applying first and second reference voltages to a reference cell of FIG. A circuit diagram for explaining the method.

Referring to FIG. 3, the connection and structure of the reference cell unit, the memory cell unit, and the sense amplifier 30 are illustrated. The reference cell portion includes reference cell selection transistors 2, 3 and reference cell 20 connected to bit lines of a folded bit line structure, and the memory cell portion includes memory cell selection transistors 21, 31, 22, 32, and memory cell transistors 10. It consists of. The sense amplifier 30 is connected between the bit lines BL1 and 2, and the word line is connected to the control gate of the memory cell transistors. Each of the memory cell transistors is connected to a transistor having a floating gate and a control gate, each of which stores charge. Here, the configuration of FIG. 3 is similar to that of FIG. 1, but the reference cell 20 receives the first and second reference voltages in the first and second modes, that is, the characteristic of the erase verification according to the present invention is a sensing margin. In order to increase, the reference voltage applied to the reference cell is divided into at least two, and the first reference voltage is applied during normal read and the second reference voltage is applied during erase verification. Among the conventional reference level setting methods, there is a method of setting a reference level of a bit line by applying a single reference voltage to a control gate of a reference cell. In the present invention, the first reference voltage Vref1 is applied to the bit line during normal read. The second reference voltage Vref2 is used for setting the reference level and the bit line reference level for erasing verification. Here, when the first reference voltage is lower than the second reference voltage, the sensing margin at the time of normal read may be increased and more stable verification may be performed at the time of erase verification.

5 shows a circuit for outputting such first and second reference voltages as an example. A switching unit composed of the first reference voltage generator 50, the second reference voltage generator 51, the switching transistors T1, T2, and the inverter I1 constitutes the circuit. The detailed configuration of the second reference voltage generator 51 may be implemented as a detailed view of the bottom.

Hereinafter, the overall operation will be described with reference to the third, fourth, and fifth degrees as necessary. First, erasing of memory cells before erasure verification is generally accomplished by applying an erase voltage to the bulk (substrate). This lowers the threshold voltage of the memory cell erased by the F-N tunneling principle (assuming erasing on cell). In this state, erasure verification starts. That is, verification is the operation of determining how much the threshold voltage of the memory cell has changed to the set value. According to the threshold of the erased cell, the memory cell string changes the degree of development of the precharged bit line level after the word line is enabled. After the desired level is set to the second reference voltage, erase verification is performed like the normal read. When the erase is a little less, the bit line level developed by the erase cell is set by the second reference voltage. It is higher than the developed level of the reference cell string, which is read as off-cell when sensing. In this case, the erase operation is performed again, and the level of development of the cell string becomes lower than the level of development of the reference cell string after the re-validation verification. As a result, as shown in FIG. 4, when it is found as on-cell after sensing, it can be seen that the level of cell erasure is located below the desired level.

In FIG. 4, the level difference between Vbl-on of the waveform 4b and the reference level Vbl-ref1 increases compared with the prior art. This is shown in the sections T6 and T8 of FIG. In this case, sections T5 and T7 are erase sections, respectively, and T6 and T8 respectively represent verification sections.

According to the present invention as described above, the sensing margin is increased during the normal read operation is effective in increasing the reliability of the data.

Claims (4)

A plurality of memory transistors constitute a single NAND cell string, and the memory transistors are arranged in a matrix form on word lines in a row direction and bit lines in a column direction to form a memory cell array, and the bit lines have a folded bit line structure. An erase verification method of a nonvolatile semiconductor memory having a transistor and a reference cell to provide a reference voltage to the bit line; Applying a second reference voltage of the first and second reference voltages to the control gate of the reference cell after the memory transistor in the memory cell array is erased; Comparing the voltage level of the bit line connected to the erased memory transistor with the second reference voltage; And verifying when the voltage level of the bit line is less than or equal to the second reference voltage. The method of claim 1, wherein the second reference voltage is higher than the first reference voltage. The method of claim 1, wherein the first reference voltage is provided to the control gate of the reference cell during normal reading. A method of driving a nonvolatile semiconductor memory having a selection transistor, a reference cell, and a memory cell array to provide a reference voltage to a bit line of a folded structure; After the memory transistor in the memory cell array is erased, the erased memory cell is verified by applying a second reference voltage among the first and second reference voltages preset during the erase verification to the control gate of the reference cell, The method of claim 1, wherein the sensing margin is increased by applying the first reference voltage to the control gate of the reference cell.