JPH0522273A - Data identification reproduction circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a data identification and reproduction circuit that can automatically punch out and reproduce the received signal always in the correct phase relationship, regardless of variations in circuits and elements, environmental condition changes, and temporal changes. To do. A variable phase circuit for controlling the phase of a clock signal is provided, and the phase amount of the variable phase circuit is controlled by a phase difference signal between an input signal of a flip-flop circuit and a data output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data discriminating and reproducing circuit in an optical receiver used for optical communication.

[0002]

2. Description of the Related Art In digital signal transmission using an optical fiber, as shown in FIG. 1, an optical signal sent by the optical fiber is converted into an electric signal by a photodiode PD, amplified by an amplifier circuit Amp, and then discriminated and reproduced. The circuit was designed to output as data and clock signals.

When the transmission distance is long, the signal is attenuated and becomes weak, so that the waveform becomes dull and increased in noise as shown in FIG. 3A, for example, and the signal is discriminated and reproduced by the discriminating and reproducing circuit. Was doing.

FIG. 4 is a block diagram of a conventional identification / reproduction circuit when the received signal input is an NRZ signal.

The received signal is input to the full-wave rectifier circuit 2 in addition to the flip-flop circuit 1, the clock signal component of the received signal is extracted by the SAW filter 3, and then the limit amplifying circuit 4 regenerates the clock signal.

This clock signal is delayed by a predetermined phase by the delay line 5 and then input to the flip-flop circuit 1 to punch out the received signal in the correct phase, so that there is no time axis distortion as shown in FIG. 4 (b). Output playback data.

[0007]

In the above conventional identification / reproduction circuit, the delay amount of the delay line 5 is adjusted to the delay amount in the flip-flop circuit 1, the full-wave rectifying circuit 2, the SAW filter 3, the limit amplifying circuit 4 and the like. Therefore, if the delay amount of each circuit changes due to the variation of each circuit or element or the variation of the environmental condition, the consistency of the delay amount of the delay line 5 is lost. There is a problem that the bit error rate increases and the reception sensitivity decreases.

An object of the present invention is to provide a data discriminating and reproducing circuit capable of automatically and correctly adjusting the delay amount of the delay line 5.

[0009]

In order to solve the above-mentioned problems, a variable phase circuit for controlling the phase of the clock signal is provided, and the variable phase circuit is provided by a phase difference signal between an input signal and a data output of the flip-flop circuit. Control the phase amount of the circuit.

Further, a clock signal extraction circuit is provided to extract the clock signal from the input signal.

[0011]

By controlling the variable phase circuit, the phase difference between the input signal and the data output of the flip-flop circuit is automatically maintained at a predetermined optimum value.

Further, the clock signal is extracted and generated from the input signal.

[0013]

1 is a block diagram of an embodiment of a data identification / reproduction circuit according to the present invention.

The received signal is input to the full-wave rectifier circuit 2 in addition to the flip-flop circuit 1, the clock signal component of the received signal is extracted by the SAW filter 3, and then the limit amplifier circuit 4 waveform-shapes the reproduced clock signal. To be done.

The phase of this clock signal is adjusted by the variable phase circuit 10 and input to the flip-flop circuit 1.
The received signal is punched out and reproduced data is output.

The flip-flop circuit 1 needs to punch out the received signal in the correct phase relationship using the clock signal.

Therefore, the phase difference between the input data and the output data of the flip-flop circuit 1 is detected by the phase comparison circuit 7, and the detection result is integrated by the integration circuit 8 to obtain a DC signal corresponding to the average phase difference. Then, the phase amount of the variable phase circuit 10 is adjusted by the comparison result signal (phase error signal) obtained by comparing this with the reference voltage Vref by the comparator 9. As a result, the clock signal input to the flip-flop circuit 1 can be automatically matched to the phase of the input data and the received signal can be punched out in the correct phase relationship.

An EX-OR circuit can be used for the phase comparison circuit 7, and a crystal band filter, a narrow band pass filter using LC, or a P filter is used for the SAW filter 3.
LL or the like can be used.

The variable phase circuit 10 is driven by a circuit for driving the set and reset terminals of the flip-flop circuit by two signals obtained by comparing the integration of the input signal with a reference voltage, and by the output of the comparator 9. It is also possible to use a mechanical variable phase machine whose delay amount is controlled by a stepping motor.

[0020]

According to the present invention, since the received signal can always be automatically punched and reproduced in a correct phase relationship, variations in each circuit, elements, etc., variations in environmental conditions, and variations in phase amount due to changes over time are automatic. It is possible to prevent the deterioration of the performance of the data discriminating / reproducing circuit.

In addition, the code error rate can be reduced, the reliability of the optical receiver can be improved, the adjustment man-hour can be reduced, and the maintenance can be facilitated.

The parts other than the SAW are monolithic I
Since it becomes possible to implement C, it is possible to provide a small-sized, highly reliable, low-priced data identification and reproduction circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a general optical transmission / reception system.

FIG. 3 is an example of waveforms of received and reproduced signals.

FIG. 4 is a block diagram of a conventional data identification and reproduction circuit.

[Explanation of symbols]

1 flip-flop circuit 2 full-wave rectifier circuit 3 SAW filter 4 Limit amplification circuit 5 delay lines 7 Phase comparison circuit 8 integrating circuit 9 comparator 10 Variable phase circuit

Claims (2)

[Claims] 1. A variable phase circuit for controlling the phase of the clock signal, and a flip-flop circuit in a data discriminating and reproducing circuit comprising a flip-flop circuit for punching out an input signal by a clock signal and outputting data discriminated and reproduced. And a phase comparison circuit for detecting the phase difference between the input signal and the data output, and the clock signal phase of the variable phase circuit is controlled by the output signal of the phase comparison circuit. circuit. 2. A data discriminating / reproducing circuit according to claim 1, further comprising a clock signal extracting circuit, whereby the clock signal is extracted and generated from an input signal of the flip-flop circuit.