JPH0575588A - Digital signal clock reproduction circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the phase deviation of a recovered clock in a received clock recovery circuit of a digital communication device. [Structure] Bandpass filter 1 and variable gain amplifier circuit 4
In the clock recovery circuit including the limiter amplifier circuit 6, the peak value detection circuit 8 detects the output amplitude 5 of the variable gain amplifier circuit 4 and keeps the output signal amplitude 5 constant.
A circuit for controlling the gain control voltage 11 of the variable gain amplifier circuit 4 is added. [Effect] Even if the mark ratio of the received digital signal varies, the input amplitude of the limiter circuit is kept constant and the phase deviation of the recovered clock is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception clock recovery circuit for a digital communication device.

[0002]

2. Description of the Related Art In digital communication, it is necessary to regenerate a clock signal synchronized with an incoming digital signal at a receiving section. Various methods have been proposed for recovering a clock signal in the receiving unit, but a typical conventional method is as described in "Technology of PCM communication", Kogaku Shuppan, PP 84-86, (1976). There is a method of limiting the amplitude of the clock component extracted by the bandpass filter by a limiter.

[0003]

Generally, in the case of extracting a clock component by passing a received digital signal through a bandpass filter, if the ratio (mark ratio) of "1" of the input digital signal changes, the The amplitude of the extracted clock component changes. In the above-mentioned conventional technique, since this timing component is directly input to the limiter, a change in the amplitude of the timing component causes a phase deviation in the output clock signal, which adversely affects subsequent digital signal transmission. was there.

An object of the present invention is to reduce the phase deviation of the clock signal.

[0005]

The above object is to add a variable gain amplifier circuit between a bandpass filter and a limiter, and change the gain so that the output amplitude of the variable gain amplifier circuit is constant. Will be achieved.

[0006]

Since the output signal amplitude of the variable gain amplifier circuit output is kept constant even when the input mark ratio changes, a limiter circuit is used to reshape the output signal to regenerate the clock signal. However, no phase deviation occurs.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of signal waveforms at respective points. The received digital signal 1 is added to the band pass filter 2, the clock component 3 is extracted, and amplified by the variable gain amplifier circuit 4. The output signal 5 of the gain amplifier circuit is shaped into the clock signal 7 by the limiter circuit 6. Here, the gain control voltage 1 of the variable gain amplifier circuit 4
1 is applied with a voltage which is the difference between the amplitude of the output signal 5 detected by the peak value detection circuit 8 and the reference voltage 9. When the amplitude of the band-pass filter output signal 3 changes due to fluctuations in the mark ratio of data, the gain variable amplifier circuit gain changes so that the variable gain amplifier circuit output amplitude 5 becomes constant. Therefore, the reproduced clock signal 7 shaped by the limiter has no phase deviation. On the other hand, in FIG. 2 and FIG.
The block diagram of the clock recovery circuit by a prior art and the signal waveform of each point are shown. In this case, the output amplitude of the band-pass filter 2 changes due to the mark rate fluctuation of the received digital signal 1, and the output signal 12 is input to the limiter circuit 6 as it is. Therefore, as shown in FIG. Causes an output phase deviation due to the input amplitude fluctuation due to the amplitude phase conversion effect of the limiter circuit. According to this embodiment, the phase deviation of the reproduced clock signal can be reduced. In this embodiment, the received digital signal has a duty of 50.
% Of RZ (R eturnto Z ero) has been described as a signal, NRZ (N on R eturn to Z e
In the case of the (ro) signal, a similar effect can be expected by inserting a non-linear circuit such as a folding circuit before the band pass filter and extracting the clock component.

[0008]

According to the present invention, it is possible to construct a clock reproducing circuit in which the phase deviation of the clock signal is reduced, and it is possible to accurately identify and reproduce the digital signal by using the reproduced clock.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a clock recovery circuit according to the present invention,

FIG. 2 is a block diagram of a clock recovery circuit according to the related art;

FIG. 3 is a waveform diagram of each part of the clock recovery circuit according to the present invention,

FIG. 4 is a waveform diagram of each part of the clock recovery circuit according to the related art.

[Explanation of symbols]

 1 ... Received digital signal, 2 ... Band pass filter, 4 ... Gain variable amplification circuit, 6 ... Limiter circuit, 7 ... Regenerated clock signal, 8 ... Peak value detection circuit, 9 ... Reference voltage.

Front page continued (72) Inventor Makoto Maruyama 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Ltd. Totsuka factory

Claims (1)

[Claims] 1. A circuit for regenerating a clock signal synchronized with a digital signal from a received digital signal, which comprises a bandpass filter, a variable gain amplifier circuit, and a limiter circuit. A digital signal clock recovery circuit characterized by adding a circuit for changing the output amplitude to be constant.