JPH0521388A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] A method for improving the formation of source / drain (S / D) electrodes of a fine MOS field effect transistor (MOSFET), which is suitable for the miniaturization of the device and has excellent characteristics. It is intended to provide a method of forming a contact. [Composition] A step of forming a semiconductor film such as poly-Si or a conductor film containing a metal after opening the contact hole, and then performing ion implantation in the conductor film to form an impurity of the same conductivity type as that of the S / D region. And a heat treatment for reducing the resistance of the contact portion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming electrodes of a semiconductor device, and more particularly to a fine MOS field effect transistor (M
OSFET) source / drain (S / D) electrode formation method.

In recent years, along with the trend of miniaturization of devices,
The shallowization of the S / D area is progressing. As a result, the S / D resistance increases, and the effect of this on the device characteristics cannot be ignored.

[0003]

[Prior Art] As a measure for increasing S / D resistance, the conventional S / D
We are trying to reduce the S / D resistance by providing a low resistance layer on the surface. This low resistance layer is based on the well-known Silic
ideS / D technology, or Salicide (Self Aligned Silicid
e) Formed using S / D technology. Figure 4 is a diagram explaining the steps of forming electrode wiring in the S / D of a MOSFET by the conventional method.

As shown in FIG. 4A, a field oxide film 32 having a thickness of 500 nm is formed on the surface of a p-type Si substrate 31, and S / D
The region 33 contains phosphorus (P) ions with an energy of 30 KeV and a dose of
An N ^- layer is formed by implanting at ^{1x10 13} cm ^-2 , a gate oxide film (SiO ₂ film) 34 with a thickness of 10 nm, a gate electrode (poly Si film) 35 with a thickness of 300 nm, and further on that. 30 nm thick oxide film (CVD
A SiO ₂ film) 36 is formed. Next, as shown in Fig. 4 (b), a sidewall 37 of SiO _{2 with} a width of 0.1 μm is formed on the side surface of the gate electrode 35 by the conventional method, and then arsenic (As) is formed in the S / D region 33. ) With an energy of 30 KeV and a dose of 4 x 10 ¹⁵ cm ^-2 , and the N ⁺ layer (S / D diffusion layer) 38
To form. Next, as shown in Fig. 4 (c), the N ⁺ layer 38
Titanium silicide (TiSi ₂ ) about 60 nm deep from the surface of
Layer 39 is a normal Ti sputter deposit and two RTA (rapi
d thermal annealing) processing method. next,
As shown in Fig. 4 (d), 400 nm thick BPSG (bor
o-phospho silicate glass) film is deposited as the interlayer insulating film 40, and the BPSG film 40 and TiSi ₂ S / D area opening through layer 39 (
Contact holes) 41, 42 are formed to expose the N ⁺ layer 38. Next, as shown in Fig. 4 (e), the thickness 20
nm BPSG film 43 is deposited, and S / D area openings 41 and 42 are selectively
Energy of P ion is 30 KeV, Dose amount ^{1x10 15} cm ^-2
To further increase the concentration of the N ⁺ layer 38 in contact with the bottoms of the S / D region openings 41 and 42. Finally, as shown in Fig. 4 (f), after removing the BPSG film 43, a 0.5 μm-thick Si film is applied to the N ⁺ layer 38 in contact with the bottoms of the S / D region openings 41 and 42. Aluminum containing a percentage is formed for wiring.

[0005]

SUMMARY OF THE INVENTION In the above method,
Etching is performed by reactive ion etching (RIE) to form S / D region openings 41 and 42 in the interlayer insulating film 40 shown in Fig. 4 (d), but the TiSi ₂ layer 39 is removed at that time. In some cases, part of the N ⁺ layer 38 is also removed. Also, after the etching by RIE, the resist is removed, and the TiSi ₂ layer 39 is similarly removed in the step of performing the surface treatment with a dilute solution of hydrofluoric acid.

As a matter of course, this causes an increase in contact resistance or non-ohmic contact characteristics. As a countermeasure against these, as shown in Fig. 4 (e), after forming the S / D region openings 41 and 42, through the insulating film 43 such as BPSG, the same conductivity type as the N ⁺ layer 38, that is, The n-type impurities were selectively ion-implanted into the S / D region openings 41 and 42.

However, in such a compensation ion implantation method, whether the ions are implanted into the N ⁺ layer 38 by penetrating the insulating film 43 by increasing the energy of the ions,
Alternatively, it is necessary that a part of the distribution of the implanted ions be in a form of protruding from the insulating film 43 into the N ⁺ layer 38. In any of these cases, the depth after activation of the ion-implanted layer becomes large, which becomes a factor that hinders the miniaturization of the device. There is also a problem that the throughput is deteriorated due to the large dose amount. Furthermore, since the energy is large, the damage due to the implantation is not completely recovered by the heat treatment, and thus the contact resistance is increased.

Therefore, the present invention is suitable for miniaturization of devices,
Moreover, it is an object of the present invention to provide a method for forming a contact with a semiconductor having good characteristics.

[0009]

[Means for Solving the Problems] The above problem is caused by the step of forming a conductor film including a semiconductor film such as poly-Si or a metal after opening a contact hole, and then ion implantation into the conductor film. This is all solved by a method for forming a contact on a semiconductor, which includes a step of doping an impurity of the same conductivity type as that of the S / D region and a step of performing a heat treatment to reduce the resistance of the contact portion thereafter.

FIG. 1 is a diagram illustrating the principle of the present invention. 1 is Si
Substrate, 2 is a field oxide film, 13 is an interlayer insulating film made of BPSG, 16 is a conductor film made of poly-Si or silicide, 9 and 10 are N ⁺ layers, and 11 is a silicide layer. Unlike the conventional method, the compensation ion implantation in the present invention is performed in the conductor film 16. By the subsequent heat treatment step, the impurity atoms injected into the conductor film 16 are solid-phase diffused into the N ⁺ layers 9 and 10, and a shallow contact diffusion layer is formed.

[0011]

[Operation] In FIG. 1, since the conductor film 16 itself has a role of a contact layer, all the implanted ions contribute to the reduction of the contact resistance. That is, compared to the conventional method, S
Less ions reach the surface of the Si diffusion layer in the / D region,
The occurrence of damage can also be prevented. Therefore, even if the annealing temperature is low, it is possible to prevent an increase in leak current and contact resistance after activation. Also, a conductor film 16 is formed on the bottom of the contact hole.
Since Al is deposited, the coverage ratio of Al in the case of depositing Al for wiring is improved as compared with the case without the conductor film 16. Therefore, no breakage of Al wiring occurs and reliability is improved.

Instead of the conductor film 16 shown in FIG. 1, a selective growth layer of tungsten (W) may be provided. In this case, the step corresponding to the patterning of the conductor film 16 is not necessary, which is particularly effective in the case of a fine layout. When the contact hole is opened to remove the silicide layer 11 and expose the N ⁺ layers 9 and 10, the selective growth method of tungsten (W) is effective.

[0013]

EXAMPLE Two examples in which the present invention is applied to an S / D contact of a MOS FET will be described with reference to the drawings.

First Embodiment FIG. 2 is a diagram for explaining a contact forming method according to the present invention in accordance with each step.

The steps shown in FIGS. 2 (a), 2 (b), 2 (c), and 2 (d) are the same as those in the conventional example shown in FIG.
It is the same as (b), 4 (c) and 4 (d). As shown in Fig. 2 (a), p-type Si
A field oxide film 2 with a thickness of 500 nm is formed on the surface of the substrate 1, and phosphorus (P) ions with an energy of 30 KeV are added to the S / D regions 3 and 4.
Dose was injected with 1x10 ¹³ cm ^-2 N ^- to form a gate oxide film (SiO ₂ film) having a thickness of 10 nm 5, thickness of 300nm thereon
A gate electrode (poly Si film) 6 is formed, and an oxide film (CVD SiO ₂ film) 7 having a thickness of 30 nm is further formed thereon. Next, as shown in Fig. 2 (b), SiO _{2 is formed on} the side surface of the gate electrode 6 by the conventional method.
To form a sidewall 8 with a width of 0.1 μm, and then arsenic (As) is applied to the S / D regions 3 and 4 with an energy of 30 KeV,
Ions are implanted at a dose of 4 x 10 ¹⁵ cm ^-2 to form N ⁺ layers 9 and 10. Next, as shown in Fig. 2 (c), N ⁺ layers 9, 10
Titanium silicide (TiSi ₂ ) about 60 nm deep from the surface of
Layers 11 and 12 are formed by conventional methods. At this time, Fig. 2 (a)
If the SiO ₂ film 7 on the gate electrode of 1 is not formed, a TiSi ₂ layer is also formed on the gate electrode 6 to form a salicide gate. Next, as shown in Fig. 2 (d), the total thickness of 400n
A BPSG film of m was deposited as the interlayer insulating film 13, and the BPSG film 13 and Ti
S / D area opening (contact hole) that penetrates Si ₂ layers 14 and 15 1
4 and 15 are formed to expose the N ⁺ layers 9 and 10. At this time, part of the TiSi layer may remain in the openings 14 and 15 depending on the etching conditions. Next, as shown in Fig. 2 (e), a tungsten silicide film (WSi) 16 with a thickness of 20 nm is again deposited on the entire surface, and P ions are selectively applied to this WSi film 16 with an energy of 15 KeV and a dose amount. Inject ^{1x10 15} cm ^-2 , then 800
Annealing is performed at 20 ° C. for 20 minutes to further increase the concentration of the N ⁺ layers 9 and 10 in contact with the bottoms of the S / D region openings 14 and 15. Finally, as shown in Fig. 2 (f), after removing the WSi film 16, the S / D
To N ⁺ layers 9, 10 contacting the bottoms of the region openings 14, 15, thickness 0.5
μm aluminum (Al) or Al containing Si, Ti, copper (Cu)
The films 17 and 18 are formed for wiring. Also, metal wiring 17,
It is also possible to form a barrier metal such as Ti / TiN or Ti / TiW before forming 18.

The WSi film 16 is formed of another silicide film or poly.
It can be replaced with a conductor layer such as a Si film, an amorphous Si film, or a metal. Second Embodiment FIG. 3 shows a second embodiment of the present invention.
FIG. 8 is a diagram for explaining a contact forming method according to the embodiment of the present invention following each step.

The steps shown in FIGS. 3 (a), 3 (b), 3 (c) and 3 (d) are the same as those of the steps in the first embodiment shown in FIG.
Since it is the same as (a), 2 (b), 2 (c), and 2 (d), the description is omitted.

As shown in FIG. 3 (e), the contact hole 1
A selective CVD (chemical vapor deposition) of W is performed on the surfaces of the N ⁺ layers 9 and 10 exposed at the bottom of the layers 4 and 15 to obtain a thickness of 20 n.
Form W layers 19 and 20 of m 2. Among these W layers 19 and 20, P
1x10 ^{19 to} 1x10 ²⁰ cm ^-3 .

Finally, as shown in FIG. 3 (f), the W layer 19,
Aluminum wiring layers 17 and 18 are formed on 20 respectively. The present invention also holds true for the p-channel MOSFET by replacing the implanted ion species with the present embodiment. Therefore, it can also be applied to CMOSFET circuits.

[0020]

According to the present invention, a shallow and silicide S /
A contact forming method is provided which has good characteristics even in a MOS FET using D and does not reduce the throughput. As a result, it greatly contributes to the miniaturization of semiconductor devices.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a diagram showing a first embodiment.

FIG. 3 is a diagram showing a second embodiment.

FIG. 4 is a diagram showing a conventional example.

[Explanation of symbols]

1, Si substrate 2, field oxide film 3, 4, 33, 34 S / D diffusion layer 5, gate oxide film 6, gate electrode 7, CVD SiO ₂ film 8, sidewall 9, 10, 38 N ⁺ layer 11, 12, 39 TiSi ₂ layer 13 Interlayer insulation film 14, 15, 41, 42 S / D area opening 16, 43 BPSG film 17, 18 AlSi film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 21/336 29/784

Claims (4)

[Claims] 1. A manufacturing method for forming a contact on the surface of a source / drain diffusion layer of a MOSFET, the method comprising: forming a first conductor layer mainly containing metal having a lower resistance than the diffusion layer; An interlayer insulator film is deposited on the first conductor layer, and a contact opening is formed to penetrate the interlayer insulator film and at least a part of the first conductor layer and expose the diffusion layer. And a step of forming a second conductor layer on the diffusion layer exposed in the contact opening, the method for manufacturing a semiconductor device. 2. The second conductor layer is formed by forming a film containing one of a semiconductor and a metal as a main component, and then forming one of the semiconductor and a metal as a main component. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity having the same conductivity type as that of the diffusion layer is introduced into the film by the ion implantation method. 3. The formation of the second conductor layer is performed by forming a film mainly containing one of a semiconductor and a metal on the diffusion layer exposed in the contact opening by selective chemical vapor deposition. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by a growth method. 4. In the film containing one of a semiconductor and a metal as a main component, the semiconductor is selected from polysilicon and amorphous silicon, and the metal is tungsten (W), molybdenum (Mo), 4. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is selected from titanium (Ti), nickel (Ni), palladium (Pa), alloys thereof, and silicides thereof.