JPH0521736A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Objective] The present invention relates to an improved contact in a metal S / D structure MOSFET and a method of manufacturing the same.
At S / D diffusion layer and well contact layer,
The object is to form a good ohmic contact to realize a contact with low contact resistance and to provide a manufacturing method thereof. [Structure] A structure in which a silicide layer is not formed on the surface where the well contact layer and the S / D diffusion layer contact each other, and the well contact layer and the S / D diffusion layer are not directly connected via the silicide layer, A structure in which the silicide layer of the well contact and the silicide layer of the S / D are connected via the wiring layer, and in order to fabricate this structure, the well contact layer and the S / D diffusion layer are crossed once. After forming the silicide layer as described above, the step of removing the silicide layer in the region where the well contact layer and the S / D diffusion layer contact each other, and the wiring layer straddling the region where the silicide layer is removed and the well contact layer and the S / D diffusion layer are removed. / D forming step so as to be in contact with the diffusion layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a metal S / D structure MOSFET.
Regarding improved contact and production method thereof.

Recently, CMOSFET-LOGIC devices have been required to have higher speed and higher capacity. Factors that determine the speed of CMOSFET-LOGIC devices are parasitic capacitance and resistance. Of these, the parasitic resistance is
Most affected by S / D diffusion layer resistance. Therefore, it is absolutely necessary to reduce the S / D diffusion layer resistance.

[0003]

_2. Description of the Related Art A method of forming a low resistance layer containing a metal such as TiSi _{2 on} the surface of a diffusion layer in order to reduce the resistance of the S / D diffusion layer, a so-called metal S / D technique is known.

Further, Japanese Patent Laid-Open No. 60-120571 (Shinichiro Mitani, application, December 5, 1983 (December 5, 1983), published June 28, 1985 (1985))
Discloses a method in which a well contact layer and an S / D diffusion layer are formed in contact with each other, and a metal S / D is formed so as to traverse the surfaces thereof so that only one contact hole is required. Has been done.

FIG. 6 is a diagram for explaining the outline of a conventional process for manufacturing an n-type channel MOSFET (hereinafter referred to as NMOSFET) having the above contacts. As shown in Fig. 6 (a), a p-type well 52 is formed on a p-type Si substrate 51, and the thickness is 400 nm.
A field oxide film 53 and a gate oxide film 54 having a thickness of 10 nm are formed. As shown in FIG. 6B, a gate electrode poly-Si film 55 having a thickness of 120 nm and a CVD SiO ₂ film 56 having a thickness of 20 nm are deposited and patterned to form a gate electrode. As shown in Fig. 6 (c), a side wall 57 is formed on the gate electrode 55, while impurities are introduced to p ⁺ layer (well contact layer) 58 and n ⁺ source for contact of the p-type well 52, respectively. A diffusion layer 59 and a drain diffusion layer 60 are formed. here,
The well contact layer 58 and the source diffusion layer 59 are in lateral contact with each other. As shown in Fig. 6 (d), the TiSi ₂ layer is formed on the surface of the well contact layer 58 and the source diffusion layer 59.
Form 61. As shown in Fig. 6 (e), the thickness is
Deposit BPSG (boro-phosphosilicate glass) of 200nm,
A contact opening 63 for the well contact layer 58 and the source diffusion layer 59, a contact opening 64 for the drain diffusion layer 60,
A contact opening 65 for the gate electrode 55 is provided. Finally, as shown in Fig. 6 (f), the Al wiring 6 with a thickness of 0.5 μm
6, 67 and 68 are formed as contacts for the well contact layer 58 and the n-type source diffusion layer 59, contacts for the drain diffusion layer 60, and contacts for the gate electrode 55, respectively.

[0006]

[Problems to be Solved by the Invention] However, arsenic (As), phosphorus
It is known that the diffusion coefficient of impurities such as (P) and boron (B) is much higher in silicide layers such as TiSi ₂ layers than in Si crystals. For example, the diffusion coefficient of P in WSi is about 50 times that in Si.

As shown in FIG. 6D, a well contact layer 58 and an n-type source diffusion layer 59, which are opposite conductivity type diffusion layers, are formed.
Are connected via the TiSi ₂ layer 61, the p-type impurities from the well contact layer 58 pass through the TiSi ₂ layer 61 to the source diffusion layer 59, and the n-type impurities from the source diffusion layer 59 to the TiSi ₂ layer 61.
Diffuse into the well contact layer 58 through the through holes and cancel the diffused impurities to reduce the surface carrier concentration. As a result, the contact resistance of both the well contact layer 58 and the source diffusion layer 59 increases, sometimes non-ohmic contact occurs, and the leak current between the well contact layer 58 and the source diffusion layer 59 increases. Occur. The conventional contact forming method has the above-mentioned difficulties, and it is an urgent task to solve them.

Therefore, the present invention realizes a contact with low contact resistance by forming a good ohmic contact with respect to the S / D diffusion layer and the well contact layer in a well type MOSFET, and provides a manufacturing method thereof. The purpose is to do.

[0009]

[Means for Solving the Problems] The above problem is to prevent the formation of a silicide layer on the surface where the well contact layer and the S / D diffusion layer contact each other, and
A structure in which the diffusion layer is not connected via a silicide layer,
Furthermore, the structure in which the well contact silicide layer and the S / D silicide layer are connected via the wiring layer, and
In order to fabricate this structure, once the well contact layer and
After the silicide layer is formed so as to straddle the S / D diffusion layer, the step of removing the silicide layer in the region where the well contact layer and the S / D diffusion layer are in contact, and the wiring layer is removed. Well contact layer and S / D
And a step of forming the diffusion layer in contact with the diffusion layer.

[0010]

According to the present invention, as in the conventional case, the impurity atoms in the well contact layer pass through the S / D via the silicide layer.
It does not diffuse into the diffusion layer. On the contrary, the impurity atoms in the S / D diffusion layer do not diffuse into the well contact layer through the silicide layer.

Therefore, it is possible to prevent an increase in contact resistance of the well contact layer and the source diffusion layer and an increase in leak current between the well contact layer and the source diffusion layer.

[0012]

EXAMPLES Examples of the present invention are described below with reference to the drawings.
While explaining. Figure 1 shows a contact structure according to the present invention.
NMOSFET and p-channel MOSFET (hereinafter abbreviated as PMOSFET)
Shows a schematic cross-sectional view of the main part of a CMOSFET consisting of In the figure
Where 1 is the p-type Si substrate and 2 and 3 are the layers formed in the device area.
N-type and p-type wells, 4 are field oxide films (SiO 2₂
 Film), 5 is the gate oxide film (SiO₂Membrane), 6 is the gate electrode, 7 is
CVD SiO₂Membrane, 8 is p⁺Source diffusion layer, 9 is p⁺drain
Diffusion layer, 10 is n⁺Well contact layer, 11 is n⁺Drain
In diffusion layer, 12 is n⁺Source diffusion layer, 13 is p ⁺Well
Contact layer, 14 for sidewall, 15 for TiSi₂Stratum, 19
Is a BPSG film and 26, 27, 28 and 29 are Al wirings.

2 and 3 are schematic views showing steps of a process for manufacturing the CMOSFET shown in FIG. Also, Fig. 4, 5
[FIG. 3] is a plan view showing the arrangement of CMOSFETs of this embodiment.

As shown in FIG. 2 (a), a device region and a field SiO ₂ region 4 are formed on a Si substrate 1 by a normal process, and a p-type well (P well) 3 and a field SiO ₂ region 4 are formed in the device region, respectively.
An n-type well (N well) 2 is formed. In Figure 4 (a),
41 indicates the PMOSFET region and 42 indicates the NMOSFET region. BB 'in the figure,
The cross sections by CC 'are shown in the left and right parts of Fig. 2, respectively.

As shown in FIG. 2B, a gate poly-Si film 6 having a thickness of 120 nm and a S-polysilicon film having a thickness of 30 nm are formed on the gate SiO ₂ film 5 having a thickness of 30 nm.
An iO ₂ film 7 is formed and patterned to form respective gates. The plan view is shown in FIG. 4 (b).

Next, resist patterning is performed to form the source region 8 / drain region 9 of the N well 2 and the well contact layer 13 of the P well 3 by ion implantation. Next, resist patterning is performed again to form the drain region 11 / source region 12 of the P well 3 and the well contact layer 10 of the N well 2 by ion implantation. At this time, the ion implantation conditions are as follows: for n-type impurity ions, the energy is 30 KeV and the dose is 2x10 ¹³ cm ^-2 , and for p-type impurity ions is BF ₂ ⁺ , the energy is 10 KeV and the dose is 1x10. ^{It is 13} cm ^-2 . After that, the entire surface is covered with CVD SiO _2.
A film is formed, and the CVD SiO ₂ film is etched by the RIE method to form a sidewall 14 having a width of 0.1 μm. After that, S / D diffusion layers 8, 9, 11, and 12 are formed again by ion implantation.
The implantation conditions at this time are as follows: BF ₂ ⁺ energy 10 KeV for source region 8 / drain region 9 and dose 2x10 ¹⁵ cm ^-2 for source region 11 / drain region 12 and arsenic energy 10 Ke for source region 11 / drain region 12.
V, dose 4x10 ¹⁵ cm ^-2 Inject. The state thus completed is shown in FIG. 2 (c).

Next, a titanium (Ti) film having a thickness of 35 nm is deposited on the entire surface, and RTA (rapid thermal anneal) is performed at 650 ° C. for 40 seconds.
ing) process. In this treatment, the Ti film on the SiO ₂ film remains in an unreacted state and is then removed by a mixed solution of NH ₄ OH and H ₂ O ₂ . Then, the TiSi layer 15 is formed on the S / D diffusion layers 8, 9, 11, 12 and the well contact layers 10, 13 by performing RTA treatment again at 800 ° C. for 30 seconds. The state thus completed is shown in FIG. 2 (d).

Next, as shown in FIG. 2 (e), the entire thickness is
A 50 nm CVD SiO ₂ film 16 is formed. Next, as shown in Fig. 3 (f), the CVD SiO ₂ film 16 and the TiSi layer 15 are penetrated, and the N well 2
Near the boundary between the drain diffusion layer 9 and the well contact layer 10 of the P well 3, and the source diffusion layer 12 and the well contact layer of the P well 3
Grooves 17 and 18 are formed so that the vicinity of the boundary of 13 is exposed.

Next, as shown in FIG. 3G, BPSG 19 having a thickness of 200 nm is deposited on the entire surface. Next, as shown in Fig. 3 (h), the BPSG film 19 and the CVD SiO ₂ film 16 are penetrated, and on the S diffusion layer 8 of the N well 2 and on the S diffusion layer 11 of the P well 3.
Contact holes 20 and 23 are formed so that the TiSi layer 15 is exposed and penetrates the BPSG film 19, the CVD SiO ₂ film 16 and the SiO ₂ film 7,
Contact hole 2 so that gate poly-Si film 6 is exposed
Form 1, 24. At the same time, the BPSG film 19 and the CVD SiO ₂ film 1
6 and the TiSi layer 15 and contact holes 2 connected to the contact holes 17 and 18 shown in FIG. 3 (f), respectively.
Form 2, 25.

At this time, the diameters of the contact holes 22 and 25 are made larger than the diameters of the contact holes 17 and 18. Finally, as shown in Fig. 3 (i), these contact holes
Al wiring through 20, 21, 22, 23, 24, 25 26, 27, 28, 29
To complete the CMOSFET. The plan view at this time is shown in FIG.
Is shown in.

[0021]

According to the present invention, a MOSFET having a metal S / D structure which prevents contact failure in the well contact portion and generation of a junction leak current between the S / D diffusion layer and the well contact layer, and a method for manufacturing the same are provided. . As a result, it greatly contributes to high speed and high reliability of MOSFET.

[Brief description of drawings]

FIG. 1 is a diagram of a CMOSFET according to the present invention.

FIG. 2 is a diagram of a method for manufacturing a CMOSFET according to the present invention (part 1)

FIG. 3 is a diagram of a method for manufacturing a CMOSFET according to the present invention (No. 2)

FIG. 4 is a plan view of arrangement of CMOSFETs according to the present invention (No. 1)

FIG. 5 is a plan view of a CMOSFET arrangement according to the present invention (No. 2)

FIG. 6 Diagram of conventional MOSFET manufacturing method

[Explanation of symbols]

1, 51 p type Si substrate, 2 n type well 3 p type well 4, 53 field oxide film 5, 54 gate oxide film 6, 55 gate electrode, 7, 16, 57 CVD SiO ₂ film 8 p ⁺ source diffusion layer 9 p ⁺ drain diffusion layer 10 n ⁺ well contact layer 13, 58 p ⁺ well contact layer 11, 60 n ⁺ drain diffusion layer 12, 59 n ⁺ source diffusion layer 15, 61 TiSi ₂ layer 19, 62 BPSG film 17, 18, 20, 21, 22, 23, 24, 25, 63, 64, 65 Opening 26, 27, 28, 29, 66, 67, 68 Al Wiring layer

Claims (2)

[Claims] 1. A first or second conductivity type well is formed in a first conductivity type semiconductor substrate, and a conductivity type channel MOSFET opposite to the conductivity type of the well is formed in the well.
What is claimed is: 1. A semiconductor device comprising a diffusion layer forming a source or a drain of ET and a well contact layer in contact with one of the diffusion layers, and a conductor layer having a resistance lower than that of the diffusion layer. One of the diffusion layers and a conductor layer having a defect on the contact region of the well contact layer, and a well contact layer formed to cover the defect of the conductive layer and contacting one of the diffusion layers and the conductor layer. And a wiring layer in contact with the semiconductor device. 2. A first or second conductivity type well is formed on the surface of the first conductivity type semiconductor substrate, and a conductivity type channel MOSFET opposite to the conductivity type of the well is formed in the well.
On the surface of the well contact layer that contacts one of the diffusion layers that form the source or drain of the MOSFET,
In manufacturing a semiconductor device in which a conductive layer body layer having a resistance lower than that of the diffusion layer is formed, a step of forming a diffusion layer to be a source or a drain in a well formed in a first conductivity type semiconductor substrate, Forming a well contact layer in contact with one of the diffusion layers, forming a conductor layer on the diffusion layer and the well contact layer, and forming a conductor layer on one of the diffusion layers and the well contact layer Removing the conductor layer and exposing one of the diffusion layers and the well contact layer; and forming a wiring layer in contact with one of the exposed diffusion layer, the well contact layer, and the conductor layer. A method of manufacturing a semiconductor device, comprising: