JPH05210440A - Key input method for key input device - Google Patents

Abstract

PURPOSE:To improve efficiency for using a RAM and to realize the method with the simple circuit, with respect to the key input method for a key input device, which detects valid keys by repeatedly scanning a keyboard. CONSTITUTION:In a first process, the state of keys last time is compared with the state of keys this time, and the key counter value of a key changing the state of the key is stored in a first storage region 21 of a RAM 17. In the next second process, a value stored in a second storage region 22 is updated into a value corresponding to the state last time and this time. Further in the third process, the valid key state of the key changing the state is detected from the key counter value stored in the first storage region 21 and the value stored in the second storage region 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key input method for a key input device, and more particularly to a key input method for a key input device for repeatedly scanning a keyboard to detect an effective key.

[0002]

2. Description of the Related Art Conventionally, a key input device having a matrix keyboard has been used in various devices such as a personal computer, a word processor, and a cash register. In these key input devices, detection of a new effective key input when a plurality of keys are pressed multiple times and detection of an effective key input when chattering occurs are roughly performed by the following method.

FIG. 10 is a flow chart showing an example of a memory map of a conventional key input device, and FIG. 11 is a flow chart showing an essential part of an example of a key input method of the conventional key input device.

In the case of a conventional key input device having an 8 × 16 matrix keyboard, a storage area 101 consisting of 8 × 16 storage areas corresponding to a key matrix as shown in FIG. Has a storage area 102 as a data memory on a RAM (Random Access Memory).

In FIG. 11, after the storage area 101 and the data in the storage area are initialized (step 103), the key matrix is scanned (scanned) in step 104, and the state of each key corresponds to the storage area 101. Is written in each address (step 105).

Next, it is judged whether or not the state of each key is a new key input (step 106), and if it is a new key input, the code corresponding to the key is output (step 1).
07) If it is not a new key input, the data stored in the storage area 101 is written in each address of the storage area 102 corresponding to the key matrix as the current key state (step 108). After that, the processing from step 104 onward is repeatedly executed. Here, the process of step 106 is performed as follows.

First, the data of the previous scan and the data of the current scan are compared by taking the exclusive OR of the data at the respective addresses of the storage areas 101 and 102 corresponding to the key matrix. Exclusive OR is 0
If so, the state of the key has not changed, so the data at the next address is compared. If the exclusive OR becomes 1, it indicates that the previous scan data and the current scan data are different, and the state of the key has changed. At this time, since the current scan data becomes a new key input, the logical product of the current scan data and the exclusive OR 1 (that is, the current scan data) is obtained and used as the new key input.

[0008]

However, in order to perform the key input by the above method, the storage area of the data memory needs to have a storage capacity twice as large as the storage capacity corresponding to the key matrix. An arithmetic circuit for obtaining an exclusive OR of data corresponding to the key matrix and an arithmetic circuit for obtaining a logical product are required respectively. For example, 128 for an 8x16 matrix keyboard
A bit (16 bytes) storage capacity is required, and as the number of keys increases, the RAM usage efficiency deteriorates and the circuit becomes complicated.

In view of the above points, it is an object of the present invention to provide a key input method of a key input device which has a high RAM utilization efficiency and can be realized by a simple circuit.

[0010]

The above problems can be solved by constructing according to the principle process chart of FIG.

That is, by scanning a plurality of keys on the keyboard and comparing the state of the previous key and the state of the present key of each of the plurality of keys, the key counter value of the key whose state has changed is set to the first value. The first step 1 of storing in the storage area, and the second step
The value stored in the storage area of is updated to a value according to the previous state and the current state of the key whose state has changed.
And the third step of detecting the valid key state of the key whose state has changed from the key counter value stored in the first storage area and the updated value stored in the second storage area.
And the process 3 of 3).

[0012]

According to the present invention having the above-described structure, the key counter value of the key whose key state has changed in the first step 1 is stored in the first storage area, and then in the second step 2, The value stored in the second storage area is updated to a value according to the previous state and the current state of the key whose state has changed, and further stored in the first storage area in the third step 3. A newly input valid key is detected from the key counter value and the value stored in the second storage area.

[0013]

FIG. 2 is a block diagram of a key input device applied to an embodiment of the present invention. In the figure, the key input device 6 is composed of a microcomputer 7, a keyboard 8 and a buffer circuit 9. To the buffer circuit 9, a device main body (not shown) such as a word processor or a personal computer is connected from the outside.

As shown in FIG. 2, the microcomputer 7 includes an oscillator 13, an interrupt controller 14, and a CPU (Central Processing Unit).
Processing Unit) 15, read-only memory ROM (Rea
d Only Memory) 16, readable / writable memory RAM 1
7, a timer 18, a bus line 19, a bus control unit 10, an input / output port 11, a serial port 12 and the like, which are well-known configurations, and a CP according to a flowchart described later.
A logical operation process is executed by U15.

The microcomputer 7 outputs a scanning signal to the keyboard 8 via the input / output port 11 according to a program stored in the ROM 16 to input a signal indicating ON / OFF of each key. From these signals, a valid key input is detected by a method described later, and a code corresponding to the valid key input is controlled to be output to an external device via the buffer circuit 9.

FIG. 3 is a diagram showing a key matrix of the keyboard 8 shown in FIG. The keyboard 8 is composed of an 8 × 16 key matrix, and scan line I,
A scan signal is applied to II and VIII from the input / output port 11, and the detection lines (1), (2), to (16) are used to input / output port 1.
A detection signal indicating the state of each key is output to 1. As shown in the figure, each key is assigned a key counter value of 1 to 128.

For example, the key counter value of the "A" key is 1, the key counter value of the "C" key is 15, the key counter value of the "H" key is 32, and the key counter value of the "Y" key. Is 127. These key counter values are R
It is given by counting each key of the key matrix by the key counter configured in the AM 17.

FIG. 4 is a block diagram of the RAM 17 which is a main part of the key input device shown in FIG. As shown in the figure, the RAM 17 is composed of an 8-bit memory n bytes composed of B0, B1, B2, B3, B4, B5, B6 and B7, respectively. In the figure,
The third byte is assigned as the key counter 20, and the (n-2) th byte is assigned as the output buffer 23. The detected valid key input code is input to the output buffer 23.

From the a-th byte of RAM 17, (a +
9) The 10 bytes up to the byte are used as the first storage area 21, and the key counter value of the key in which the change in the key data is detected as a result of scanning the key matrix is stored in each of these 1 bytes. The 10 bytes from the bth byte to the (b + 9) th byte are set as the second storage area 22, and when a change in the key data is detected, the value of each 1 byte is updated to a value according to the way of the change. To be done. a and b are integers, and (a + 9) <b. Note that the maximum number of keys that can be simultaneously pressed by the operator of the key input device is 10, and the capacity of each storage area is set to 10 bytes.

FIG. 5 is a flow chart showing the outline of one embodiment of the present invention. In FIG. 5, when the power of the main body of the device such as the word processor is turned on and the power of the key input device is turned on (step 31), first, the RAM 1
The initial state is set by setting all the contents of 7 to "0" (step 32).

Next, the key scan routine (step 33) is executed to scan the key matrix of the keyboard 8 once. And the output buffer 2 of the RAM 17
The code stored in No. 3, that is, the code of the detected valid key is output to the apparatus main body through the input / output port 11 and the buffer circuit 9 (step 34), and after waiting for a certain time (about 10 mSEC) in step 35, the step 33 and subsequent steps are executed, and the code of the effective key detected as the repeated key scan is output.

In the above-mentioned schematic flow chart, the present invention has a salient feature in the key scan routine (step 33), and a specific flow chart of the key scan routine shown in FIG. 6 will be described below.

In FIG. 6, first, the initial state of the key scan is set by setting the value of the key counter 20 to "0" (step 41). Then, a scan signal is output to the scan line (step 42) and key data indicating ON / OFF of the scan line is input (step 43).

At this time, the scan signal is output to one scan line, but initially the scan signal is output to the scan line I by the initial setting and then the scan line I is output.
The key data of each key “A”, ..., “D” is input.
The keyboard 8 is configured so that the output of the key is low level when it is on and high level when it is off, but these key data are inverted and input as high level when it is on, that is, "1".

Next, in step 44 which is the first step, the key counter value of the key whose key data has changed is set in the first storage area 21. The values of each 10 bytes in the first storage area 21 are all set to the initial value "0", but each key is turned off when the device is powered on, and the key is turned on at first. As a result, the key data changes.

That is, when the key is first turned on, the key counter value of the turned-on key is stored in the first storage area 2
It is determined whether there is a change in the key data by referring to each 10-byte value of 1. For example, when the "A" key is first turned on, the key counter value "1" of the "A" key is converted into a binary number and the first byte of the first storage area 21 (RAM1
Stored in the 7th a-byte).

Next, in step 45, which is the second step, the value stored in the second storage area 22 is updated to a value according to the way of changing the key data. As described above, the second storage area 22 is B0, B1, B2, B3, B4, B5, B6, B7.
It consists of 10 bytes of 8-bit memory consisting of B0, B in each of these bytes in step 45.
Bits 1 and B4 are updated according to how the key data changes.

The information stored in these bits B0, B1 and B4 is hereinafter referred to as status information. In the present embodiment, the second
The other bits of the storage area 22 are not used, and the value of the other bits does not change from "0". Further, any 3 bits of 8 bits may be used as the status information.

The values of B0, B1 and B4 of each 10 bytes of the second storage area 22 are set to the initial value "0", but the value of the bit of B4 is turned on at the time of key scanning. It shall be set to "1" at times and to "0" when the key is turned off. Further, it is determined that the values of B0 and B1 are updated as shown in FIG. 7 according to the way the key data changes.

FIG. 7A is a diagram showing a method of updating key status information in the key scan routine of the embodiment of the present invention, and FIG. 7B is a diagram explaining FIG. 7A.

As shown in FIGS. 7A and 7B, when the key-off is detected before the key data change is detected and the key-on is detected in the first key scan, B0 remains "0" and B1 is set to "1". Make 1 ". As shown in, when the key-off is detected before the key data change is detected, the key-on is detected in the first key scan, and the key-on is detected in the second key scan, B1 remains "1" and B1 is also set to "1". ..

As indicated by, when the key data is detected before the key data change is detected, the key-on is detected in the first key scan, and the key-off is detected in the second key scan, B1 is set to "0" together with B0. The key-on is valid and the key-on is invalid.

When the key data is not detected before the key data change is detected, the values of B0 and B1 are "1" as shown in the result. Then, as shown in, when the key-on is detected before the key data change is detected and the key-off is detected in the first key scan, B0 remains "1" and B1 is set to "0".

As shown in, when the key-on is detected before the key data change is detected, the key-off is detected in the first key scan, and the key-off is detected in the second key scan, B1 remains "0" and B0 remains "0". 0 ”.
Further, as shown in, when the key-on is detected before the key data change is detected, the key-off is detected in the first key scan, and the key-on is detected in the second key scan, B0 is set to “0” and B1 is set to “1”. "
The key-off is valid and the key-off is invalid.

FIG. 8 is a diagram for explaining how the status information is updated according to the flowchart of FIG. 8A shows the case where the key-on shown in FIG. 7 is valid, FIG. 8B shows the case where the key-on shown in FIG. 7 is invalid, and FIG. When the key-off shown is valid, the same figure (D)
Shows the case where the key-off shown in FIG. 7 is invalid.

Returning to the flow chart of FIG. 6, which will be described with reference to FIG. 8, when the key-on of “A” is detected in step 44, the first byte (R) of the first storage area 21 is detected.
The key counter value "1" of the key "A" is stored in the a-th byte of AM17). This corresponds to the case where the key-off is detected before the key data change is detected and the key-on is detected in the first key scan.

Therefore, step 45 is executed, and as shown in FIG.
As shown in (A) and (B), when the key is turned on, first, "1" is set in B4 of the first byte of the second storage area 22 (the b byte of RAM 17) (Fig. 8 (A)). b, Fig. 8
After (B) b), B1 is set to "1" while keeping B0 at "0" (Fig. 8 (A) c, Fig. 8 (B) c). After updating the values of status information B0 and B1 in this way, B4 is reset to "0".
(FIG. 8 (A) d, FIG. 8 (B) d).

Next, in step 46 which is the third step, it is checked whether a valid key has been detected. At this time, since B0 is "0" and B1 is "1" and no valid key has been detected, step 47 is skipped and step 48 is executed to increment the key counter value by one.

Then, in step 49, it is checked whether all the states of the respective keys of the scan line have been ticked. Initially, since only the state of the "A" key of the scan line I is checked, the step 44 is entered. Return.

At this time, since the key counter value is advanced by one, the processing up to step 49 is executed for the next key corresponding to this key counter value, that is, the "B" key. Similarly, the state of each key of the scan line I is determined by advancing the key counter value one by one and repeatedly executing the processing from step 44 to step 49.

Then, regarding the key of "D", step 4
As a result of executing the processes up to 9, the ticks of the states of all the keys of the scan line I are completed, so that step 4
After step 9, step 50 is executed to set the output signal of the next scan line, scan line II.
Subsequently, in step 51, it is checked whether or not the scan has been completed for all the scan lines. At this time, since only the scan of the scan line I is completed at first, the process returns to step 42, and the scan signal is output to the scan line II which is the next scan line, and the state of each key of the scan line II is determined.

Further, by repeating the same processing from step 42 to step 51, the state of each key of each scan line is determined. And steps 42 to 5 for scanline VIII
After the execution up to 0, it is determined in the next step 51 that the scanning for all the scan lines is completed. As a result, one scan of all the 8 × 16 key matrix of the keyboard 8 is completed, and the process returns to the main routine shown in FIG. Then, the process proceeds to step 34, and when the valid key is detected as described above, the code of the valid key is output.

At this point, the key counter value of the key whose key data has changed is stored in each byte in the first storage area, and the status information of B0 and B1 of each byte in the second storage area is the key matrix. Is updated and stored with a value according to the change of each key at the time of scanning once.

Further, the key scan routine (step 33) is executed through step 35 of the main routine. As described above, in this step, the key counter value is incremented by one, so that the second scan is performed in a predetermined order according to the key counter value of each key from scan line I to scan line VIII. Is done.

Next, the detection of the state of the "A" key of the scan line I at this time will be described. As described above, when the result key executed in steps 41 to 43 is on, the key data of the key of "A" remains on and remains unchanged, so the key counter value is not set in step 44 and step 45 is executed. To execute.

Then, add "1" to B4 (Fig. 8 (A) e).
After that, as described with reference to FIG. 7, while keeping B1 at “1”, set “1” to BO (FIG. 8 (A) f), and continue to B4.
Is reset to "0" (Fig. 8 (A) g).

As a result, in step 46, the key counter value of the key "A" stored in the first storage area and the status information B stored in the second storage area.
0, B1 value "1", "1" to "A" key "ON"
Is found to be valid, then step 47 is executed and the code representing the "on" of the "A" key is RA.
It is set in the output buffer 23 of M17.

If the "A" key is turned off in the second scan, B4 is "0" in step 45.
Since the status information B4 and B1 are "0" and "1", respectively, it is detected that the ON state during the first scan is invalid. Therefore, the status information becomes as shown in FIG. 8 (8) e, and it is detected that the key of "A" is on.

When the key-off is detected in the first scan shown in FIG. 8C and the key-off is also detected in the second scan, the status information of the second storage area is 1 as described in FIG. Step 45 is executed for the second time, and then FIG.
As shown in (C) b, as a result of executing step 45 the second time, as shown in c in the same figure, it is detected that the key "OFF" is valid.

Furthermore, when the key-off is detected in the first scan and the key-on is detected in the second scan shown in FIG. 8D, the status information of the second storage area is as shown in FIG. As shown in FIG. 8D by executing step 45 for the first time, and as a result of executing step 45 for the second time, as shown in FIG. 8C, it is detected that the key “OFF” is invalid. It

The output buffer 2 detected as described above
The code representing the valid key set to 3 is controlled by the CPU 15 so as to be output from the microcomputer 7 via the bus line 19 and the input / output port 11. Further, the code representing the valid key is supplied to the apparatus main body such as a word processor (not shown) via the buffer circuit 9.

According to the above embodiment, the first storage area,
The storage capacity of each of the second storage areas can be configured with the same number of bytes as the number of keys that the operator can operate while the operator scans the key matrix once, regardless of the size of the key matrix. The usage efficiency of is high. In this embodiment, each storage area is configured with the same number of bytes (10 bytes) as the number of fingers of both hands of the operator.
A smaller storage capacity is possible.

Further, a simple structure can be realized by a microcomputer without requiring a complicated circuit such as an arithmetic circuit for obtaining an exclusive OR or an arithmetic circuit for obtaining a logical product as in the conventional key input device. It is possible to reduce the cost.

In step 47 of the flow chart shown in FIG. 6, the code corresponding to the valid key is set in the output buffer. However, in this embodiment, for the sake of convenience of explanation, the number of output buffers is one. .. If there is only one output buffer, only one valid key code can be inserted in the operation of the above flow chart. If two or more valid keys occur, the code detected as the valid key first appears next. The valid key is ignored because the code detected as the valid key is rewritten, or the code detected as the valid key after the second key does not enter the output buffer.

In order to prevent this, actually, an area of about 16 bytes is usually provided as an output buffer. If the valid key code still does not fit into the output buffer, the status information in the storage area 2 is not changed and the corresponding process is performed by canceling the detection of the valid key.

Further, without depending on the microcomputer,
As shown in FIG. 9, the first key scan signal generation circuit 61,
First key information storage circuit 62, first key status information storage circuit 63, second key scanning signal generation circuit 64, second key information storage circuit 65, second key status information storage circuit 66, key status The key input device 70 including the information updating circuit 67, the new input key detecting circuit 68, and the key code outputting circuit 69 can also save the storage capacity as in the above embodiment. However, in this case, the circuit configuration may be complicated and expensive.

[0057]

As described above, according to the present invention, the key counter value stored in the first memory area in the first step and the second memory area updated in the second step are stored. Since the newly input effective key is detected in the third step from the value, the storage capacities of the first storage area and the second storage area are the number of keys that can be keyed in while scanning the keyboard. The key input device has the features that the storage capacity of each storage area can be reduced and the key input device can be configured at low cost.

[Brief description of drawings]

FIG. 1 is a principle process chart of the present invention.

FIG. 2 is a block diagram of a key input device applied to one embodiment of the present invention.

FIG. 3 is a diagram showing a key matrix of the keyboard shown in FIG.

FIG. 4 is a configuration diagram of a RAM which is a main part of a key input device applied to an embodiment of the present invention.

FIG. 5 is a flowchart showing an outline of an embodiment of the present invention.

FIG. 6 is a detailed flowchart of a key scan routine according to an embodiment of the present invention.

FIG. 7 is a diagram showing a method for updating key status information in a key scan routine according to an embodiment of the present invention, and a diagram for explaining the updating method.

FIG. 8 is a diagram illustrating how the status information is updated according to a specific flowchart of a key scan routine according to an embodiment of the present invention.

FIG. 9 is a block diagram of another embodiment of the present invention.

FIG. 10 is a diagram showing an example of a memory map of a conventional key input device.

FIG. 11 is a flowchart showing a main part of an example of a key input method of a conventional key input device.

[Explanation of symbols]

 1,44 First step 2,45 Second step 3,46 Third step 6 Key input device 8 Keyboard 11 Input / output port 15 CPU (Central Processing Unit) 16 R0M (Read Only Memory) 17 RAM (Random Access) Memory) 20 key counter 21 first storage area 22 second storage area 23 output buffer 33 key scan routine

Claims (1)

[Claims] 1. A key input method for a key input device for repeatedly scanning a plurality of keys of a keyboard to detect an effective key input of the keyboard, wherein the plurality of keys of the keyboard are scanned and each of the plurality of keys is scanned. The first step of storing the key counter value of the key whose state has changed by comparing the previous key state with the current key state in the first storage area, and storing in the second storage area A second step of updating the stored value to a value according to the previous state and the current state of the key whose state has changed, the key counter value stored in the first storage area, and the Thirdly detecting the valid key state of the key whose state has changed from the updated value stored in the second storage area
And a key input method for a key input device.