JPH1139159A - Computer system - Google Patents

Abstract

(57) [Problem] To provide a technique capable of executing a complicated operation at high speed without changing hardware. SOLUTION: Operation means capable of changing the operation contents, rewrite instruction judgment means for judging a rewrite instruction for rewriting the operation contents of the operation means, and use instruction for judging a use instruction for performing an operation using the operation means Determining means for rewriting the operation content of the arithmetic means when the rewriting instruction is determined by the rewriting instruction determining means, and rewriting the arithmetic content when the used instruction is determined by the used instruction determining means And control means for performing calculations using

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for executing a process by changing the operation part of an arithmetic unit by software, and more particularly, to a PLD for executing the processing part of the arithmetic unit
(This relates to a technology that is effective when applied to a programmable computer system.

[0002]

2. Description of the Related Art Generally, a computer system includes a CPU, a storage device, an input device, an output device, and the like, and executes an operation by executing an instruction read from the storage device by the CPU.

The operation part of the CPU is composed of hardware which cannot be rewritten by software, and if the operation part is changed, it is necessary to change the IC and the wiring.
When the CPU executes an operation not provided as a single instruction, a target operation is performed by combining a plurality of instructions of the CPU.

[0004]

The operation part of the CPU of the conventional computer system is constituted by hardware which cannot be rewritten by software. To change the operation part, it is necessary to change the IC and the wiring. For this reason, there is a problem that the circuit of the operation part must be changed when the CPU tries to execute an operation not provided as a single instruction at a high speed.

In a conventional computer system, C
An operation that the PU does not have as a single instruction
In order to execute it, it is necessary to use a combination of instructions of the CPU, and there is a problem that the processing speed is reduced when performing a complicated operation.

An object of the present invention is to solve the above-mentioned problem and to provide a technique capable of executing a complicated operation at high speed without changing hardware.

[0007]

SUMMARY OF THE INVENTION The present invention rewrites the operation contents of an operation means in accordance with the contents of an operation procedure in a program, and executes the operation procedure at high speed by the operation means rewriting the operation contents. It is.

In the computer system according to the present invention, first, an instruction stored in a program memory is read, and the read instruction is a rewrite instruction for rewriting the operation content of an operation means such as a PLD capable of changing the operation content. Whether it is determined by the rewrite instruction determination means.

When the read instruction is a rewrite instruction, the control means executes the rewrite instruction, reads program data for rewriting the arithmetic means, and rewrites the arithmetic means accordingly.

Next, the used instruction determining means checks whether or not the next instruction read from the program memory is a used instruction for performing an operation using the arithmetic means.

If the read instruction is a use instruction, the control means executes the use instruction and performs an operation using the operation means in which the program data has been rewritten.

As described above, the operation means is rewritten by the instruction stored in the program memory, and the operation is performed by the operation means in which the processing content is rewritten. It can be done at high speed by means.

As described above, according to the computer system of the present invention, the operation is performed by rewriting the operation contents of the operation means in accordance with the contents of the operation procedure in the program. The operation can be performed at high speed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, a computer system according to Embodiment 1 in which a part of an operation part is configured by a PLD, and the PLD is rewritten by a specific instruction to execute processing will be described.

FIG. 1 is a diagram showing a schematic configuration of a computer system according to the present embodiment. As shown in FIG. 1, the computer system according to the present embodiment includes a CPU 101 that executes a normal instruction.
A memory controller 102 for controlling access to the program memory 103;
The PLD 104 includes a program memory 103 that stores a program including a PLD use instruction 109 and a PLD 104 that is an operation unit that can change the operation content, and a PLD controller 105 that controls rewriting and operation processing of the PLD 104.

The memory controller 102 includes a CPU 10
1 and a controller that controls access from the PLD controller 105 to the program memory 103.
An LD rewrite instruction determination block 106 and a PLD use instruction determination block 107 are provided.

PLD rewrite instruction determination block 106
Corresponds to a rewrite instruction determining means for determining a PLD rewrite instruction 108 for rewriting the operation content of the PLD 104. The PLD use instruction determination block 107
4 corresponds to a used instruction discriminating means for discriminating the PLD use instruction 109 for performing the operation using the instruction No. 4.

The program memory 103 is a memory for storing a program for performing an arithmetic operation. The program includes a command executed by the CPU 101 and a PLD rewrite command 108 for rewriting the PLD 104 and a PLD rewrite command 108.
A program data for rewriting the LD 104 and a PLD use instruction 109 which is an instruction for using the PLD 104 in which the program data is written are stored.

In FIG. 1, the program data for rewriting the PLD 104 includes a PLD rewrite instruction 10.
8, the program data may exist at a different address from the PLD rewrite instruction 108. For example, when the PLD rewrite instruction 108 is executed, a program for rewriting the PLD 104 is called as a subroutine. It is good.

The PLD 104 is a device that can change the logic by rewriting the program data.
Is a controller that rewrites and controls the calculation.

Here, the PLD 104 corresponds to an arithmetic means capable of changing the operation content, and the PLD rewrite instruction 108 determined by the PLD rewrite instruction determination block 106
Rewrites the operation contents of the PLD 104 by P
PL determined by LD use instruction determination block 107
It corresponds to control means for performing an operation using the PLD 104 in accordance with the D use instruction 109.

FIG. 2 is a flowchart showing a processing procedure of the computer system of the present embodiment. As shown in FIG. 2, the computer system according to the present embodiment reads an instruction in the program memory 103 by the memory controller 102 in step 201, and proceeds to step 202.

In step 202, the PLD rewrite command determination block 106 checks whether the read command is a PLD rewrite command 108. If the read command is a PLD rewrite command 108, the PLD rewrite command
1 is instructed not to execute the instruction.

Next, in step 204, the PLD controller 105 reads the program data for rewriting the PLD 104 existing in the PLD rewrite command 108, and rewrites the PLD 104 according to the program data.

When the rewriting of the PLD 104 is completed, the process proceeds to step 205, where the instruction for not executing the command issued to the CPU 101 is released, and the process returns to step 201.

As a result of examining the contents of the instruction in step 202, the instruction read from the program
If it is not the D rewrite command 108, step 206
Proceed to.

In step 206, the PLD use instruction determination block 107 determines that the read instruction is a PLD use instruction 1
It is checked whether the instruction is 09 or not. If the instruction is a PLD use instruction 109, an instruction not to execute the instruction is issued to the CPU 101 in step 207.

Here, as a precondition, a PLD use instruction 1
Before executing 09, the PLD 104 must be in a state where the operation can be performed. If the PLD 104 is not in a state where the operation can be performed, the PLD 104 is not ready when the PLD use instruction 109 is issued. Error processing to the effect.

In step 208, the PLD controller 10
5 performs the calculation in the PLD 104 when the PLD 104 is in a state where the calculation can be performed normally, and passes the calculation result to the memory controller 102 in step 209.

The memory controller 102 stores the passed operation result in a specific register or a memory address in accordance with the operation content, so that the operation result can be used in the subsequent operation of the CPU 101.

When the storing of the operation result is completed, the process proceeds to step 210, where the instruction for not executing the command issued to the CPU 101 is released, and the process returns to step 201.

As a result of examining the contents of the instruction in step 206, the instruction read from the program
If the instruction is not the D use instruction 109, P
Normal processing without using the LD 104, that is, the CPU 1
The arithmetic processing using 01 is performed, and the process returns to step 201.

As described above, the PLD 104 is rewritten according to the instruction stored in the program memory 103,
By performing the calculation by the PLD 104 instead of the CPU 101, a specific calculation process in the program can be performed at high speed.

In the computer system of this embodiment, P
The LD 104 and the PLD controller 105 are connected to the CPU 101
It is good also as what is built in.

FIG. 3 is a diagram showing another example of the CPU 101 of the present embodiment. As shown in FIG. 3, the CPU of this embodiment
The CPU 101 includes an ALU 300 for performing calculations, a PLD 104, and a PLD controller 105 inside the CPU 101. The PLD controller 105 includes a PLD rewrite instruction determination block 106 and a PLD use instruction determination block 107.

In the example shown in FIG. 3, the PLD rewrite instruction 108 and the PLD
Is rewritten inside the CPU 101, so that the memory controller 102 can read the same instruction as in the related art without being aware of whether the instruction in the program memory 103 is executed by the CPU 101 or the PLD 104. It is.

As described above, according to the computer system of the present embodiment, the operation is performed by rewriting the operation contents of the operation means according to the contents of the operation procedure in the program, so that the hardware is not changed. It is possible to execute complicated calculations at high speed.

(Embodiment 2) A computer system according to Embodiment 2 for executing processing of a specific operation procedure by a PLD will be described below.

FIG. 4 is a diagram showing a schematic configuration of a computer system according to this embodiment. As shown in FIG. 4, the computer system according to the present embodiment includes an operation procedure 40 executed by the PLD 104.
3 includes an operation procedure detection block 401 for detecting the number 3 and an operation procedure conversion block 402 for converting the operation procedure 403 into program data. The other configuration is the same as that shown in the first embodiment.

The program memory 103 includes a PLD 104
A program including an operation procedure 403 to be executed by the program is stored, and the operation procedure 403 includes a plurality of instructions.

Here, the operation procedure 403 executed by the PLD 104 is a processing procedure composed of a series of instructions existing in the form of, for example, a subroutine.

Here, the calculation procedure detection block 401
It corresponds to an operation procedure detecting means for detecting an operation procedure 403 executed by the PLD 104, and is an operation procedure conversion block 402
Corresponds to an operation procedure conversion unit that converts a specific operation procedure 403 into the operation content of the PLD 104.

When the calculation procedure detection block 401 detects the calculation procedure 403, the PLD controller 105 rewrites the PLD 104 with the calculation content converted by the calculation procedure conversion block 402 to perform the calculation of the calculation procedure. Is equivalent to

FIG. 5 is a flowchart showing a processing procedure of the computer system of this embodiment. As shown in FIG. 5, the computer system according to the present embodiment reads an instruction in the program memory 103 by the memory controller 102 in step 501.

In steps 502 and 503, the operation procedure detection block 401 detects the operation procedure 403 to be executed by the PLD 104, and determines whether the read instruction is the instruction of the operation procedure 403. Note that P
The detection of the calculation procedure 403 executed by the LD 104 will be described separately with reference to FIGS.

If the read instruction is an instruction of the operation procedure 403 to be executed by the PLD 104, a normal process without using the PLD 104, that is, an arithmetic process using the CPU 101 is performed in step 504, and
Return to 1.

If the read instruction is the instruction of the operation procedure 403 executed by the PLD 104, the process proceeds to step 505, and it is determined whether the operation procedure 403 is constituted by the PLD 104.

Here, that the operation procedure 403 is constituted by the PLD 104 means that the operation result obtained when the operation procedure 403 is performed by the CPU 101 is the same as the result obtained by the PLD 104 rewritten with specific program data. At one point, the PLD 104 is said to consist of an arithmetic procedure 403.

In step 505, the operation procedure 403 is PLD
As a result of the determination as to whether or not the
If 03 is not composed of the PLD 104, the operation procedure conversion block 402 converts the operation procedure 403 into program data for rewriting the PLD 104 in step 506, and rewrites the PLD 104 in step 507.

Next, in step 508, an instruction not to execute the command is issued to the CPU 101, and in step 509, the P
The operation is performed by the LD 104, and the operation result is passed to the memory controller 102 in step 510.

Then, in step 511, the CPU 10
The instruction for not executing the instruction issued to 1 is released, and the process returns to step 501.

As described above, the operation procedure 403 stored in the program memory 103 is determined, and the
By rewriting the PLD 104 so that it can be executed by the LD 104 and performing the calculation by the PLD 104 instead of the CPU 101, the calculation of the calculation procedure 403 can be performed at high speed.

FIG. 6 is a diagram showing an outline of the calculation procedure detection block 401 of the present embodiment. As shown in FIG. 6, an operation procedure detection block 401 of the present embodiment is a block for detecting an operation procedure 403 composed of a series of instructions, and includes a buffer 601 for storing instructions read from the program memory 103, And a table 602 for storing instructions for comparison with the instructions in the buffer 601.

The table 602 has an area indicating whether the instruction is a continuation of the previous instruction and an area indicating how many times the instruction has been used, and stores a plurality of instructions.

The operation procedure detection block 401 includes an instruction read from the program memory 103 and a table 602.
Are sequentially compared, and if the read instruction and the instruction in the table 602 hit successively (when the comparison result is the same), it is regarded as a series of instructions (for example, a subroutine), Further, when the series of instructions is executed frequently, the series of instructions is
It is determined that the calculation procedure 403 is executed by the LD 104.

FIG. 7 is a flowchart showing a processing procedure of the calculation procedure detection block 401 of the present embodiment. FIG.
As shown in FIG.
Reads the instruction in the program memory 103 by the memory controller 102 in step 701, and stores the read instruction in the buffer 601 in step 702.

In step 703, the instruction comparison between the buffer 601 and the table 602 is performed, and it is determined whether the same instruction as the instruction in the buffer 601 exists in the table 602.

When the instruction comparison is performed, the table 602 is used.
Are compared in the order of the item number. If a hit occurs (if the result of the comparison is the same), the item number is stored, and when the next instruction comparison is performed, the comparison is performed from the item number following the item number. And As described later, it is possible to determine whether or not instructions are continuous by performing the comparison in this manner.

In step 703, the buffer 601
If the same instruction is not in the table 602,
In step 704, the instruction of the buffer 601 is registered in the table 602, and the process returns to step 701.

In step 703, the buffer 601
If the same instruction in table 602 is
In step 705, “1” is added to the count value of the corresponding instruction in the table 602. As will be described later, this count value is used as an index for determining whether or not continuous instructions are determined to be the operation procedure 403.

Next, at step 706, in order to determine whether or not instructions are continuous, the immediately preceding buffer 601 is used.
In the instruction comparison of the table 602, it is determined whether or not a hit has occurred.

If the result of determination in step 706 is that there was no hit in the immediately preceding instruction comparison between the buffer 601 and the table 602, the flow returns to step 701.

If the result of determination in step 706 is that there is a hit in the instruction comparison between the buffer 601 and the table 602 immediately before, the process proceeds to step 707, and in step 703 the table 60 that hits the instruction in the buffer 601 is hit
The corresponding instruction of No. 2 is registered as an instruction following the immediately preceding instruction.

In step 708, the number of instructions registered as a continuation of the immediately preceding instruction is checked, and it is determined whether the continuation of the instruction has been continued to some extent.

If the result of determination in step 708 is that the subsequent registration of instructions is not continuous to some extent, step 701 is executed.
Return to

As a result of the determination in step 708, if the continuous registration of the instructions is continuous to some extent, it is determined that the instructions are a series of instructions such as a subroutine, the flow advances to step 709, and the count value is specified. Is checked to determine whether the series of instructions has been executed a plurality of times.

If the result of determination in step 709 is that the count value is not greater than a specific value, it is determined that the series of instructions is not frequently executed, and the operation procedure 403 is executed.
, And the process returns to step 701.

If the result of determination in step 709 is that the count value is greater than a specific value, it is assumed that the series of instructions is frequently executed, and in step 710, the series of instructions is calculated by the operation procedure 403. Judge.

In the computer system of this embodiment, P
The LD 104 and the PLD controller 105 are connected to the CPU 101
It is good also as what is built in.

FIG. 8 is a diagram showing a schematic configuration when the PLD controller of this embodiment is included in a CPU. As shown in FIG. 8, the PLD controller of this embodiment is connected to a CPU.
In the case where the PLD is included, the PLD 104 and the PLD controller 105 are provided inside the CPU 101, and the PLD controller 105 has a calculation procedure detection block 401 and a calculation procedure conversion block 402.

In the example shown in FIG. 3, since the detection of the operation procedure 403 and the conversion of the operation procedure 403 are performed inside the CPU 101, the memory controller 102 executes the instruction in the program memory 103 by either the CPU 101 or the PLD 104. It is possible to read an instruction similar to the conventional one without being conscious of whether or not the instruction is read.

As described above, according to the computer system of the present embodiment, the operation is performed by rewriting the operation contents of the operation means according to the contents of the operation procedure in the program, so that the hardware is not changed. It is possible to execute complicated calculations at high speed.

[0073]

According to the present invention, since the operation is performed by rewriting the operation contents of the operation means in accordance with the contents of the operation procedure in the program, complicated operations can be executed at high speed without changing hardware. It is possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a computer system according to a first embodiment.

FIG. 2 is a flowchart illustrating a processing procedure of the computer system according to the first embodiment.

FIG. 3 is a diagram illustrating another example of the CPU 101 according to the first embodiment.

FIG. 4 is a diagram illustrating a schematic configuration of a computer system according to a second embodiment.

FIG. 5 is a flowchart illustrating a processing procedure of the computer system according to the second embodiment.

FIG. 6 is a diagram illustrating an outline of a calculation procedure detection block 401 according to the second embodiment.

FIG. 7 is a flowchart illustrating a processing procedure of a calculation procedure detection block 401 according to the second embodiment.

FIG. 8 is a diagram illustrating a schematic configuration when a PLD controller according to a second embodiment is included in a CPU.

[Description of Signs] 101: CPU, 102: Memory controller, 103
... Program memory, 104 ... PLD, 105 ... PLD
Controller: PLD rewrite instruction determination block 106: PLD use instruction determination block 108: P
LD rewrite instruction, 109 ... PLD use instruction, 300 ...
ALU, 401: operation procedure detection block, 402: operation procedure conversion block, 403: operation procedure, 601: buffer, 602: table.

Claims (2)

[Claims] 1. An operation means capable of changing operation contents, a rewrite instruction determining means for determining a rewrite instruction for rewriting the operation contents of the operation means, and a use instruction for performing an operation using the operation means. An instruction discriminating means for rewriting the operation content of the arithmetic means when the rewriting instruction is judged by the rewriting instruction judging means, and rewriting the operation content when the used instruction is judged by the used instruction judging means. Control means for performing calculations using the means. 2. An operation means capable of changing the operation content, an operation procedure detecting means for detecting an operation procedure executed by the operation means, and an operation procedure conversion means for converting a specific operation procedure into the operation content of the operation means. When the calculation procedure is detected by the calculation procedure detection means, the detected calculation procedure is converted into the calculation content of the calculation means by the calculation procedure conversion means, and the calculation means is rewritten by the converted calculation content to rewrite the calculation means. A computer system comprising: control means for calculating the calculation procedure by the calculation means.