JPH05204749A - Memory space allocating circuit - Google Patents

Abstract

PURPOSE:To obtain the memory space allocating circuit which can automatically secure a certain memory area in a certain memory space. CONSTITUTION:This circuit is provided with an address counter 4 to successively output the specified addresses of memory spaces, data counter 5 to successively output specified data and comparator 8 to compare data read from the specified address of the memory space designated by the address counter 4 with the specified data outputted from the data counter and when the comparator 8 shows non-coincidence, the specified data outputted from the data counter 5 are written in the specified address designated by the address counter 4. Therefore, the memory space can be automatically allocated no board holding the same board address exists on the same bus, and the malfunction of a system can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory space allocation circuit, and more particularly to a memory space allocation circuit that can automatically allocate a memory space.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an address allocation circuit of a board itself connected to a bus, in which 100 is a board, and Bus is connected to a data register 3 and a dip The outputs of the switch 1 and the data register 3 are input to the comparator 2, and the comparator 2 sends out a CS (chip select) signal inside the board.

Next, the operation will be described. In Fig. 4, when the board 100 is connected to the Bus, the dip
The switch 1 sets the address of the board itself. Bus
The address accessed from is input to the data register 3. The address of the board itself is accessed from the DIP switch 1, and the address accessed from Bus is
Input from the data register 3 to each comparator 2. The comparator 2 compares the input addresses,
If the addresses are equal, CS to enable the board
Activate the (Chip Select) signal to activate the board.

[0004]

Since the conventional memory space allocation is made by setting the address of the board itself in the DIP switch as described above, if the same B
When a board holding the same address is connected to us, there is a problem that data collides on the bus and the system malfunctions.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to prevent a malfunction of a system by preventing a board holding the same address from existing on the same bus. Aim to get the circuit.

[0006]

A memory space allocation circuit according to the present invention comprises an address counter which is initialized by an initialization signal and sequentially outputs specific addresses of the memory space according to a clock signal, and an initialization signal by the initialization signal. A data counter, which is initialized and sequentially outputs specific data in response to the clock signal, compares the data read from a specific address in the memory space designated by the address counter with the specific data output by the data counter. , A matching means for outputting the coincidence and the non-coincidence, and a data allocating means for writing the specific data output by the data counter to a specific address designated by the address counter when the outputs of the comparing means are non-coincident. By writing specific data to a specific address in a memory space that is It is intended to assign the address.

[0007]

In the present invention, since the specific data is written in the specific address of the unallocated memory space, it is possible to prevent the board holding the same address from existing on the same bus, and the system malfunctions. Can be prevented.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a memory space allocation circuit according to an embodiment of the present invention. The memory space allocation circuit of this embodiment is provided on each board. As shown in the figure, the reference clock signal CLK is input to the clock generator 9, the output Read of the clock generator 9 is input to Bus 11 and the CLK terminal of the delay flip-flop 3, and the output Write of the clock generator 9 is the second. Input to OR gate 2 of
The output CLK1 is input to the first OR gate 1.

The Q output of the delay flip-flop 3 is the first
Is input to the OR gate 1, and the QC output is input to the second OR gate 2. The output of the first OR gate 1 is input to the address counter 4 and the data counter 5. The output of the second OR gate 2 is the board register 10
Entered in. The count value output of the address counter 4 is connected to Bus11. The count value output of the data counter 5 is Bus 11, the comparator 8 and the board.
It is input to the register 10. The data on the Bus 11 is input to the data register 6, and the output of the data register 6 is input to the comparator 8. The output of the comparator 8 is input to the D terminal of the delay flip-flop. The output of the connection detector 7 is input to the address counter 4, the data counter 5, and the data register 6.

Next, the operation will be described. CLK input in FIG. 1, output A of connection detector 7, clock generator 9
Output CLK1, Read, Write, output Compout of comparator 8, output B of first OR gate 1, output C of second OR gate 2, address count value, data count value, and data register value in FIG. Show. FIG. 3 shows a memory space to be allocated. In the memory space, data 00 _H is stored at address 0000 _H , data 10 _H is stored at address 1000 _H , and address 200 is stored.
It is assumed that the data 20 _H is allocated to the address 0 _H and the memory space after the address 3000 _H is unallocated. Since the memory space is not allocated at the address 3000 _H , the data FF _H is stored.

1, 2, and 3, the clock generator 9
Inputs the reference clock CLK as a data input, so that Write, Read, C as shown in FIG.
It is assumed that the LK1 waveform is generated.

When the connection detector 7 detects that the board is connected to the Bus 11, it outputs the A waveform as shown in FIG. This A waveform is for address counter 4, data
The data is input to the counter 5 and the data register 6, whereby the address counter 4, the data counter 5, and the data register 6 are initialized.

The address counter 4 and the data
The counter 5 counts up at the rising edge of the CLK1 waveform, and the data at the address address of the memory space designated by the address counter 4 is read by the data register 6 at the falling edge of the Read waveform. The value of the data counter 5 and the value of the data register 6 are input to the comparator 8, and the comparator 8 compares these values. If they match, the waveform of “L” level is output, and if they do not match, the “H” level waveform is output to C level.
Output as ompout.

The value of the address counter 4 is 3000 _H ,
When the value of the data counter 5 reaches 30 _H , Read
Address 300 in the memory space of FIG.
The data FF _H in the address 0 _H is read by the data register 6, and the Compout waveform continues to output “H” because the values of the data counter 5 and the data register 6 do not match. Then, the delay flip-flop 3 receives the COMPOU input to the D terminal at the falling edge of the Read waveform.
The "H" level output of t is output to the Q output. As a result, the output of the OR gate 1 (B waveform) is always "H", and the count up of the address counter 4 and the data counter 5 is stopped. And the second OR gate 2
When the output (C waveform) is "L", the value 30 _H of the data counter 5 is written to the board register 10 to determine the address of the board itself. Also, the address 3000 in FIG.
Data 30 _H is also written in address _H.

As described above, in this embodiment, the address counter for sequentially designating the specific address of the memory of the host computer, the data counter for sequentially outputting the specific data,
It is provided with a comparator that compares the memory data of the address specified by the address counter with the data output by the data counter, and writes the output data of the data counter at that time to a specific address when the output of the comparator indicates a mismatch, and Since this output data is stored in the board register, the data corresponding to the board address can be automatically assigned to the unallocated address in the memory of the host computer, and the boards connected to the same Bus are the same. Since it does not have the address of, the malfunction of the system can be prevented.

In the above embodiment, the method of changing the address counter value is 0000 _H , 1000 _H , 2000.
_Although the method of changing the data counter value is set to 00 _H , 10 _H , 20 _H , ... so that it becomes _{H 2} , ... Is described, this can be freely set according to the application. It is possible.

[0017]

As described above, according to the present invention, since the memory space is allocated by writing the specific data in the specific address of the memory space which is not allocated, the same address is allocated on the same bus. It is possible to prevent the board that holds the device from existing and prevent the malfunction of the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory space allocation circuit according to an embodiment of the present invention.

FIG. 2 is an output waveform diagram for explaining an operation of the memory space allocation circuit of FIG.

FIG. 3 is a diagram showing a memory space in which memory areas are allocated according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining conventional memory space address allocation.

[Explanation of symbols]

 1, 2 or gate 3 delay flip-flop 4 address counter 5 data counter 6 data register 7 connection detector 8 comparator 9 clock generator 10 board register 11 Bus

Claims (1)

[Claims] 1. A memory space allocation circuit for securing a certain memory area in a certain memory space, wherein the address counter is initialized by an initialization signal and sequentially outputs a specific address of the memory space according to a clock signal. A data counter initialized by the initialization signal and sequentially outputting specific data in response to the clock signal, data read from a specific address of the memory space designated by the address counter, and a specific output by the data counter. Comparing means for comparing the data and outputting the coincidence or non-coincidence, and data allocating means for writing the specific data output by the data counter to a specific address designated by the address counter when the outputs of the comparing means do not coincide And a memory space allocation circuit.