JPH0474736B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing generation circuit, and particularly to a timing generation circuit used in various information processing devices including memories.

In general, it is clear that the generalization of resources, both hardware and software, is industrially beneficial. However, with the recent progress in integrated circuit technology, higher performance of devices, and diversification of specifications, timing generation circuits The generalization of has become an important technological challenge.

In other words, even in information processing equipment that requires multiphase timing signals, as timing generation circuits become more highly integrated, the number of units used within the same model or under the same specification is decreasing, so it is possible to use multiphase timing signals between different models or under different specifications. Common use will become essential.

In this case, due to differences in interfaces and clock speeds due to different models, differences in specifications of timing signal supply destination circuits, and furthermore, due to the trend toward faster circuit operation, conventional means for changing or adjusting timing signals in common use are It tends to become twice as difficult.

A conventional timing generation circuit of this type includes a counter that receives a start signal as an input, counts an externally applied clock, and generates an output signal, a logic circuit that performs a logical operation using the output of the counter as an input, and the counter or The output of the logic circuit is composed of a flip-flop whose output is set by a pulse synchronized with the clock, and a timing signal is obtained as the output of the logic circuit or the flip-flop.

In such a conventional configuration, since the counter or logic circuit and the flip-flop are connected by a conductor such as printed wiring, it is difficult to change the setting of the timing signal, and there is a drawback that the configuration lacks versatility.

An object of the present invention is to provide a versatile timing generation circuit.

The timing generation circuit of the present invention has a holding means that is set by an externally supplied activation signal, a counting means that counts clocks while the holding means is in the set state, and a plurality of addresses each having a plurality of digits. and storage means for reading out the contents of the digits from an address determined by the count value of the counting means and an operation designation signal supplied from the outside; The present invention is characterized in that a timing generating means is provided for generating a timing pulse for each digit position in the means.

Next, the present invention will be explained in detail with reference to the drawings.

A first embodiment showing a first embodiment of the present invention in a block diagram.
In the figure, this embodiment consists of two flip-flops 1 and 5, a 2-bit counter 2, a read-only memory (ROM) 3, a flip-flop group 4, and two AND circuits 6 and 7. , a timing generation circuit that generates timing pulses for a storage device (not shown).
The ROM 3 has an 8 (address) x 7 (digit/address) configuration.

The activation signal STA applied from the outside sets the flip-flop 1 to "1", and as a result, the AND circuit 7 accepts the clock CLK and supplies it to the counter 2. The counter 2 counts the clock CLK while the flip-flop 1 is in the set state of "1" and always outputs the counted value to the ROM 3.

On the other hand, the operation designation signal RWC externally applied to the storage device is also supplied to the AND circuit 6, and is ANDed with the activation signal STA. Flip-flop 5 is set to "0" or "1" in response to this AND result, and the output of flip-flop 5 forms the access address bits for ROM 3 together with the count value of counter 2 (the output of flip-flop 5 is the most significant bit). )
do.

The output of flip-flop 1 is also connected to ROM 3 to be used as the chip enable signal CEN.
Therefore, while the flip-flop 1 is set to the "1" state, the ROM 3 is accessed while sequentially incrementing the address in synchronization with the clock CLK, and the ROM output ROO is read out.

Digit content BIT0~ of this ROM output ROO
BIT5 is 3 delayed clocks (supplied externally) that are synchronized with clock CLK and out of phase.
Together with DC0, DC1 and DC2, the flip-flop group 4 generates timing pulses to be supplied to the memory device for each digit.

These timing pulse signals include an address switching signal ADR for switching between a first address signal and a second address signal that are time-divisionally supplied to the same terminal of a memory IC constituting a storage device, and an address switching signal ADR for strobe of the first address signal. Row address strobe signal RAS, column address strobe signal to strobe the second address signal
CAS, read data strobe signal RDS to strobe the read data read from the memory IC, write data strobe signal to set the write data supplied to the storage device
These include a write enable signal WEN for validating write data to the WDS and memory IC.

In addition, the digit content BIT6 of the ROM output ROO
is used as a reset signal RST for flip-flops 1 and 5 and counter 2.

Figure 2 shows the flip-flop group 4 in Figure 1.
The detailed circuit diagram of flip-flop group 4 is shown in FIG.
D-type flip-flops 12, 13, 14, 2
0, 21, 22, 23, 24 and 25. Digit content BIT2, BIT3 and BIT4
are delayed by delay clock DC2 in D-type flip-flops 12, 13 and 14, respectively (delay ROM output
ROD) is input to the D-type flip-flops 22, 23 and 24, and the remaining digit contents BIT0, BIT1
and BIT5 are D-type flip-flops 20, 21
and 25 directly.

D-type flip-flop 20 is a delay clock DC
1, D-type flip-flops 21 and 25 are delay clock DC2, and D-type flip-flop 2
2, 23, and 24 output their respective inputs in response to the delay clock DC0, respectively, and generate timing signals. That is, digit content BIT0
The waveform generation operation is performed by associating the binary information of ~BIT5 with the height of the timing pulse waveform and determining the timing of its output by delay clocks DC0, DC1, and DC2.

FIG. 3 shows data written in advance in the ROM 3 in FIG. 1, and FIG. 4 shows a waveform diagram when the ROM 3 stores data as shown in FIG. While ROM3 output is “1”,
The ROO or ROD output is set by each clock to output each timing signal, resulting in the timing output shown in FIG. Operation designation signal
When RWC specifies a read operation, the write enable signal WEN of the write strobe signal WDS in FIG. 4 is not output, and
When the operation designation signal RWC designates a write operation, the read strobe signal in FIG.
RDS is not output.

FIG. 5 shows a detailed circuit diagram of the flip-flop group 4 in a second embodiment in which the configuration of only the flip-flop group 4 is changed from the first embodiment shown in FIG. D-type flip-flops 32, 33 and 34 and six JK flip-flops 40 to 4
5, and ROM3 output is “1”
Then, each timing signal is inverted by the ROO output or ROD output.

FIG. 6 shows the second embodiment shown in FIG.
In order to generate the same timing signal as shown in FIG. 4, data to be written in the ROM 3 in advance is shown.

The effect of the first embodiment column and the second embodiment is that since the operation designation signal RWC for the storage device is made part of the access address bits for the ROM 3, different timing signals can be obtained in the same hardware.

FIG. 7 shows that the circuit configuration of only the flip-flop group 4 is changed in the first embodiment shown in FIG. 1, and the changed flip-flop group 4 and the first
A detailed circuit diagram of a flip-flop group 4 in a third embodiment in which flip-flops 1 and 5, counter 2, and AND circuits 6 and 7 shown in the figure are included in an integrated circuit on the same substrate is shown. In this case, flip-flop group 4 consists of 12 D
Type flip-flop 50-55 and 70-75
and six selection circuits 60 to 65.

The D-type flip-flops 50 to 55 delay the digit contents BIT0 to BIT5, respectively, in synchronization with the delay clock DC2, and the selection circuits 60 to 65 externally supply the outputs of the D-type flip-flops 50 to 55 from the digit contents BIT0 to BBIT5, respectively. The selection is made based on the binary information provided. D-type flip-flop 70 has delay clock DC1, D-type flip-flop 71
and 75, a delay clock DC2, and D-type flip-flops 72, 73, and 74 output their respective inputs (outputs of selection circuits 70-75) in response to the delay clock DC0, and generate timing signals.

FIG. 8 shows that in the third embodiment shown in FIG.
A detailed circuit diagram of a flip-flop group 4 in a fourth embodiment is shown, in which the flip-flops 100 to 105 are changed and the other structure is the same as that of the third embodiment.

The first effect of the third embodiment row and the fourth embodiment is similar to the effect of the first embodiment and the second embodiment described above.

The second effect of the third and fourth embodiments is that by providing a circuit that delays the ROM output ROO for every digit and a selection circuit, it is possible to increase the selection width of the timing signal generation pulse using an external terminal. Therefore, even if the timing signal generation circuit is integrated, versatility is not lost.

The effect of the present invention is that by adopting the above configuration, the generated timing signal can be changed over a wide range by changing the data that should be written in advance in the storage means and readjusting the delay clock. Therefore, it is possible to provide a versatile timing generation circuit in which timing signal settings can be easily changed.

Furthermore, the operation designation signal along with the counter output
Since it is configured to be used for addressing storage means such as ROM, it is possible to generate versatile timing for multiple types of operating states.

[Brief explanation of drawings]

1 and 2 show the first embodiment, FIGS. 3 and 4 are diagrams for explaining the operation of the first embodiment, FIG. 5 shows the second embodiment, and FIG. 6 shows the operation of the first embodiment. The figure is a diagram for explaining the operation of the second embodiment, FIG. 7 shows the third embodiment, and FIG. 8 shows the fourth embodiment. 1, 5... Flip-flop, 2... Counter, 3... Read-only memory ROM, 4... Flip-flop group, 6, 7... AND circuit, 12,
13, 14, 20-25, 32, 33, 34, 5
0~55, 70~75, 80~85...D flip-flop, 40~45, 100~105...
JK flip-flop, 60-65, 90-95
...Selection circuit, CLK...Clock, DC0, DC
1, DC2...delay clock, RWC...operation designation signal, STA...start signal, CEN...chip enable signal, RST...reset signal, ROO...
ROM output, ROD...Delayed ROM output, BIT0~
BIT6...Digit content, RAS...Row address strobe signal, ADR...Address switching signal, CAS
………Column address strobe signal, RDS…
...Read strobe signal, WDS...Write strobe signal, WEN...Write enable signal.

Claims (1)

[Claims] 1. Holding means that is set by an externally supplied activation signal; Counting means that counts clocks while the holding means is in the set state; and a plurality of addresses each having a plurality of digits; storage means for reading out the contents of the digits from an address determined by the count value in the counting means and an operation designation signal supplied from the outside; Timing maintenance that reads the storage contents specified by the operation designation signal of the storage means and the counting means within the operation time, stores the information for each digit only for the time specified by the storage contents, and generates a timing signal. 1. A timing generation circuit comprising: means. 2. The timing holding means includes a delay circuit for each digit that delays the contents of each digit, and an output of the delay circuit corresponding to the contents of each digit or the contents of each digit according to a signal supplied from the outside. 2. The timing generation circuit according to claim 1, comprising a selection circuit for selectively outputting the timing pulse, and a flip-flop for outputting the output of the selection circuit as the timing pulse in response to a pulse synchronized with the clock.