JPH05204476A - Regulated power supply circuit - Google Patents

Abstract

PURPOSE:To allow the characteristic of an input power voltage to be a wide band and to have voltage ripple suppression function. CONSTITUTION:A working differential amplifier 12 feeds back an inputted reference voltage Vref supplied to an inverse input terminal via an input terminal 11 and the output of a variable resistance part 14 mentioned later to a nonreverse input terminal. The output of the working differential amplifier 12 supplies the variable resistance part 14 via a current mirror circuit 13. The variable resistance part 14 turns input the voltage VIN supplied via an input terminal 10 into suppressed ripple to output it from the output terminal 15. The other terminal side of the variable resistance part 14 is grounded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-saturation stabilized power supply circuit having a stable voltage ripple suppressing capability over a wide range of frequencies.

[0002]

2. Description of the Related Art A conventional stabilized power supply circuit has, for example, a schematic block circuit configuration shown in FIG. First,
NPN the input voltage V _IN supplied through the input terminal 20
It is supplied to the emitter side of the type transistor TR50 and is supplied to one end side of the resistor R10. The resistor R1
The other end side of 0 is the one end side of the resistor R11 and the reference voltage V _ref.
Is connected to the input terminal 21 for inputting. Further, the reference voltage V _ref is supplied to the inverting input terminal of the error amplifier 22.

The output voltage is supplied from the collector side of the transistor TR50 to the output load 24 via the output terminal 23, and the divided voltage by the resistors R12 and R13 is supplied to the non-inverting input terminal of the error amplifier 22. At this time, the inverting input terminal and the non-inverting input terminal of the error amplifier 22 operate so as to have the same potential, so that the output voltage V _OUT is V _OUT = {(R12 + R13) / R13} · {R11 / ( R10 + R11)} ..... Stabilized in (1).

As described above, in the output voltage feedback control type series regulator which actively suppresses the input power supply voltage ripple and outputs a stable voltage without voltage ripple at the output, the voltage error between the reference voltage and the output voltage is eliminated. A general method is to stabilize the output voltage by amplifying it and controlling the saturation voltage of the field effect transistor FET (or transistor) that is the output stage.

Next, an example of a more specific circuit configuration of the schematic block circuit shown in FIG. 8 is shown in the figure. Here, common parts are given the same reference numerals, and description thereof is omitted. Figure 8
The error amplifier 22 shown in FIG.
The channel field effect transistors TR51 and TR52 form a differential amplifier circuit. The n-channel field effect transistors TR53 and TR54 form a current mirror constant current circuit. In an IC internal circuit, a constant current circuit is often used in such a high resistance portion.

With this configuration, the error amplifier 22 outputs the output signal from the drain side of the field effect transistor TR51 to the p-channel field effect transistor TR5 of the output stage.
It supplies to the gate of 5.

This p-channel field effect transistor T
R55 is the above-mentioned field effect transistors TR51 to T
A power field effect transistor (or transistor) for large power, which is considerably larger than R54, is often used.

[0008]

By the way, since the gate capacitance (or base capacitance) of the field effect transistor TR55 (or transistor) seen from the output of the error amplifier 22 shown in FIG. The frequency of the generated primary pole is several Hz to several hundreds Hz. Since the frequency range in which the input voltage ripple can be actively suppressed is limited to the low frequency range, the input voltage ripple in the frequency range higher than the frequency generated by the primary pole is up to, for example, −40 dB shown in FIG. The effect area A of the active suppression is gradually decreased as the frequency becomes higher. Therefore, a method of passively suppressing the input voltage ripple is used. One of the methods is generally to connect a capacitor to the output side.

In this output voltage feedback control type series regulator, there are two passive methods for stably operating so as not to oscillate. Capacitor C _L connected to the output side
It is shown that when the capacitance of 1 is decreased, the ripple suppression rate can be reduced by 6 dB per octave in the high frequency region C shown in FIG. Also, the point where the zero level of the ripple suppression rate and each suppression characteristic intersect shows the cutoff frequency. This cutoff frequency is shown in FIG.
It is determined by the gate capacitance and the output impedance of the field effect transistor TR55 (or transistor) shown in.

However, as is apparent from FIG. 9, there is a region where the ripple suppression rate is zero. If the capacitance of the capacitor C _L is increased, the cutoff frequency can be moved in the lower frequency direction to reduce the ripple suppression rate zero region. However, even if the capacitance of the capacitor C _L is increased, the frequency region B is increased. _{If the} cutoff frequency is lower than ₁ , it will oscillate.

As a second method, a capacitor C _{L is} further added.
If the capacitance is increased and the cutoff frequency is lowered to be lower than the primary pole, the ripple suppression rate can be reduced in the entire frequency band. However, if the cutoff frequency is in the region B ₂ near the primary pole, the output voltage feedback control type series regulator will oscillate.
The capacitance of the capacitor C _L must be set to a very large capacitance value. This means an increase in the size of the capacitor, which makes it impossible to reduce the size of the stabilized power supply circuit. Further, since the frequency band of the active ripple suppression region becomes very narrow, it becomes impossible to follow and respond to the transient fluctuation of the output load in a short time.

In view of the above situation, the present invention is directed to an output voltage feedback control type series regulator in which a primary pole generated in the circuit is generated even if the capacitance of the capacitor connected to the output side is set small. It is an object of the present invention to provide a stabilized power supply circuit which sets a frequency in a high frequency range to broaden an active ripple suppression characteristic to a wide band and further exerts an effect on a response of a transient output load fluctuation.

[0013]

A stabilized power supply circuit according to the present invention comprises an amplifying means for amplifying an error voltage with respect to a reference voltage, a current amplifying means for current amplifying an output signal from the amplifying means, and the current amplifying means. And output means for outputting an input voltage supplied from an input power source according to the output signal from the means, by feeding back the output signal from the output means to the input side of the amplifying means, Solve.

Here, the amplifying means may suppress the gain of the amplifier of each stage to extend the frequency characteristic, and may obtain a high gain by serially forming multiple stages. The current amplification means performs current amplification using, for example, the configuration of a current mirror circuit. Further, the output means may use a push-pull circuit configuration in which the output signals from the plurality of current amplification means are supplied to one end of the semiconductor elements which are vertically symmetrically combined and driven to output.

[0015]

In the stabilized power supply circuit according to the present invention, for example, a current mirror circuit for amplifying the output signal obtained by amplifying the error voltage with respect to the reference voltage by current amplification is arranged between the output means and the output seen from the amplifying means in the related art. By making the large capacitance of the means appear small, the primary pole generated inside the circuit is moved to the high frequency region, so that the input voltage supplied from the input power source to the output means is stabilized and the output has no ripple. .. Further, the amplification means suppresses the gain of the amplifier at each stage to extend the frequency characteristic, and is serially multistaged to secure a wider frequency region of the active ripple suppression rate. Further, by adopting a push-pull circuit configuration as the output means, the response characteristic and stabilization of the output voltage with respect to the transient fluctuation of the output load is achieved.

[0016]

Embodiments of the stabilized power supply circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block circuit of a first embodiment showing a basic block configuration of a stabilized power supply circuit according to the present invention. The stabilized power supply circuit is a differential error amplifier 12 that is an amplifying unit that amplifies and prints an error voltage with respect to a reference voltage, and a current mirror circuit 13 that is a current amplifying unit that current-amplifies an output signal from the differential error amplifier 12.
And a variable resistance portion 14 which is an output means for stabilizing and outputting an input voltage supplied from an input power source according to an output signal from the current mirror circuit 13.

An input voltage V _IN is supplied to one end of the variable resistance section 14 from the input power source via the input terminal 10. Further, the reference voltage V _ref is supplied to the inverting input terminal side of the differential error amplifier 12 via the input terminal 11. The reference voltage capacitor C _ref is arranged between one end between the input terminal 11 and the inverting input terminal of the differential error amplifier 12 and the ground. The non-inverting input terminal side of the differential error amplifier 12 is fed back with an output signal from a variable resistance section 14 described later.

The output signal of the differential error amplifier 12 is output to the current mirror circuit 13. The current mirror circuit 13 amplifies the current based on the supplied signal and outputs it to the variable resistance section 14. This variable resistance unit 14
It is composed of a field effect transistor (or transistor), a resistor, and the like. Here, as the field effect transistor, a MOS (Metal Oxide Semiconductor) type device is generally used.

Output voltage feedback control type series described above
The primary pole in the regulator has been generated depending on the output impedance of the field effect transistor (or transistor), particularly the gate capacitance (or base capacitance). The method to deal with the occurrence of this primary pole is
There is a method of disposing a large-capacity capacitor C _L on the output side in order to suppress the ripple suppression rate in the entire frequency band well. However, the capacity of the capacitor used is too large to be practical.

By arranging the current mirror circuit 13 between the differential error amplifier 12 and the variable resistance portion 14, the variable resistance portion 1 viewed from the output of the differential error amplifier 12 is provided.
The output impedance of the field effect transistor (or transistor) in 4 can be reduced. As a result, the ripple suppression ratio can be sufficiently suppressed in the entire frequency band even if the capacitance of the capacitor C _L used for this cutoff frequency is reduced without generating a region where the ripple suppression ratio is zero.

The output signal from the variable resistance portion 14 is supplied to a load (not shown) as an output voltage V _OUT via the output terminal 15. The output terminal 16 is a ground terminal.

With such a configuration, by providing a current mirror circuit in the subsequent stage of the differential error amplifier, the output impedance of the field effect transistor (or transistor) for high power viewed from the output of the differential error amplifier. It is possible to improve the ripple suppression rate over the entire frequency band while reducing the capacitance of the capacitor disposed on the output side by reducing the value of.

Next, the broadening of the band of the active ripple suppression rate will be described with reference to the schematic block circuit in the second embodiment shown in FIG. Here, common parts are given the same reference numerals, and description thereof is omitted. In order to widen the band of the active ripple suppression rate, the differential error amplifier 12 uses a plurality of differential error amplifiers and suppresses the gain of the amplifiers in each stage to be used in multiple stages in series. For example, the first stage differential error amplifier 12a shown in FIG. 2 supplies the output to the inverting input terminal and the non-inverting input terminal of the second stage differential error amplifier 12b, respectively. The gain of the differential error amplifier is reduced in order to extend the frequency characteristic of each differential error amplifier. The desired gain is
Thus, it is obtained by connecting a plurality of differential error amplifiers in series.

The ripple suppression characteristic of the actual input voltage is shown in FIG.
Will be described. First of all, the notable points in FIG.
The frequency generated by the primary pole is 150kHz to 200kHz, which is much higher than the conventional frequency of several Hz to several hundreds of Hz. In Fig. 3, the ripple suppression rate is -40 dB.
It is possible to secure the region A that is suppressed to a certain extent over a very wide range. In the frequency range higher than this primary pole, the ripple suppression is reduced. Therefore, the cutoff frequency is set to 1 by the capacitor C _L arranged on the output side.
Set to a frequency lower than the frequency of the next pole to cut off high frequencies.

The smaller the capacitance of the capacitor C _L having this cutoff frequency, the higher the cutoff frequency can be set. However, the region B on the low frequency side from the primary pole shows a region in which oscillation occurs when the cutoff frequency is crossed because the phase rotation becomes large. For this reason, the capacitance of the capacitor C _L is set to a cutoff frequency at a frequency that does not fall in this region B. In this way, the passive ripple suppression region C that reduces −6 dB ripple per octave is set.

With this configuration, the frequency range of the active ripple suppression rate is widened when the power supply voltage is stably supplied, for example, the frequency characteristic of 10 ³ to 10 ⁵ is improved in the order of the conventional case.

Further, description will be given with reference to a schematic block circuit in the third embodiment for ensuring the responsiveness / stability to the fluctuation of the output load shown in FIG. Here, the same parts as those described above are designated by the same reference numerals and the description thereof will be omitted.

The variable resistance section 14 is a semiconductor element in which output signals from the plurality of current mirror circuits 13a and 13b are vertically symmetrically combined in order to improve responsiveness and stability with respect to variations in output load. A push-pull circuit that supplies to the gates of the field effect transistors TR14a and TR14b to drive and output them is configured.

In order to configure the push-pull circuit, for example, the field effect transistor TR14a has a p-channel,
On the other hand, the field effect transistor TR14b uses an n-channel field effect transistor.

In accordance with this push-pull circuit configuration, the current mirror circuit 13 at the preceding stage is also provided with two top-side and bottom-side current mirror circuits 13a and 13b. For this reason, the output of the differential error amplifier 12b at the preceding stage is further supplied to each of the top side and the bottom side.

The relationship between the output load and the output voltage V _OUT is briefly shown in FIG. FIG. 5A shows the magnitude of the output load, and the heavy load is displayed at a high level. 5 shows that the output voltage V _OUT shown in FIG. 5 transiently changes according to the magnitude of the output load shown in FIG. The dotted line shows the conventional response. As shown in the waveform of the output voltage V _OUT in FIG. 5B, for example, the transient response when the load changes from the conventional heavy load to the light load takes a very long time to stabilize. However, the load on each can be reduced by using the push-pull circuit configuration, so that the response can be quickly converged regardless of the load, as shown by the solid line in FIG. 5B. ..

The semiconductor element used in the structure of the push-pull circuit is not limited to the field effect transistor described above, and a transistor may be used. In addition, as shown in the above-described embodiment, for example, as shown in FIG.
The block circuit configured by omitting the differential amplifier 12b having the configuration shown in FIG. 4 and the block circuit configured by omitting the current mirror circuit 13b on the bottom side shown in FIG. 4 can also be independently used. It is clear that the operation of the stable over-power supply circuit, that is, the primary pole can be transited to the high frequency region.

Description will be made with reference to a more specific circuit shown in FIG. 6 based on the above-described schematic block circuit configuration. Here, the same parts as those described above are designated by the same reference numerals and the description thereof will be omitted. An input voltage V _IN = 4.5 V is supplied from the power supply to the stabilized power supply circuit via the input terminal 10. The inverting input terminal of the field effect transistor TR20 in the differential error amplifier 12a at the previous stage is connected to the input terminal 11. By this connection, the inverting input terminal is supplied with the reference voltage V _ref . The inverting input terminal is the gate terminal of the n-channel field effect transistor TR20. Further, the output voltage V _OUT is directly fed back to the non-inverting input terminal of the field effect transistor TR21 in the front stage differential error amplifier 12a.

The reference voltage V _ref shown in FIG.
1 and the resistance R2 and the input voltage V _IN , V _ref = {R2 / (R1 + R2)} · V _IN (2) Actually used resistance R1 = 15kΩ, resistance R2
= 215 kΩ, the reference voltage V _ref is 4.2
It becomes V. The differential error amplifier 12 operates so that the potentials of the inverting input terminal and the non-inverting input terminal become equal.
Therefore, the final output voltage V _OUT is also stabilized at 4.2 V.

The differential error amplifier 12a at the preceding stage constitutes a basic differential error amplifier with the two field effect transistors TR20 and TR21. The differential error amplifier 12a is
The drain sides of the field effect transistors TR22 and TR23 are connected in series by resistors R3 and R4, and the midpoint of both resistors is connected to the gate sides of the field effect transistors TR22 and TR23. Here, the resistor R3 and the resistor R
The resistance value of 4 is made the same to widen the frequency region of the active ripple suppression rate, so that the gain is suppressed.

The drain of the field effect transistor TR22 is connected to the gate of the field effect transistor TR25 on the non-inverting input terminal side of the differential error amplifier 12b in the subsequent stage. The drain of the field effect transistor TR23 is connected to the gate of the field effect transistor TR24 on the inverting input terminal side of the differential error amplifier 12b in the subsequent stage.

The differential error amplifier 12b in the subsequent stage also has the same structure as the differential error amplifier 12a in the preceding stage using four field effect transistors TR24 to TR27. In the differential error amplifier 12b in the subsequent stage, the resistance values of the resistors R5 and R6 arranged between the drain sides of the field effect transistors TR26 and TR27 are, for example, 150 kΩ.
It is set to 100 kΩ and the gain is increased to obtain the desired gain.

The field effect transistors TR37 to T37 are used.
The R48 constitutes a constant current source by a current mirror circuit for the differential error amplifier 12a in the front stage and the differential error amplifier 12b in the rear stage.

The output of the differential error amplifier 12b at the subsequent stage is connected to the field effect transistor TR28 and the field effect transistor TR28 in the two independent current mirror circuits 13a and 13b via the drains of the field effect transistor TR26 and the field effect transistor TR27. It is supplied to the gate of the transistor TR29. With these connections, the field effect transistors TR28 and TR29 are controlled by their respective drain currents.

The current mirror circuit 13a on the top side shown in FIG. 4 includes the field effect transistors TR28 and TR.
Current mirror circuit 13a composed of 30 and TR31
_The current mirror circuit 13a ₂ composed of ₁ and the field effect transistors TR33 to TR35 has a two-stage structure.

The field effect transistor TR28 in the current mirror circuit 13a ₁ is for flowing the same drain current as the drain current flowing in the field effect transistor TR28 into the current mirror circuits of the field effect transistors TR30 and TR31. However,
Since the field-effect transistors TR30 and TR31 form a current mirror circuit with a current amplification ratio of 1:10, the current-mirror circuit 13a ₁ has a field-effect transistor TR31 whose drain current is 10 times that of the field-effect transistor TR30. Will flow.

The drain of the field effect transistor TR31 is connected to the drain of the field effect transistor TR33 forming the current mirror circuit 13a ₂ and the gate of the field effect transistor TR34. Therefore, the field effect transistor TR33 is the field effect transistor TR.
The same drain current as 31 flows. Further, the field effect transistors TR33 and TR35 have a current amplification ratio of 10:
It is a 1000 current mirror circuit. Therefore, the field effect transistor TR35 outputs a current 100 times that of the field effect transistor TR31. Therefore, the current mirror circuit 13a on the top side is
Current mirror circuit 13a ₁ Current mirror circuit 13a
The current amplification factor is 1000-fold by the two-stage configuration of _two.

The bottom-side current mirror circuit 13b shown in FIG. 4 has the field effect transistor TR2.
9, TR32 and TR36. The field effect transistor TR32 is replaced by the field effect transistor TR2.
The same drain current as that flowing in 9 flows.
Since the field-effect transistors TR32 and TR36 form a current mirror circuit having a current amplification ratio of 1: 2, the field-effect transistor TR36 flows twice the drain current of the field-effect transistor TR32.
Therefore, the bottom side current mirror circuit 13b has a current amplification factor of 2 times.

The variable resistance portion 14 corresponds to the field effect transistor TR35 in the current mirror circuit 13a ₂ and can output a large current. This variable resistance unit 1
4, the field effect transistors TR35 and TR36 shown in FIG. 6 form a push-pull circuit. By disposing the field effect transistor TR36 and adopting the push-pull circuit configuration, it is possible to improve the transient response according to the output load variation.

The output of the push-pull circuit using the power field effect transistor for supplying a large amount of power stably outputs the output voltage V _OUT = 4.2 V via the output terminal 15. This output voltage V _OUT is the same as the above-mentioned differential error amplifier 12 in the preceding stage.
It is fed back to the non-inverting input terminal of a.

The field effect transistor TR34 is used.
Is a follower field effect transistor for reducing the mirror capacitance of the gate of the field effect transistor TR35. Further, the constant current source I _ref2 is a load of the field effect transistor TR34.

By disposing the current mirror circuit 13 between the differential error amplifier 12b in the subsequent stage and the variable resistance section 14 in this way, the output from the differential error amplifier 12b in the subsequent stage passes through the electric field transistors TR28 and TR29 in an extremely short time. It can be done with a small size. Therefore, the gate capacitances of the field effect transistors TR28 and TR29 viewed from the output of the differential error amplifier 12b in the latter stage also appear small. As a result, the frequency of the primary pole generated inside the stabilized power supply circuit can be raised to a frequency higher than the conventional frequency. In this way, a low dropout output voltage feedback control type series regulator having a practically small capacitance of the output side capacitor C _L shown in FIG. 6 and having sufficient ripple suppression characteristics over a wide frequency band is realized. can do.

[0049]

As is apparent from the above description, according to the stabilized power supply circuit of the present invention, the amplifying means for amplifying the error voltage with respect to the reference voltage, and the current for amplifying the output signal from the amplifying means with the current. It has an amplifying means and an output means which stabilizes and outputs an input voltage supplied from an input power source according to an output signal from the current amplifying means, and outputs the output signal from the output means to the input side of the amplifying means. To reduce the output impedance of the high-power field-effect transistor (or transistor) seen from the output of the differential error amplifier to reduce the capacitance of the capacitor arranged on the output side, and to reduce the primary pole. It is possible to improve the ripple suppression rate over the entire frequency band to be used by shifting the frequency at which the frequency is generated to a higher frequency direction.

In the amplifying means, the gain of the amplifier at each stage is suppressed to make the amplifier multi-stage in series, so that the frequency of the primary pole generated inside the stabilized power supply circuit is raised to a frequency higher than the above-mentioned frequency. Will be able to.

In the output means, the output signals from the plurality of current amplification means are respectively supplied to one end of the semiconductor elements which are vertically symmetrically combined to drive and output the push-pull circuit. While having a ripple suppression characteristic over a wide band, it is possible to realize excellent response characteristics and stability of the output voltage even in a synergistically diverse transition of the output load.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic block circuit configuration in a first embodiment of a stabilized power supply circuit according to the present invention.

FIG. 2 is a diagram showing a schematic block circuit configuration of a stabilized power supply circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a ripple suppression characteristic with respect to frequency in the circuit configuration shown in FIG.

FIG. 4 is a diagram showing a schematic block circuit configuration of a stabilized power supply circuit according to a third embodiment of the present invention.

5 is a diagram showing a relationship between an output load and an output voltage in the block circuit configuration shown in FIG.

FIG. 6 is a diagram showing a more specific circuit configuration of a stabilized power supply circuit.

FIG. 7 is a schematic block circuit diagram of a conventional stabilized power supply circuit.

FIG. 8 is a diagram showing a more specific circuit in a conventional stabilized power supply circuit.

9 is a diagram showing a ripple suppression characteristic with respect to frequency in the circuit configurations shown in FIGS. 7 and 8. FIG.

[Explanation of symbols]

 10, 11 ... Input terminal 12 ... Differential error amplifier 13 ... Current mirror circuit 14 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Variable resistance part 15, 16 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Output terminal

Claims (3)

[Claims] 1. An amplifying means for amplifying an error voltage with respect to a reference voltage, a current amplifying means for current amplifying an output signal from the amplifying means, and an input power supply according to an output signal from the current amplifying means. A stabilized power supply circuit, comprising: output means for outputting an input voltage, wherein an output signal from the output means is fed back to the input side of the amplification means. 2. The stabilized power supply circuit according to claim 1, wherein in the amplifying means, the gain of the amplifier at each stage is suppressed and the amplifier is serialized in multiple stages. 3. The output means uses a push-pull circuit configuration in which output signals from a plurality of the current amplification means are supplied to one end of semiconductor elements which are vertically symmetrically combined and driven to output. The stabilized power supply circuit according to claim 1, which is characterized in that.