JPH05183694A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To realize a substantial output voltage without any in-block stroke with simple circuit configuration by adjusting a charge transfer time with respect to the dispersion in a capacitance and a resistance caused in each photoelectric converter. CONSTITUTION:This converter is provided with a 1st switch means T extracting sequentially an output signal of plural optical sensors S by one prescribed number as one block. A signal from the 1st switch means T is stored in a 1st storage means CL and the 1st storage means CL and plural optical sensors S are connected by a matrix connection section. Then a signal by one block stored in the 1st storage means CL is extracted by a 2nd switch means USW and stored in a 2nd storage means CT. The crosstalk is prevented by adjusting the ON time of the 2nd switch means USW.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device suitable for use as an input unit for facsimiles, image readers, digital copying machines, electronic blackboards and the like.

[0002]

2. Description of the Related Art The first prior art relating to the first to third photoelectric conversion devices of the present invention will be described below.

In recent years, in order to reduce the size and improve the performance of facsimiles, image readers and the like, a long line sensor having a unity magnification optical system has been developed as a photoelectric conversion device.

Conventionally, this type of line sensor has an integrated circuit (hereinafter referred to as an IC) for signal processing in which a switch element or the like is formed for each photoelectric conversion element arranged in a line in an array. Connected and configured. However, in accordance with the facsimile G3 standard, the number of photoelectric conversion elements required is 1,728 for A4 size. For this reason, the number of mounting steps also increases, and satisfactory manufacturing costs and reliability have not been obtained.

On the other hand, by reducing the number of signal processing ICs,
In addition, as a configuration for reducing the mounting man-hours, a configuration using matrix wiring has been conventionally used.

Further, by adopting a thin film transistor (hereinafter referred to as a TFT) as a switching element and taking an integrated structure including a photoelectric conversion element, a TFT, a matrix wiring, etc., a function of an IC for signal processing can be obtained. Attempts have been made to reduce the cost and provide a high-speed long contact type image reading apparatus at low cost.

Further, in order to reduce the manufacturing cost and provide a highly reliable long contact type image reading apparatus, the photoelectric conversion layer of the photoelectric conversion element and the semiconductor layer of the TFT are made of the same material, for example, amorphous silicon. Formed, photoelectric conversion element, TF
A method of integrally forming T, matrix wiring, and the like on the same substrate using the same manufacturing process has also been developed.

Furthermore, in order to reduce the size and cost,
There is also proposed a photoelectric conversion device in which a photoelectric conversion element directly detects reflected light from an original through a transparent spacer such as glass without using a 1x fiber lens array.

FIG. 20 is an equivalent circuit diagram of the conventional photoelectric conversion device we have previously proposed.

[0010] The optical information incident on the photoelectric conversion elements S _1-1 to S _36-48 are accumulated from the photoelectric conversion elements S _1-1 to S _36-48 capacitor C _S1-1 ~C _S36-48, transferring TFT T _1-1 ~ T
_36-48 and the matrix signal wirings L _{1 to} L ₄₈ to provide parallel voltage outputs. Further, it is converted into a serial signal by the read switch IC and taken out to the outside. The residual charges stored in the storage capacitors C _{S1-1 to} C _S36-48 are reset by the reset TFTs R _{1-1 to} R _36-48 .

Here, the read switch IC includes a transfer switch U _SW1 to a switch between the load capacitances C _{L1 to} C _L48 of the matrix signal wiring section and the read switches T _{SW1 to} T _SW48.
U _SW48 and reading capacitors C _{T1 to} C _T48 are provided,
Further, a reset switch V _SW for resetting the reading capacitors C _{T1 to} C _T48 is provided.

[0012] transfer switch U _SW1 ~U _SW48 is connected to the wiring of the matrix signal wirings L ₁ ~L _48, the load is formed on the matrix signal wirings L ₁ ~L ₄₈ capacitance C _L1 ~
The charge stored in C _L48 is transferred to the reading capacitor C _T1.
˜C _T48 is a switch for transferring, and is simultaneously driven by the transfer pulse G _t .

The read switches T _{SW1 to} T _SW48 are connected to the respective read capacitors, and by sequentially switching them, the potentials of the read capacitors C _{T1 to} C _T48 are sequentially read out to the outside of the photoelectric conversion device via the amplifier Amp. Is a read-out switch, and is sequentially driven by the shift register SR2.

R _{SW1 to} R _SW48 are load capacitors C _{L1 to} C _L48 and transfer switches U formed in the matrix signal wiring section.
_SW1 is provided between the ~U _SW48, the load capacitance C _L1 -C _L48
Is a reset switch for resetting the potential of the reset potential V _R to the reset potential V _R , and is driven by the reset pulse C _res .

Further, V _SW is a reading capacitor C _T1
The potential of -C _T48 is a reset switch for resetting the reset potential V _R, driven by a reset pulse g _res.

In the configuration example of the photoelectric conversion device of the conventional example, photoelectric conversion elements having a total pixel number of 1728 bits are grouped by 48 bits and divided into 36 blocks. Each operation proceeds sequentially in units of this block. FIG. 21 is a timing chart when a document having a uniform image density is read by the conventional photoelectric conversion device.

The photoelectric conversion elements S _{1-1 to} S of the first block
_The optical information incident on _1-48 is stored in the storage capacitors C _S1-1 to C _S1-1.
It is stored as an electric charge in _s1-48 . After a certain period of time, a voltage pulse is applied from the shift register SR ₁ to the first gate drive line G ₁ , and the transfer TFTs T _{1-1 to} T _1-48 are turned on. As a result, the charges of the storage capacitors C _{S1-1 to} C _s1-48 are transferred to the load capacitors C _{L1 to} C _L48 through the matrix signal lines L _{1 to} L ₄₈ . The gate pulse width t ₁ (shown in FIG. 21) required for this transfer is the smaller one of the storage capacitor C _S and the load capacitance C _L and the transfer T.
It depends on the time constant determined by the ON resistance R _t of FTT.

A suitable value is 10 to 20 pF for the storage capacitor C _{S and} 100 to 300 pF for the load capacitance C _L.
Since the N resistance R _t is as high as several MΩ in a TFT using a-Si: H, the time constant is 10 to 40 μs.
It becomes ec.

Then, by applying the gate drive signal G _t ,
The transfer switches U _{SW1 to} U _SW48 are simultaneously turned on, and the signal charges stored in the load capacitors C _{L1 to} C _L48 are simultaneously transferred to the read capacitors C _{T1 to} C _T48 . The length t ₃ (shown in FIG. 21) of the gate pulse G _t necessary for this transfer is the ON resistance Ru of the transfer switch U _SW and the small capacitance values of the load capacitance C _L and the reading capacitor C _T. It depends on the time constant determined by the other value.

The load capacitance C _L is 100 to 300 pF, the read capacitor C _T is 10 to 20 pF, and the ON resistance Ru can be selected to be 3 k to 5 kΩ by using a general analog switch. Constant is 100
It can be a short value of nsec or less.

Subsequently, voltage pulses are sequentially applied from the shift register SR ₂ to the gate drive lines g _{1 to} g ₄₈ , whereby the signal charges of the first block transferred to the read capacitors C _{T1 to} C _T48 are read out. Switch T
_Converted to a serial signal by _{SW1 to} T _SW48 , and the amplifier Amp
Is amplified by and is taken _out as an output voltage V _out to the outside of the photoelectric conversion device.

During the period t ₄ (shown in FIG. 21) during which the signal output for one block is output, the read switch T _{SW is used.}
Although it depends on the ON resistance Rt, the input capacitance including the wiring capacitance of the amplifier Amp, and the response speed of the amplifier, since it can be selected to be 1 to 2 μsec per bit, it becomes about 50 to 100 μsec for 48 bits.

In this read operation, the reset pulse g _res is applied to the reset switch V _SW during the latter half period t ₅ (shown in FIG. 21) of the high voltage (high) voltage pulse applied to g _{1 to} g ₄₈ . It is applied sequentially. As a result, in the latter half period t ₅ , the read switch T _SW and the reset switch V _SW are simultaneously turned on, and the read capacitors C _{T1 to} C _T48 are sequentially reset to the reset potential V _R.

Gate pulse g required for this reset
The length t ₅ of the _res is, the ON resistance Rv of the reset switch V _SW, depends on the time constant determined by the values of the ON resistance Rt and read capacitor C _T of the read switch T _SW, the capacitor C _T for reading 10 to 20 pF is suitable, and if a general-purpose analog switch is used for the ON resistances Rv and Rt, it can be selected to 50 to 300Ω.
This time constant can be set to a short value of 100 nsec or less.

Further, in parallel with this signal reading operation,
Reset pulse C _res is reset switch R _SW1 ~ R
_By applying to _SW48 , the load capacitances C _{L1 to} C _L48 are simultaneously reset.

Gate pulse C required for this reset
The length t _{2 of res} (illustrated in FIG. 21) depends on the time constant determined by the values of the ON resistance Rr of the reset switch R _SW , the resistance of the matrix signal wiring, and the load capacitance C _L , and is several μ.
The value is about sec.

After the reset operation is completed, a voltage pulse is applied to the gate drive wiring G ₂ from the shift register SR ₁ to start the transfer operation of the second block. At the same time as this transfer operation, the reset TFTs _R1-1 to R of the first block
_1-48 is _{turned on} , the charges of the storage capacitors C _{S1-1 to} C _S1-48 of the first block are reset to the reset potential V _R , and the next storage operation is ready. Hereinafter, the gate drive line G
Data for one line is output by sequentially driving ₃ , G ₄ ,.

Next, the second prior art relating to the fourth photoelectric conversion device of the present invention will be described.

FIG. 24 is a circuit diagram of a conventional photoelectric conversion device. However, here, the case of an optical sensor array having nine optical sensors will be taken as an example.

In the figure, optical sensors S11 to S33 are provided.
The three make up one block, and the three blocks make up an optical sensor array. The same applies to the storage capacitors CS11 to CS33 and the switching transistors T11 to T33 corresponding to the optical sensors S11 to S33, respectively.

The individual electrodes having the same order in each block of the photosensors S11 to S33 are connected to the common lines 101 to 1 via the switching transistors T11 to T33, respectively.
It is connected to one of 03.

In detail, the first switching transistors T11, T21, T31 of each block are connected to the common line 1
01 to the second switching transistor T of each block
12, T22, T32 on the common line 102, and the third switching transistors T13, T2 of each block.
3, T33 are respectively connected to the common line 103 (such a connection is called a "matrix connection").

Switching transistors T11 to T33
The gate electrodes of are connected in common for each block, and are connected to the parallel output terminals of the shift register 201 for each block. Therefore, depending on the shift timing of the shift register 201, the switching transistors T11 to T11
T33 is sequentially turned on for each block. Common line 10
1 to 103 are switching transistors TS1 to TS1, respectively.
It is connected to the amplifier 204 via TS3.

Switching transistors R11 to R33
Gate electrodes of the switching transistors T11 to T
Similar to the gate electrode 33, they are commonly connected in each block and are connected to the parallel output terminal of the shift register 202 in each block. Therefore, the shift register 20
With the shift timing of 2, the switching transistors R11 to R33 are sequentially turned on for each block.

Further, in FIG. 24, common lines 101 to 10
3 is installed via load capacitors CL1 to CL3, respectively, and is grounded via switching transistors RS1 to RS3.

The capacitances of the load capacitors CL1 to CL3 are set sufficiently larger than those of the storage capacitors CS11 to CS33. The gate electrodes of the switching transistors RS1 to RS3 are commonly connected and connected to the terminal 104. That is, when the high level is applied to the terminal 104, the switching transistors RS1 to RS3 are simultaneously turned on and the common lines 101 to 103 are grounded.

The portion A surrounded by the dotted line in FIG. 24 is called a parallel-serial conversion section.

Next, the operation of the conventional example having such a configuration will be described with reference to the switching transistors RS1 to R shown in FIG.
This will be described with reference to the timing charts of S3 and R11 to R33. However, FIG. 25 shows the timing when each switching transistor is turned on, but of course, this timing is also the high-level timing output from the shift registers 201, 202, and 203.

First, when light is incident on the photosensors S11 to S33, the power supply 105 causes the capacitor CS to change in intensity.
Electric charges are accumulated in 11 to CS33. Then, first, a high level is output from the first parallel terminal of the shift register 201, and the switching transistors T11 to T13 are turned on (FIG. 25-a).

Switching transistors T11 to T13
Is turned on, the capacitors CS11 to CS1
The charges accumulated in 3 are stored in the capacitor CL1 respectively.
To CL3.

Subsequently, the high level output from the shift register 203 is shifted, and the switching transistors TS1 to TS3 are sequentially turned on (FIG. 25-d.
Figure 25-f).

As a result, the capacitors CL1 to CL3 are
The optical information of the first block transferred and stored in the amplifier 20
The data are sequentially read out through the memory 4. When the information of the first block is read, a high level is applied to the terminal 104, and the switching transistors RS1 to RS3 are simultaneously turned on (FIG. 25-g).

By this operation, the capacitors CL1 to CL are
The residual charge of 3 is completely discharged. Capacitor CL1
When the residual charge of CL3 is completely discharged, the shift register 201 shifts and a high level is output from the second parallel terminal. As a result, the switching transistors T21 to T23 are turned on (FIG. 25-b), and the charges accumulated in the capacitors CS21 to CS23 of the second block are transferred to the capacitors CL1 to CL3.
At the same time, a high level is output from the first parallel terminal of the shift register 202, the switching transistors R11 to R13 are turned on (FIG. 25-h), and the residual charges of the capacitors CS11 to CS13 are completely discharged.

Thus, the capacitor C of the first block
The discharging operation of S11 to CS13 and the transfer operation of transferring the charges accumulated in the capacitors CS21 to CS23 of the second block to the capacitors CL1 to CL3 are performed in parallel. Then, as in the case of the first block, the shift transistors 203 shift to sequentially turn on the switching transistors TS1 to TS3, and the optical information of the second block accumulated in the capacitors CL1 to CL3 is sequentially read (FIG. 25-d to FIG. 25-f).

Similarly, in the case of the third block, the discharging operation of the capacitors CS21 to CS23 of the second block is performed in parallel with the transfer operation (FIG. 25-c) (FIG. 25-).
i) and so on, the above operation is repeated for each block.

[0046]

However, in the matrix-connected photoelectric conversion device according to the first prior art described with reference to FIGS. 20 and 21, even when the amount of charge accumulated by the sensor is the same. The phenomenon that the output voltage varies depending on the charge amount of other bits in the block (hereinafter referred to as intra-block crosstalk) occurs.

In order to consider the change of the output voltage due to the intra-block crosstalk, one block as shown in FIG. 22 consists of 3 bits, and the value of the load capacitance of each bit is C.
Consider a matrix circuit in which the values of L and the capacitance of the cross part are all equal in CP.

Each terminal 1 to 3 of such a matrix circuit
Output voltage V1 when signal charges Q1 to Q3 are input to
V3 is represented by Formula 1.

[0049]

[Equation 1] When the input charge is Q1 = Q2 = Q3 = Q0, the output voltage is

[0050]

[Equation 2] Becomes

When the input charge is Q1 = Q2 = Q3 = 0, V1 = V2 = V3 = 0 is obtained from the equation 1 as well.

However, when the input charge is Q1 = Q0, Q
When 2 = Q3 = 0, V1 = a · Q1 ≠ VO V2 = V3 = b · Q1 ≠ 0, and the output voltage differs even if the input charge amount is the same.

Here, the output voltage Vi of the terminal i in the case where the number of bits in one block is N can be expressed by the following equation 3 based on the equation 1.

[0054]

[Equation 3] When the change in the output voltage due to the intra-block crosstalk is the largest, only one of the N bits has the input charge amount of 0.
Then, the input charge amount of the other (N-1) bits is Q0 (or vice versa). This input charge is 0
If the output voltage of the load capacitance CL of the bit corresponding to is VW0,

[0055]

[Equation 4] Further, when the output voltage of the load capacitance CL of the bit whose input charge amount corresponds to Q0 is VWQ,

[0056]

[Equation 5] Further, using the value of VW0, the intra-block crosstalk amount XCT at the terminal i is defined as follows.

[0057]

[Equation 6] Here, VW is the original output voltage of the terminal i when there is no intra-block crosstalk of the bit corresponding to the input charge amount Q0.

[0058]

[Equation 7] The crosstalk amount XCT also matches the crosstalk amount with respect to the output voltage of CT after the charge is transferred from CL to CT by the transfer switch U _{SW in} FIG. Formula 6
Is as the crosstalk amount XCT in the block approaches 0,
The obtained output approaches the original output voltage value, indicating that there is little change due to intra-block crosstalk.

In the reproduced image using the original reading signal, the intra-block crosstalk is likely to cause a problem when the black original reading signal is increased by the white original reading signal.

Now, let us consider the change over time of intra-block crosstalk in the conventional example shown in FIG. FIG. 23 shows that when the input charge amount of the load capacitance C _L1 is 0 and the input charge amount of the load capacitances C _{L2 to} C _L48 is Q0, the load capacitances C _L1 and C _L2 to C.
_L48 voltages V _CL1 , V _{CL2 to} V _CL48 , and read capacitors C _T1 , C _{T2 to} C _T48 voltages, V _CT1 , V _CT2
~ V _CT48 and the intra-block crosstalk amount XCT are shown over time.

Here, at T = 0, the transfer switch U _SW is turned on.
The read capacitor C _T is 10 pF, the load capacitance C _L is 200 pF, the ON resistance of the transfer switch U _SW is 4 kΩ, and the common resistance R _COM = 10 Ω (where the common resistance R _COM is a parasitic It is a resistance that occurs in a random manner).

Here, T = χ ′ is the time when XCT = 0, and it can be seen that the charge transfer efficiency α from the load capacitance C _L to the read capacitor C _T is about 30% at this timing. Generally, transfer efficiency α is halftone 64
It is considered that 80% or more is required to reproduce gradation levels, and 30% or more is required to reproduce monotone 2 gradation levels. Since it is considered that the transfer efficiency α is required to be 80% or more to reproduce about 64 halftones, it is necessary to use T ≧ χ ° (about 110 nsec) in the conventional example. The inner crosstalk is (VW0 / VW) × 100%.

In order to suppress the change in the output voltage due to such a black stroke in the block, FIG.
As is clear from the figure, the amount of crosstalk in the block XC
It is conceivable to transfer at the time when T = 0, eliminate the cross portion capacitance CP, or increase the ratio between the cross portion capacitance CP and the load capacitance CL. Specific measures against these problems are described in JP-A-62-67864, JP-A-62-67865 and the like.

[0064] However, in these countermeasures, since the block crosstalk amount is dependent on the common ground wiring resistance values of the capacitance value and the load capacitance C _L of the load capacitance C _L, occurs every photoelectric conversion device, the capacity The amount of crosstalk in the block does not become zero due to variations in values and resistance values,
In order to prevent the cross portion capacitance CP from being formed, a shield layer must be separately provided between the wirings, or because the wiring width is narrowed to reduce the cross portion capacitance CP, the manufacturing yield decreases. Increasing the load capacitance CL causes new problems such as a decrease in signal output voltage.

In view of the above problems, the first to third photoelectric conversion devices of the present invention are capable of correcting crosstalk within a block with a simple structure to provide a photoelectric conversion device having excellent signal quality. The purpose is to provide the device at a low price and, eventually, to achieve a low cost of a device to which the device is applied.

In the matrix-connected photoelectric conversion device according to the second conventional technique described with reference to FIGS. 24 and 25, even if the amount of charge accumulated by the sensor is the same, other bits in the block A phenomenon (hereinafter referred to as intra-block crosstalk) in which the output voltage differs depending on the amount of electric charges of

In order to consider the change of the output voltage due to the intra-block crosstalk, one block consists of 3 bits as shown in FIG. 22, the load capacitor value of each bit is CL, and the cross section capacitance value is Consider a matrix circuit in which all CPs are equal.

Each terminal 1 to 3 of such a matrix circuit
Output voltage V1 when signal charges Q1 to Q3 are input to
V3 is represented by the above-mentioned Numerical formula 1.

When the input charge is Q1 = Q2 = Q3 = QO, the output voltage is given by the above-mentioned formula 1 and the above-mentioned formula 2.

When the input charge is Q1 = Q2 = Q3 = 0, similarly, V1 = V2 = V3 = 0 according to the equation (1).

However, if the input charge is Q1 = QO, Q
When 2 = Q3 = 0, V1 = a · Q1 ≠ VO V2 = V3 = b · Q1 ≠ 0, and the output voltage differs even if the input charge amount is the same.

In order to suppress the change in the output voltage due to such intra-block crosstalk, as is apparent from the equation 1, the cross portion capacitance CP is eliminated or the ratio of the cross portion capacitance CP and the load capacitance CL is set. Can be increased. Specific measures against these problems are described in JP-A-62-67864 and JP-A-62-67865.

However, in these measures, a shield layer must be separately provided between the wirings in order to prevent the cross portion capacitance CP from being formed, or the wiring width is narrowed to reduce the cross portion capacitance CP. Therefore, a new problem arises that the manufacturing yield is lowered, or the signal output voltage is lowered by increasing the load capacitance CL.

In view of the above problem, the fourth photoelectric conversion device of the present invention is capable of correcting intra-block crosstalk with a simple structure, thereby providing a photoelectric conversion device with excellent signal quality at low cost. In addition, the purpose is to achieve a low price of equipment to which this is applied.

[0075]

A first photoelectric conversion device according to the present invention comprises at least a plurality of optical sensors, and first switch means for sequentially extracting a fixed number of output signals of the optical sensors as one block. A first storage unit that stores a signal for one block extracted by the first switch unit, a matrix connection unit that connects the first storage unit and the plurality of optical sensors, and the first storage unit. Photoelectric conversion having second switch means for taking out the signal for one block accumulated in the accumulating means and second accumulating means for accumulating the signal for one block taken out by the second switch means. The apparatus is characterized by comprising means for adjusting the on-time of the second switch means.

In the second photoelectric conversion device of the present invention, at least a plurality of optical sensors, first switch means for sequentially extracting a fixed number of output signals of the optical sensors as one block, and the first switch. First accumulation means for accumulating the signal for one block taken out by the means, a matrix connection part for connecting the first accumulation means and the plurality of photosensors, and accumulated in the first accumulation means. A photoelectric conversion device having a second switch means for taking out a signal for one block and a second accumulating means for accumulating a signal for one block taken out by the second switch means. One of the electrodes of one storage means is connected for one block, and is connected to a constant potential through a common resistance sufficiently larger than the ground wiring resistance parasitically generated in the electrode. To.

In the third photoelectric conversion device of the present invention, at least a plurality of optical sensors, first switch means for sequentially extracting a fixed number of output signals of the optical sensors as one block, and the first switch. First accumulation means for accumulating the signal for one block taken out by the means, a matrix connection part for connecting the first accumulation means and the plurality of photosensors, and accumulated in the first accumulation means. A photoelectric conversion device having a second switch means for taking out a signal for one block and a second accumulating means for accumulating a signal for one block taken out by the second switch means. One of the storage means is connected to one block for one block and is connected to a constant potential through a common resistance to adjust the resistance value of the common resistance and the second switch means. Characterized in that a means for adjusting the time.

The fourth photoelectric conversion device of the present invention comprises a plurality of optical sensors, a switch means for sequentially taking out one constant of the output signal of each optical sensor as one block, and one block taken out by the switch means. In a photoelectric conversion device having a storage unit for storing signals, a matrix connection unit connecting the storage unit and the optical sensor, and a signal readout unit for sequentially extracting signals for one block stored in the storage unit, Calculating means for obtaining an average value of the signals of one block accumulated in the accumulating means and multiplying the average value by a constant determined by the configuration of the photoelectric conversion device; and the arithmetic value obtained by the arithmetic means, And differential means for subtracting from each signal of one block.

[0079]

[Operation] In the first photoelectric conversion device of the present invention, the in-block crosstalk amount XCT is made completely zero by adjusting the ON time of the second switch means.

In the second photoelectric conversion device of the present invention, one electrode of the first storage means is connected for one block, and a common resistance sufficiently larger than the parasitic wiring resistance of the electrode is used. By connecting to a constant potential, when the intra-block crosstalk amount XCT becomes 0,
The charge transfer efficiency α from the load capacitance C _L to the read capacitor C _T is 80% or more.

In the third photoelectric conversion device of the present invention, one electrode of the first storage means is connected for one block and is connected to a constant potential through a common resistance, and the resistance value of the common resistance and the second resistance By adjusting the ON time of the switch means, the charge transfer efficiency α from the load capacitance C _L to the read capacitor C _T becomes 80% or more when the in-block crosstalk amount XCT becomes 0. is there.

The fourth photoelectric conversion device of the present invention obtains an average value of signals of one block accumulated in the accumulating means, multiplies the average value by a constant determined by the configuration of the photoelectric conversion device to obtain an operation value, By subtracting this calculated value from each signal of one block, intra-block crosstalk is corrected with a simple configuration.

[0083]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

First, the first photoelectric conversion device of the present invention will be described.

FIG. 1 is an embodiment according to the present invention and shows an equivalent circuit diagram of a photoelectric conversion device. In this embodiment, the photoelectric conversion element section, the storage capacitor section, and the TF formed on the same substrate.
The configuration of the T section, the matrix signal wiring section, the gate drive wiring section, and other photoelectric conversion sections is basically the same as the equivalent circuit diagram of the conventional photoelectric conversion device shown in FIG. 20, and therefore detailed description thereof is omitted.

The photoelectric conversion device of this embodiment differs from the conventional photoelectric conversion device in terms of an equivalent circuit in that the load capacitances C _{L1 to} C _L48.
That is, a multivibrator circuit (shown by a broken line in FIG. 1) for adjusting the transfer pulse width for performing the charge transfer from the read capacitors to the read capacitors C _{T1 to} C _T48 is provided.

The operation of the photoelectric conversion device of this embodiment will be described below, but the description of the elements and the timing for performing the same operation as in the conventional example will be omitted.

First block photoelectric conversion elements S _{1-1 to} S
_The optical information incident on _1-48 is converted into photocurrent and stored in the storage capacitors C _{S1-1 to} C _S1-48 as electric charges. After a certain period of time, the first voltage pulse for transfer is applied to the gate drive line G ₁ for t ₁ hour to switch T _{1-1 to} T _1-48 of the transfer TFT to the ON state. With this, the storage capacitors C _S1-1 ~ C
The charges of _S1-48 are transferred to the load capacitances C _{L1 to} C _L48 through the matrix signal wirings L _{1 to} L _48, and the potentials V _{L1 to} V _L48 of the respective load capacitances become high.

At this time, intra-block crosstalk occurs due to the cross portion capacitance CP of the matrix signal wirings L _{1 to} L ₄₈ .

Then, by applying the gate drive signal G _t ,
The transfer switches U _{SW1 to} U _SW48 are simultaneously turned on, and the signal charges stored in the load capacitors C _{L1 to} C _L48 are simultaneously transferred to the read capacitors C _{T1 to} C _T48 . At this time, the length of the gate drive signal G _t can be changed by adjusting the variable resistance R _X and the variable capacitance C _X in the multivibrator circuit, which will be described in detail later.

At this time, since the ground electrodes of the load capacitors C _{L1 to} C _L48 are all connected, the ground electrode potential V _COM of the bit having the input charge amount of 0 is grounded to the bit of the bit having the input charge amount of Q0. It is the same as the electrode potential. Ground electrode potential V
_{In the COM} , the total input charge of bits whose input charge amount is not zero passes through the transfer switch U _SW and the read capacitor C _T.
It grows bigger at the moment it is transferred to.

At the same time, the potential V _L of the load capacitance C _L of the bit whose input charge amount is zero greatly drops, but the common resistance R
_It takes time to return to the ground potential due to _COM . Therefore, the read capacitor C of the bit whose input charge is zero
_The charge is transferred from _T to the load capacitance C _L, and the potential V _CT of the read capacitor C _{T with} an input charge amount of zero bit decreases and takes a minimum value. As the ground electrode potential V _COM returns to the ground potential, V _CT rises and saturates at a certain value. The time constant at this time is determined by the smaller one of the load capacitance C _L and the read capacitor C _T and the ON resistance of the transfer switch T _SW .

Eventually, VW0 in Equation 4 and load capacitance C _L
And potential determined by the read capacitor C _T

[0094]

[Equation 8] become.

However, the common resistance R _COM and the load capacitance C _L vary somewhat depending on the photoelectric conversion device. The variation of the common resistance R _COM is mainly the variation of the parts, and also includes the variation of the wiring resistance which is parasitically generated. Further, variations in the load capacitance C _L will be described later with reference to FIGS.
It is thought that the main cause is the variation in the film thickness of the first insulating layer 25, the photoconductive semiconductor layer 26, and the ohmic contact layer 27 forming the common capacitor portion 7 shown in FIG.

Thus, the common resistance R _COM and the load capacitance C
Depending on the photoelectric conversion device, the time T during which the intra-block crosstalk becomes zero may differ by about ± 10% due to variations in _L.

In such a case, the variable resistance R _X 91 and the variable capacitance C _{X of} the mono-multivibrator circuit shown in FIG.
By adjusting 92, the intra-block crosstalk of all photoelectric conversion elements can be used at zero. That is, in FIG. 23, by adjusting the variable resistance R _X and the variable capacitance C _X for each photoelectric conversion element, the intra-block crosstalk in which the black signal is increased by the white signal is made zero in all photoelectric conversion devices. You can

As is clear from the above description, according to the present invention, the charge transfer time is adjusted for variations in the resistance value and the capacitance value occurring in each photoelectric conversion device, so that all the photoelectric conversion devices have the same block structure. Crosstalk can be reduced to zero.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross portion capacitance CP is eliminated, or the ratio of the cross portion capacitance CP and the load capacitance CL is increased. The method becomes unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. The signal output voltage drops because CL is increased,
It does not occur.

Further, according to the present invention, the original output voltage can be obtained even if the load capacitance CL is made small as long as the transfer efficiency can be secured. Therefore, by reducing the load capacitance CL as much as possible in circuit formation, As is clear from Equation 7, a large output voltage can be obtained with a small amount of input charge.

This means that it is possible to reduce the amount of charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or a state where the amount of incident light is small, that is, the light source for illuminating the original has low brightness. In this state, the photoelectric conversion device can be used at a low cost.

2 and 3 are a schematic cross-sectional view and a plan view of the photoelectric conversion portion of the photoelectric conversion device of this embodiment.

In this embodiment, the photoelectric conversion element section 1, the storage capacitor section 2, the TFT sections 3 and 4, the matrix signal wiring section 5, the gate drive wiring section 6, the common capacitor section 7, etc. are used by using a-Si: H. Are integrally formed on the translucent insulating substrate 10 by the same process.

On the translucent insulating substrate 10, a first conductor layer 24 of Al, Cr or the like, a first insulating layer 25 of SiN or the like,
Photoconductive semiconductor layer 26 made of a-Si: H, n ⁺ type a
-Si: H ohmic contact layer 27, Al, Cr
And the second conductor layer 28 is formed.

In the photoelectric conversion element section 1, 30 and 3
Reference numeral 1 is an upper layer electrode wiring. The signal light L'reflected by the original P changes the conductivity of the photoconductive semiconductor layer 26 made of a-Si: H, and the upper electrode wirings 30 facing each other in a comb shape,
The current flowing between 31 is changed. Reference numeral 32 denotes a metal light-shielding layer, which is connected to an appropriate driving source to connect the main electrode 30.
It may be a control electrode (gate electrode) facing (source electrode or drain electrode) and 31 (drain electrode or source electrode).

The storage capacitor section 2 includes a lower layer electrode wiring 33.
A first insulating layer 25, a photoconductive semiconductor layer 26, and a photoconductive semiconductor layer 26 formed on the lower electrode wiring 33.
The upper electrode wiring 31 of the photoelectric conversion element unit 1 formed on the upper wiring is continuous with the wiring. The structure of the storage capacitor section 2 is a so-called MIS capacitor structure. Although both positive and negative bias conditions can be used, stable capacitance and frequency characteristics can be obtained by using the lower layer electrode wiring 33 in a state where it is always biased negatively.

The TFT parts 3 and 4 are composed of the lower electrode wiring 34 which is a gate electrode and the second insulating layer 2 which is a gate insulating layer.
5, the semiconductor layer 26, and the upper layer electrode wiring 3 as the source electrode
5 and the upper electrode wiring 36, which is a drain electrode, and the like.

In the matrix signal wiring portion 5, the individual signal wiring 22 made of the first conductive layer, the insulating layer 25 covering the individual signal wiring 22, the semiconductor layer 26, the ohmic contact layer 27, and the individual signal are formed on the substrate 10. A common signal wiring 37 made of a second conductive layer is sequentially laminated so as to intersect the wiring. 38 is an individual signal wiring 22 and a common signal wiring 37
And 39 is a ground wire for the storage capacitor unit 2.

In the wiring portion 6 of the gate line for driving the TFT, the individual gate wiring 40 formed of the first conductive layer 24 on the substrate 10, the insulating layer 25 covering the individual gate wiring 40, the semiconductor layer 26, the ohmic contact layer. 27, and a common gate wiring 41 composed of the second conductive layer 28 is sequentially stacked so as to intersect the individual gate wiring 40. Reference numeral 42 is a contact hole for making ohmic contact between the individual gate wiring 40 and the common gate wiring 41.

The common capacitor section 7 includes a lower electrode wiring 22 which is an individual signal wiring, a first insulating layer 25 formed on the lower electrode wiring 22, a photoconductive semiconductor layer 26, and a photoconductive semiconductor layer 26. It is composed of the upper layer electrode wiring 43 formed of the second conductive layer 28 formed above. The structure of the common capacitor section 7 is the same as that of the storage capacitor section 2 of the MIS capacitor. The bias condition may be positive or negative, but stable capacitance and frequency characteristics can be obtained by using the upper electrode wiring 43 in a state where it is always positively biased.

As described above, the photoelectric conversion device of this embodiment is
Since the photoelectric conversion element section, the storage capacitor section, the TFT section, the matrix signal wiring section, the gate drive wiring section, and the common capacitor section all have a laminated structure of a photoconductive semiconductor layer, an insulating layer, a conductor layer, etc. Simultaneous formation by the same process.

Further, on the second conductive layer 28, a passivation layer 11 made of SiN or the like and a manuscript P are mainly provided for protection and stabilization of the semiconductor layer surfaces of the photoelectric conversion element section 1 and the TFT sections 3 and 4. A friction resistant layer 8 made of microsheet glass or the like is formed to protect the photoelectric conversion element and the like from friction.

Between the passivation layer 11 and the abrasion resistant layer 8, an antistatic layer 15 made of a transparent conductive layer is formed.

The antistatic layer 15 is composed of the original P and the abrasion resistant layer 8.
It is arranged in order to prevent the static electricity generated by the friction with the photoelectric conversion element and the like from being adversely affected. As the material of the static electricity countermeasure layer 15, it is necessary to transmit the illumination light L and the signal light L ′, and therefore an oxide semiconductor transparent conductive film such as ITO is used.

In this embodiment, the anti-wear layer having the antistatic layer formed thereon is adhered onto the passivation layer 11 by an adhesive layer.

FIG. 4 shows an example of a sensor unit constituted by a photoelectric conversion device according to the present embodiment and a circuit pattern substrate on which a light source for illuminating a document is mounted, and a flexible cable connecting the photoelectric conversion device and the circuit pattern substrate. FIG. 3 is a schematic configuration diagram showing a state where the photoelectric conversion device and the circuit pattern substrate do not face each other.

Here, 10 is a sensor substrate constituting a photoelectric conversion portion, and 72 and 82 are a drive switch IC and a read switch IC, respectively.

The output signal obtained by the photoelectric conversion portion is taken out from the sensor substrate 10 through the bonding wire 71, the read switch IC 82, the flexible cable 80, the signal input connector 78, the circuit pattern substrate 75 and the signal output connector 79. Also GND
Each power source including the power source is supplied to the sensor substrate 10, each IC and the circuit pattern substrate 75 through a path opposite to the output signal.

The 5V power supply and the GND power supply necessary for the multivibrator circuit for adjusting the transfer pulse width for transferring the charge from the load capacitances C _{L1 to} C _L48 to the read capacitors C _{T1 to} C _T48 are also the same. To the signal output connector 79. In this embodiment, the variable resistor R _X 91 and the variable capacitor C _X 92 forming the multivibrator circuit may be arranged anywhere between the read switch IC 92 and the signal output connector 79.
In the above, the wiring pattern is arranged on the circuit pattern substrate 75.

FIG. 5 shows B when cutting FIG. 4 along the line AA '.
It is sectional drawing seen. The difference from FIG. 4 is that the photoelectric conversion device and the circuit pattern substrate 75 are arranged so as to face each other, and are in a form at the time of actual driving.

In this embodiment, a photoelectric conversion device for directly detecting the reflected light from the original without using a fiber lens array of the same size, that is, a so-called perfect contact type structure is adopted.
A system such as a facsimile can be made very compact, and the degree of freedom in designing a mechanism for constructing the system is increasing.

Needless to say, it can also be used in a contact-reading type image reading apparatus using a 1 × fiber lens or the like.

FIG. 6 is a schematic configuration diagram showing an example of a facsimile having a communication function as an image information processing apparatus configured by using the sensor unit according to this embodiment.

Here, 402 is a feeding roller as a feeding means for feeding the document P toward the reading position, and 403.
Is a light source, and 404 is a separating piece for surely separating and feeding the originals P one by one. A platen roller 406 is provided at a reading position with respect to the sensor unit 400, regulates a surface to be read of the document P, and serves as a transport unit that transports the document P.

In the illustrated example, PP is a recording medium in the form of a roll paper, and the image information read by the sensor unit 400 or the image information transmitted from the outside in the case of a facsimile machine or the like is reproduced here. Reference numeral 410 denotes a recording head as a recording means for performing the image formation, and various types such as a thermal head and an inkjet recording head can be used. The recording head may be a serial type or a line type. Reference numeral 412 is a platen roller as a conveying unit that conveys the recording medium PP to the recording position of the recording head 410 and regulates the recording surface thereof.

An operation panel 420 is provided with a switch for accepting an operation input as an input / output means, a message, and a display section for notifying the state of the apparatus. Reference numeral 430 denotes a system control board as a control unit, which is provided with a control unit (controller) that controls each unit, a drive circuit (driver) for the photoelectric conversion element, a processing unit (processor) for image information, a transmission / reception unit, and the like. 440 is the power supply of the device.

Recording means used in the information processing apparatus is, for example, US Pat. Nos. 4,723,129 and 4740796.
It is preferable that the specification discloses the typical configuration and principle thereof. According to this method, at least one of the electrothermal converters arranged corresponding to the sheet or liquid path holding the liquid (ink) gives a rapid temperature rise corresponding to the recorded information and exceeding the nucleate boiling. By applying a drive signal, heat energy is generated in the electrothermal converter, causing film boiling on the heat-acting surface of the recording head, and as a result, bubbles in the liquid (ink) that correspond one-to-one to this drive signal. Is effective because it can form By the growth and contraction of the bubbles, liquid (ink) is ejected through the ejection opening,
Form at least one drop.

Further, as a full line type recording head having a length corresponding to the width of the maximum recording medium which can be recorded by the recording apparatus, by combining a plurality of recording heads as disclosed in the above-mentioned specification, Either a structure that satisfies the length or a structure as one recording head integrally formed may be used.

In addition, the ink is attached to the replaceable chip type recording head, or the recording head itself, which can be electrically connected to the apparatus main body and can supply ink from the apparatus main body by being attached to the apparatus main body. The present invention is also effective when a cartridge-type recording head provided integrally with a tank is used.

Next, the second photoelectric conversion device of the present invention will be described.

FIG. 7 shows a first embodiment according to the present invention,
The equivalent circuit diagram of a photoelectric conversion apparatus is shown. In the first embodiment, the structure of the photoelectric conversion element portion, the storage capacitor portion, the TFT portion, the matrix signal wiring portion, the gate drive wiring portion, etc. formed on the same substrate is the same as that of the conventional photoelectric conversion portion shown in FIG. Since it is basically the same as the equivalent circuit diagram of the photoelectric conversion device, detailed description of the configuration is omitted.

The photoelectric conversion device of the first embodiment differs from the conventional photoelectric conversion device in terms of an equivalent circuit in that the load capacitances C _L1 to
One common constant potential electrode (hereinafter, referred to as a ground electrode) of C _L48 has a common resistance R _COM ″ (here, the common resistance R _COM ″ is a parasitic common resistance R _COM and a newly added common resistance R _COM). 'Means a combined resistance) and is grounded.

The operation of the photoelectric conversion device of the first embodiment will be described below, but the description of the elements and the timing for performing the same operation as in the conventional example will be omitted.

The photoelectric conversion elements S _{1-1 to} S of the first block
_The optical information incident on _1-48 is converted into photocurrent and stored in the storage capacitors C _{S1-1 to} C _S1-48 as electric charges. After a certain period of time, the first voltage pulse for transfer is applied to the gate drive line G ₁ for t ₁ hour to switch T _{1-1 to} T _1-48 of the transfer TFT to the ON state. With this, the storage capacitors C _S1-1 ~ C
The charges of _S1-48 are transferred to the load capacitances C _{L1 to} C _L48 through the matrix signal wirings L _{1 to} L _48, and the potentials V _{L1 to} V _L48 of the respective load capacitances become high.

At this time, intra-block cross talk occurs due to the cross section capacitance CP of the matrix signal wirings L _{1 to} L ₄₈ .

Then, by applying the gate drive signal G _t ,
The transfer switches U _{SW1 to} U _SW48 are simultaneously turned on, and the signal charges stored in the load capacitors C _{L1 to} C _L48 are simultaneously transferred to the read capacitors C _{T1 to} C _T48 .

At this time, since the ground electrodes of the load capacitors C _{L1 to} C _L48 are all connected, the ground electrode potential V _COM of the bit having an input charge amount of 0 is equal to the ground electrode of the bit having an input charge amount of Q0. It is the same as the electric potential. The ground electrode potential V _COM is
The total input charge of a bit whose input charge amount is not zero is increased at the moment when it is transferred to the reading capacitor C _T through the transfer switch U _SW .

At the same time, the potential V _L of the load capacitance C _L of the bit whose input charge amount is zero also drops significantly, but the common resistance R
_It takes time to return to the ground potential due to _COM ″. Therefore, the read capacitor C of the bit whose input charge is zero
_The charge is transferred from _T to the load capacitance C _L, and the potential V _CT of the read capacitor C _{T with} an input charge amount of zero bit decreases and takes a minimum value. As the ground electrode potential V _COM returns to the ground potential, V _CT rises and saturates at a certain value. The time constant at this time is determined by the smaller one of the load capacitance C _L and the read capacitor C _T and the ON resistance of the transfer switch T _SW .

Eventually, VW0 in Equation 4 and load capacitance C _L
And the potential of the above-mentioned formula 8 determined by the read capacitor C _T.

The above operation will be described with reference to FIG. FIG. 8 is a diagram similar to FIG. 23. The read capacitor C _T is 10 pF, the load capacitance C _L is 200 pF, and the ON resistance of the transfer switch U _SW is 4 kΩ, which is the same as FIG. Further, the common resistance R _COM ″ is simulated as 25Ω.

[0141] According to FIG. 8, the potential V _CT1 of input charge amount zero at a 1-bit read capacitor C _T1, decreases from V _R, rising eventually are further increased becomes V _R. Where T = χ ″ (T≈110 nsec) is XCT =
Although the time is 0, the load capacitance C
_It can be seen that the charge transfer efficiency α from _L to the read capacitor C _T is about 80%. The value of χ ″ is C _L · R
Since it depends on _COM ″, C _L · R _COM ″ ≧ 200 pF × 25Ω = 5.
It may be 0 × 10 ⁻⁹ F · Ω.

In FIG. 8, by turning on the transfer switch T _SW from T = 0 to T = χ ″, the intra-block crosstalk in which the black signal is increased by the white signal can be made zero. ..

Another simulation result will be described with reference to FIG. FIG. 9 is a diagram similar to FIG. 23, and the input charge amount of each bit and the resistance value and capacitance value of each element are shown in FIG.
Is the same as. The common resistance R _COM ″ is simulated as 70Ω. That is, C _L · R _COM ″ = 2
This is the case of 00 pF × 70 Ω = 1.4 × 10 ⁻⁸ F · Ω. At the timing of T = χ when the crosstalk amount XCT = 0, the transfer efficiency α similar to FIG. 23 is about 85%.

Therefore, in FIG. 9, by turning on the transfer switch T _SW from T = 0 to T = χ, the intra-block crosstalk in which the black signal is increased by the white signal can be made zero. ..

As is clear from the above description, according to the present invention, the original output voltage without any intra-block crosstalk in which the black signal is increased by the white signal can be obtained with a simple circuit configuration.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross portion capacitance CP is eliminated, or the ratio of the cross portion capacitance CP and the load capacitance CL is increased. The method becomes unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. The signal output voltage drops because CL is increased,
It does not occur.

Further, according to the present invention, since the original output voltage can be obtained even when the load capacitance CL is made small, it is apparent from the formula 7 by reducing the load capacitance CL as much as possible in forming a circuit. Thus, a large output voltage can be obtained with a small amount of input charge.

This means that it is possible to reduce the amount of charge generated by the photosensor, and it is possible to use a photosensor having a low sensitivity, or a state where the amount of incident light is small, that is, the light source for illuminating the original has low brightness. In this state, the photoelectric conversion device can be used at a low cost.

The structure of the photoelectric conversion portion of the photoelectric conversion device of the first embodiment is the same as the structure of the embodiment of the first photoelectric conversion device of the present invention already described with reference to FIGS. 2 and 3. Therefore, the explanation is omitted here.

Strictly speaking, in the configuration of the first embodiment, the load capacitances C _{L1 to} C _L48 shown in FIG. 7 are stray capacitances and the common capacitor section 7 formed between the antistatic layer 15 and the common signal line 37. And a capacitance (hereinafter referred to as C _gs ) formed between the lower layer electrode wiring 34 serving as the gate electrode in the TFT section 3 and the upper layer electrode wiring 35 connected to the individual signal wiring 22.
It consists of three parts.

In an A4 size photoelectric conversion device that is actually available as a product, the above-mentioned load capacitance configuration example when 1728 photoelectric conversion elements are divided into 36 blocks by 48 bits using matrix connection is as follows: The stray capacitance in the common signal wiring is about 10 to 20 pF, the common capacitor section is 100 to 300 pF, and the C _GS in the TFT section is about 2
It is 0 to 40 pF.

In such an example of the photoelectric conversion device, by inserting the element R _COM ′ having a common resistance of about 20 to 100Ω into the ground wiring part of the common capacitor part, the common resistance R
The value of _COM ″ can be set to a value sufficiently larger than the parasitic resistance R _COM , and it is possible to drive with sufficient transfer efficiency and zero crosstalk in the block.

FIG. 10 is a sensor unit composed of a photoelectric conversion device according to the first embodiment and a circuit pattern substrate on which a light source for illuminating an original is mounted, and a flexible cable connecting the photoelectric conversion device and the circuit pattern substrate. It is a schematic block diagram which shows an example of a photoelectric conversion device and a circuit pattern substrate in the state which does not oppose.

Here, 10 is a sensor substrate constituting a photoelectric conversion portion, and 72 and 82 are a drive switch IC and a read switch IC, respectively.

The output signal obtained by the photoelectric conversion portion is taken out from the sensor substrate 10 through the bonding wire 71, the read switch IC 82, the flexible cable 80, the signal input connector 78, the circuit pattern substrate 75 and the signal output connector 79. Also GND
Each power source including the power source is supplied to the sensor substrate 10, each IC, and the circuit pattern 75 through a path opposite to the output signal.

In the first embodiment, the added common resistance R _COM ′ may be arranged anywhere in the ground wiring of the common capacitor section 7, but in FIG.
_COM 'has a chip resistor or the like made of ceramic or the like arranged on the wiring portion on the circuit pattern substrate 75. Further, as shown in FIG. 10, when the ground wiring passes through the inside of the read switch 82, it is possible to form a resistance element inside the IC. Further, when the ground wiring passes through the flexible cable 80 or the like as shown in FIG. 10, it is possible to dispose the resistance element on the flexible cable.

By using a common resistor R _COM ′ as a variable resistor, it is possible to adjust variations in wiring resistance and the like in each sensor unit, and it is also possible to completely eliminate intra-block crosstalk for each sensor unit. Becomes

FIG. 11 is a sectional view taken along the line B-B of FIG. 10 taken along the line AA '. The difference from FIG. 10 is that the photoelectric conversion device and the circuit pattern substrate 75 are arranged so as to face each other, and are in a form at the time of actual driving.

In the first embodiment, a system such as a facsimile is provided by adopting a photoelectric conversion device for directly detecting the reflected light from the original without using a unit fiber lens array or the like, that is, a so-called perfect contact type structure. It is possible to make it extremely compact, and the degree of freedom in mechanical design in constructing the system is increased.

Needless to say, it can also be used in a contact-reading type image reading apparatus using a 1x fiber lens or the like.

As an example of a facsimile having a communication function as an image information processing apparatus configured by using the sensor unit according to this embodiment, there is a configuration similar to that shown in FIG. Since the facsimile structure has already been described, the description is omitted here.

Next, a second embodiment will be described. Since the second embodiment is similar to the equivalent circuit diagram of the photoelectric conversion device of the first embodiment shown in FIG. 7, detailed description of the configuration will be omitted.

The photoelectric conversion device according to the second embodiment differs from the photoelectric conversion device according to the first embodiment in that the load capacitance CL is small and the common resistance R _COM ″ is large.

The operation of the second embodiment will be described with reference to FIG. FIG. 12 is a view similar to FIGS. 23, 8 and 9, the read capacitor C _T is 10 pF, and the ON resistance of the transfer switch U _SW is 4 kΩ, which is the same as FIGS. 23, 8 and 9. Here, the common resistance R _COM ″ is 1k
Ω, the load capacitance C _L is 75 pF, and the configuration is such that the stray capacitance in the common signal wiring is 20 pF, the common capacitor section is 15 pF, and the C _gs in the TFT section is 40 pF.
As can be seen from FIG. 12, even if the load capacitance C _L is reduced,
By increasing the common resistance R _COM ″, it becomes possible to reduce the intra-block crosstalk to zero at time T = 100 to 200 nsec. Specifically, time T = 180.
At nsec, the crosstalk in the block is almost zero,
The transfer efficiency α at that time reaches about 93%.

As described above, by reducing the load capacitance CL in circuit formation, it is possible to obtain a large output voltage with a small amount of input charge, as is apparent from the equation (7). This means that it is possible to reduce the amount of electric charge generated by the optical sensor, and a low-sensitivity optical sensor can be used, or a state where the incident light amount is small, that is, a state in which the light source for illuminating the original has low brightness However, the photoelectric conversion device can be used at low cost.

Others are the same as those in the first embodiment.

Next, the third photoelectric conversion device of the present invention will be described.

FIG. 13 is a first embodiment according to the present invention and shows an equivalent circuit diagram of a photoelectric conversion device. In the first embodiment, the structure of the photoelectric conversion element portion, the storage capacitor portion, the TFT portion, the matrix signal wiring portion, the gate drive wiring portion, etc. formed on the same substrate is the same as that of the conventional photoelectric conversion portion shown in FIG. Since it is basically the same as the equivalent circuit diagram of the photoelectric conversion device, detailed description of the configuration is omitted.

The photoelectric conversion device of the first embodiment differs from the conventional photoelectric conversion device in terms of equivalent circuit in that the load capacitances C _L1 to C _L1 .
One common constant potential electrode (hereinafter, referred to as a ground electrode) of C _L48 has a common resistance R _COM ″ (here, the common resistance R _COM ″ is a parasitic common resistance R _COM and a newly added common resistance R _COM). ( _Which means a combined resistance with the ′), and a multi-function for adjusting the transfer pulse width for performing charge transfer from the load capacitors C _{L1 to} C _L48 to the read capacitors C _{T1 to} C _T48 for each photoelectric conversion device. That is, a vibrator circuit is provided.

The operation of the photoelectric conversion device of the first embodiment will be described below, but the description of the elements and the timing for performing the same operation as in the conventional example will be omitted.

The photoelectric conversion elements S _{1-1 to} S of the first block
_The optical information incident on _1-48 is converted into photocurrent and stored in the storage capacitors C _{S1-1 to} C _S1-48 as electric charges. After a certain period of time, the first voltage pulse for transfer is applied to the gate drive line G ₁ for t ₁ hour to switch T _{1-1 to} T _1-48 of the transfer TFT to the ON state. With this, the storage capacitors C _S1-1 ~ C
The charges of _S1-48 are transferred to the load capacitances C _{L1 to} C _L48 through the matrix signal wirings L _{1 to} L _48, and the potentials V _{L1 to} V _L48 of the respective load capacitances become high.

At this time, in-block crosstalk occurs due to the cross portion capacitance CP of the matrix signal wirings L _{1 to} L ₄₈ .

Then, by applying the gate drive signal G _t ,
The transfer switches U _{SW1 to} U _SW48 are simultaneously turned on, and the signal charges stored in the load capacitors C _{L1 to} C _L48 are simultaneously transferred to the read capacitors C _{T1 to} C _T48 . At this time, the length of the gate drive signal G _t can be changed by adjusting the variable resistance R _X and the variable capacitance C _X in the multivibrator circuit, which will be described in detail later.

At this time, since the ground electrodes of the load capacitors C _{L1 to} C _L48 are all connected, the ground electrode potential V _COM of the bit having the input charge amount of 0 is the ground voltage of the bit having the input charge amount of Q0. It is the same as the electrode potential. Ground electrode potential V
_{In the COM} , the total input charge of bits whose input charge amount is not zero passes through the transfer switch U _SW and the read capacitor C _T.
It grows bigger at the moment it is transferred to.

At the same time, the potential V _L of the load capacitance C _L of the bit whose input charge amount is zero also drops significantly, but the common resistance R
_It takes time to return to the ground potential due to _COM ″. Therefore, the read capacitor C of the bit whose input charge is zero
_The charge is transferred from _T to the load capacitance C _L, and the potential V _CT of the read capacitor C _{T with} an input charge amount of zero bit decreases and takes a minimum value. As the ground electrode potential V _COM returns to the ground potential, V _CT rises and saturates at a certain value. The time constant at this time is determined by the smaller one of the load capacitance C _L and the read capacitor C _T and the ON resistance of the transfer switch T _SW .

Eventually, VW0 in Equation 4 and the load capacitance C _L
And the potential of the above-mentioned formula 8 determined by the read capacitor C _T.

The above operation will be described with reference to FIG. FIG. 8 is a diagram similar to FIG. 23. The read capacitor C _T is 10 pF, the load capacitance C _L is 200 pF, and the ON resistance of the transfer switch U _SW is 4 kΩ, which is the same as FIG. Further, the common resistance R _COM ″ is simulated as 25Ω.

[0178] According to FIG. 8, the potential V _CT1 of input charge amount zero at a 1-bit read capacitor C _T1, decreases from V _R, rising eventually are further increased becomes V _R. Where T = χ ″ (T≈110 nsec) is XCT =
Although the time is 0, the load capacitance C
_It can be seen that the charge transfer efficiency α from _L to the read capacitor C _T is about 80%. The value of χ ″ is C _L · R
Since it depends on _COM ″, C _L · R _COM ″ ≧ 200 pF × 25Ω = 5.
It may be 0 × 10 ⁻⁹ F · Ω.

In FIG. 8, by turning on the transfer switch T _SW from T = 0 to T = χ ″, the intra-block crosstalk in which the black signal is increased by the white signal can be made zero. ..

However, the common resistance R _COM ″ and the load capacitance C _L vary somewhat depending on the photoelectric conversion device. The variation of the common resistance R _COM ″ is mainly due to the variation of parts and other parasitic wiring. Resistance variations are included. The variation in the load capacitance C _L is thought to be mainly caused by the variation in the film thickness of the first insulating layer 25, the photoconductive semiconductor layer 26 and the ohmic contact layer 27 forming the common capacitor section 7 shown in FIGS. Be done.

As described above, the time T at which the intra-block crosstalk becomes zero may differ by about ± 10% depending on the photoelectric conversion device due to variations in the common resistance R _COM ″ and the load capacitance C _L.

Therefore, in such a case, the resistance of the common resistance is adjusted by newly inserting the common resistance element R _COM ′ into the ground wiring portion of the common capacitor portion, and the monomulti circuit shown in FIG. Variable resistance R of vibrator circuit
By adjusting _X 91 and the variable capacitance C _X 92, it is possible to use zero in-block crosstalk of all photoelectric conversion elements.

Another simulation result will be described with reference to FIG. FIG. 9 is a diagram similar to FIG. 23, and the input charge amount of each bit and the resistance value and capacitance value of each element are shown in FIG.
Is the same as. The common resistance R _COM ″ is simulated as 70Ω. That is, C _L · R _COM ″ = 2
This is the case of 00 pF × 70 Ω = 1.4 × 10 ⁻⁸ F · Ω. At the timing of T = χ when the crosstalk amount XCT = 0, the transfer efficiency α similar to FIG. 23 is about 85%.

Therefore, in FIG. 9, from T = 0 to T = χ, the transfer switch T _SW is turned on, the resistance of the common resistance R _COM ″ is further adjusted, and the variable resistance R for each photoelectric conversion element is adjusted.
By adjusting _X and the variable capacitance C _X , the intra-block crosstalk in which the black signal is increased by the white signal can be made zero.

As is clear from the above description, according to the present invention, the original output voltage without any intra-block crosstalk in which the black signal is increased by the white signal can be obtained with a simple circuit configuration. Further, even with respect to variations in the resistance value and the capacitance value that occur among photoelectric conversion devices, it is possible to reduce the intra-block crosstalk in all photoelectric conversion devices by adjusting the charge transfer time.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross section capacitance CP is eliminated, or the ratio of the cross section capacitance CP and the load capacitance CL is increased. The method becomes unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. The signal output voltage drops because CL is increased,
It does not occur.

Further, according to the present invention, since the original output voltage can be obtained even when the load capacitance CL is made small, it is clear from the formula 7 by reducing the load capacitance CL as much as possible in forming a circuit. Thus, a large output voltage can be obtained with a small amount of input charge.

This means that it is possible to reduce the amount of charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or when the amount of incident light is small, that is, the light source for illuminating the original has low brightness. In this state, the photoelectric conversion device can be used at a low cost.

Since the structure of the photoelectric conversion portion of the photoelectric conversion device of this embodiment is the same as the structure of the first photoelectric conversion device of the present invention described above with reference to FIGS. 2 and 3, the description here is omitted. The description is omitted.

Strictly speaking, in the configuration of the first embodiment, the load capacitances C _{L1 to} C _L48 of FIG. 13 are stray capacitances and common capacitor portions formed between the static electricity countermeasure layer 15 and the common signal line 37. 7 and a capacitor (hereinafter, referred to as C _gs ) formed between the lower layer electrode wiring 34 serving as a gate electrode in the TFT section 3 and the upper layer electrode wiring 35 connected to the individual signal wiring 22. ..

In an A4 size photoelectric conversion device that has actually come into the market as a product, the load capacitance configuration example when 1728 photoelectric conversion elements are divided into 36 blocks by 48 bits using matrix connection is as follows: The stray capacitance in the common signal line is about 10 to 20 pF, the common capacitor section is 100 to 300 pF, and the C _GS in the TFT section is about 20 to 40 pF.

In such an example of the photoelectric conversion device, by inserting the element R _COM ′ having a common resistance of about 20 to 100Ω into the ground wiring section of the common capacitor section, the common resistance R
You can adjust the value of _COM ″.
If the adjustment of the common resistance R _COM ″ and the adjustment of the variable resistance R _X and the variable capacitance C _X of the monovibrator circuit are added, it is possible to drive with sufficient transfer efficiency and zero crosstalk within the block. Become.

FIG. 14 is a sensor unit composed of a circuit pattern board having a photoelectric conversion device according to the first embodiment and a light source for illuminating an original and a flexible cable connecting the photoelectric conversion device and the circuit pattern board. It is a schematic block diagram which shows an example of a photoelectric conversion device and a circuit pattern substrate in the state which does not oppose.

Here, 10 is a sensor substrate constituting a photoelectric conversion portion, and 72 and 82 are a drive switch IC and a read switch IC, respectively.

The output signal obtained by the photoelectric conversion portion is taken out from the sensor substrate 10 through the bonding wire 71, the read switch IC 82, the flexible cable 80, the signal input connector 78, the circuit pattern substrate 75 and the signal output connector 79. Also GND
Each power source including the power source is supplied to the sensor substrate 10, each IC, and the circuit pattern 75 through a path opposite to the output signal.

The same applies to the 5V power supply and the GND power supply necessary for the multivibrator circuit for adjusting the transfer pulse width for performing the charge transfer from the load capacitances C _{L1 to} C _L48 to the read capacitors C _{T1 to} C _T48 for each photoelectric conversion device. To the signal output connector 79. In the first embodiment,
The added common resistance R _COM ′ may be arranged anywhere in the ground wiring of the common capacitor section 7. However, in FIG. 14, the common resistance R _COM ′ is a chip formed of ceramic or the like on the wiring section on the circuit pattern substrate 75. The resistor etc. are arranged. In addition, as shown in FIG. 14, when the ground wiring passes through the inside of the read switch 82, it is possible to form a resistance element inside the IC. Further, when the ground wiring passes through the flexible cable 80 or the like as shown in FIG. 14, it is possible to dispose the resistance element on the flexible cable. In addition, in the first embodiment, the variable resistor R _X 91 and the variable capacitor C _X 92 that form the multivibrator circuit are used.
14 may be arranged anywhere between the read switch IC 92 and the signal output connector 79, but in FIG. 14, it is arranged in the wiring portion on the circuit pattern substrate 75.

By changing the added common resistance R _COM ′ to a variable resistance, it is possible to adjust variations in wiring resistance and the like in each sensor unit, and to completely eliminate crosstalk in a block for each sensor unit. It becomes possible to do that more easily.

FIG. 15 is a cross-sectional view as seen from B when FIG. 14 is cut along AA '. The difference from FIG. 14 is that the photoelectric conversion device and the circuit pattern substrate 75 are arranged so as to face each other, and are in a form at the time of actual driving.

In the first embodiment, a system such as a facsimile is provided by adopting a photoelectric conversion device for directly detecting the reflected light from the original without using a unit fiber lens array or the like, that is, a so-called perfect contact type structure. It is possible to make it extremely compact, and the degree of freedom in mechanical design in constructing the system is increased.

Needless to say, it can also be used in a contact-reading type image reading apparatus using a 1 × fiber lens or the like.

As an example of a facsimile having a communication function as an image information processing apparatus configured by using the sensor unit according to the first embodiment, there is a configuration similar to that shown in FIG. Since the configuration of the facsimile has already been described, the description is omitted here.

A second embodiment of the third photoelectric conversion device of the present invention will be described. Since the second embodiment is similar to the equivalent circuit diagram of the photoelectric conversion device of the first embodiment shown in FIG. 13, detailed description of the configuration will be omitted.

The photoelectric conversion device of the second embodiment differs from the photoelectric conversion device of the first embodiment in that the load capacitance C _L is small and the common resistance R _COM ″ is large.

The operation in the second embodiment will be described with reference to FIG. FIG. 12 is a view similar to FIGS. 23, 8 and 9, the read capacitor C _T is 10 pF, and the ON resistance of the transfer switch U _SW is 4 kΩ, which is the same as FIGS. 23, 8 and 9. Here, the common resistance R _COM ″ is 1k
Ω, the load capacitance C _L is 75 pF, and the configuration is such that the stray capacitance in the common signal wiring is 20 pF, the common capacitor section is 15 pF, and the C _gs in the TFT section is 40 pF.
As can be seen from FIG. 12, even if the load capacitance C _L is reduced,
By increasing the common resistance R _COM ″, it becomes possible to reduce the intra-block crosstalk to zero at time T = 100 to 200 nsec. Specifically, time T = 180.
At nsec, the crosstalk in the block is almost zero,
The transfer efficiency α at that time reaches about 93%.

As described above, by reducing the load capacitance C _L in the circuit formation, it becomes possible to obtain a large output voltage with a small amount of input charge, as is apparent from the equation (7). This means that it is possible to reduce the amount of electric charge generated by the optical sensor, and a low-sensitivity optical sensor can be used, or a state where the incident light amount is small, that is, a state in which the light source for illuminating the original has low brightness However, the photoelectric conversion device can be used at low cost.

Others are the same as those in the first embodiment.

Next, the fourth photoelectric conversion device of the present invention will be described.

First, the principle of the present invention will be described.

The output voltage Vi of the terminal i in the case where the number of bits in one block is N can be expressed by the above-mentioned expression 1 based on the above-mentioned expression 1.

When the change in the output voltage due to the intra-block crosstalk is the largest, the input charge amount Q0 is only for one bit of the N bits, and the input charge amount is 0 for the other (N-1) bits. (Or vice versa). The output voltage of the bit whose input charge amount corresponds to Q0 is VWCT
Then,

[0211]

[Equation 9] Further, using this VWCT value, the intra-block crosstalk amount ηCT is defined as follows.

[0212]

[Equation 10] Here, VW is the original output voltage in the case where there is no intra-block crosstalk, and VWAVE is the average output voltage in the block when only one bit in the block has the input charge amount Q0 and the other bits have the input charge amount 0. Is.

[0213]

[Equation 11]

[0214]

[Equation 12] Expression 10 shows that the smaller the crosstalk amount ηCT in the block, the closer the obtained output is to the original output voltage value, and the change due to the crosstalk in the block is small.

Substituting equations 9, 11 and 12 into equation 10,

[0216]

[Equation 13] Therefore, it can be seen that the in-block crosstalk amount ηCT is a circuit constant determined only by the number of bits N in one block, the cross portion capacitance CP, and the load capacitance CL. Therefore, by modifying Equation 10,

[0217]

[Equation 14] Then, the original output value VW is VWCT changed by the crosstalk in the block and the average value V in the block.
It is understood that it is possible to detect WAVE and obtain it by using ηCT which is a circuit constant.

The case where the input charge amount Q0 is present in only one bit in one block has been considered above. However, even if this is generalized, it is the same as in the equation (14).

[0219]

[Equation 15] Therefore, the original output voltage value can be obtained.

Here, Vi is the original output voltage value of the i terminal, ViCT is the output voltage value of the i terminal changed due to intra-block crosstalk, and VAVE is the average output voltage value of the block.

A concrete example of the fourth photoelectric conversion device of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 16 shows an embodiment of the present invention. Except for the parallel-serial conversion unit A, the circuit is similar to the conventional circuit shown in FIG.
The circuit configuration of the serial conversion unit A is shown.

In the parallel-serial conversion section indicated by A, 301 detects the voltages of the load capacitors CL1 to CL3 connected to the matrix signal lines 101 to 103,
An averaging circuit for averaging, 302 is a multiplying circuit for multiplying the averaged output by a constant ηCT, and 303 is a switch TS.
1 to TS3, load capacities CL1 to C sequentially read
A differential AMP that outputs the difference between the potential of L3 and the multiplication output of the multiplication circuit 302, 304 is a constant 1 /
It is a multiplication circuit that multiplies (1-ηCT).

The constants ηCT and 1 / (1-ηCT) input to the multiplying circuits 302 and 304 are circuit constants that are uniquely determined by the circuit configuration as described above, so once set, there is no need to change them thereafter. ..

FIG. 16 is a block diagram showing Equation 15 of the present invention. The second term of the numerator of Equation 15 (ηCT
VAVE) is an averaging circuit 301 and a multiplying circuit 30
2 is obtained by subtracting the numerator of Equation 15 from the differential AMP3
03. Further, the division by (1−ηCT) in Expression 15 is realized by the multiplication circuit 304 which multiplies the reciprocal of 1 / (1−ηCT).

From the equation 15, 1 / (1-ηCT)
Since it is obvious that the output voltage proportional to the original output voltage value Vi can be obtained without multiplying by, it is possible to omit the multiplication circuit 304 and further simplify the configuration.

As is clear from the above description, according to the present invention, the original output voltage free from intra-block crosstalk can be obtained with a simple circuit configuration from the output voltage changed due to intra-block crosstalk.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross section capacitance CP is eliminated or the ratio of the cross section capacitance CP and the load capacitance CL is increased. The method becomes unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. There is no possibility that the signal output voltage is lowered due to the increased CL.

Furthermore, according to the present invention, since the original output voltage can be obtained even when the load capacitance CL is made small, it is apparent from the formula 11 by reducing the load capacitance CL as much as possible in forming a circuit. Thus, a large output voltage can be obtained with a small amount of input charge.

This means that it is possible to reduce the amount of charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or when the amount of incident light is small, that is, the light source for illuminating the original has low brightness. In this state, the photoelectric conversion device can be used at a low cost. (Second Embodiment) Next, as a second embodiment of the present invention,
A method of obtaining the average output voltage in the block by a simpler method and using the average output to obtain the original output voltage will be described.

In Expression 15, when there is a bit whose original output voltage Vi is 0, the output voltage VdCT changed by the intra-block crosstalk of that bit is

[0231]

(16) VdCT = ηCT · VAVE.

In other words, Equation 16 can be said to be that the output voltage after the intra-block crosstalk of the bit whose output voltage is originally 0 is a value obtained by multiplying the average output voltage ηCT of the block.

That is, the value of ηCT · VAVE is Vi =
It is obtained from the output voltage value VdCT of 0 bit. Substituting this relationship into Equation 15

[0234]

[Equation 17] Therefore, a bit in which Vi = 0 (hereinafter referred to as a dummy bit) is always provided in the matrix portion so as to be affected by intra-block crosstalk like other bits, and the output voltage VdCT after intra-block crosstalk of this bit is set. To
By subtracting from the output voltage value ViCT of each bit in a normal block, the original output voltage can be obtained.

FIG. 17 shows a second embodiment of the present invention based on the above method.

However, in FIG. 17, the case of an optical sensor array in which 6 optical sensors and 3 dummy bits are connected in a 3 × 3 matrix will be taken as an example. In FIG.
The same reference numerals as those in the conventional example of 4 indicate the same or corresponding portions.

In FIG. 17, 3 bits of the storage capacity 2 bits to which the photosensor is connected and the storage capacity 1 bit (dummy bit) to which the photosensor is not connected constitute one block, and the 3 blocks form the photosensor array. ing. The storage capacitors CS11 to CS32 are optical sensors S11 to S32, respectively.
It corresponds to. Further, the dummy bit storage capacitors CS1d, CS2d, and CS3d that are not associated with the photosensor are arranged in each block. Switching transistor T1
The same applies to 1 to T32 and T1d to T3d.

Further, the storage capacitors C12 to C32 and C1
The individual electrodes having the same order in each block of d to C3d are connected to one of the common lines 101 to 103 via the switching transistors T12 to T32 and T1d to T3d, respectively.

Specifically, the first switching transistors T11, T21, T31 of each block are connected to the common line 1
01 to the second switching transistor T of each block
12, T22, T32 on the common line 102, and the third switching transistors T1d, T2 of each block.
d and T3d are connected to the common line 103, respectively.

Switching transistors T11 to T32
The gate electrodes of T1d to T3d are commonly connected for each block, and are connected to the parallel output terminal of the shift register 201 for each block. Therefore, the switching transistors T11 to T32 and T1d to T3d are sequentially turned on for each block depending on the shift timing of the shift register 201. Common lines 101-103
Are connected to the amplifier 204 via the switching transistors TS1 to TSd, respectively.

Switching transistors R11 to R32
Similarly to the gate electrodes of the switching transistors T11 to T32 and T1d to T3d, the gate electrodes of R1d to R3d and R1d to R3d are commonly connected to each block and connected to the parallel output terminal of the shift register 202 for each block. Therefore, depending on the shift timing of the shift register 202, the switching transistors R11 to R3 are
2 and R1d to R3d are sequentially turned on for each block.

Further, in FIG. 17, the common lines 101 to 10
3 is installed via load capacitors CL1, CL2, CLd, respectively, and switching transistors RS1, R
It is grounded via S2 and RSd.

The capacities of the load capacitors CL1, CL2 and CLd are set sufficiently larger than those of the storage capacitors CS11 to CS32 and C1d to C3d. The gate electrodes of the switching transistors RS1, RS2, RSd are commonly connected and connected to the terminal 104. That is, when the high level is applied to the terminal 104, the switching transistors RS1 to RS3 are simultaneously turned on and the common lines 101 to 103 are grounded.

Even if the dummy bits are arranged in this way, the photosensors S11 to S32 can be arranged at equal intervals, so that the quality of image reading is not impaired.

Next, the operation of the embodiment having such a configuration is shown in FIG.
2, RSd and R11 to R32 and R1d to R3d will be described with reference to the timing charts. However, in FIG. 18, the timing at which each switching transistor is turned on is shown, but of course, this timing is also the high-level timing output from the shift registers 201, 202, and 203.

First, when light is incident on the photosensors S11 to S32, the power supply 105 causes the capacitor CS to change in intensity.
Electric charges are accumulated in 11 to CS32. On the other hand, no charge is stored in the storage capacitors CS1d to CS3d to which no photosensor is connected. A high level is output from the first parallel terminal of the shift register 201, and the switching transistors T11, T12, T1d are turned on (FIG. 18-
a).

Switching transistors T11, T1
2, the T1d is turned on, the capacitor CS1
The charges accumulated in 1, CS12, CS1d are transferred to the capacitors CL1, CL2, CLd, respectively.
Originally, since no charge is stored in the storage capacitor CS1d, no charge is transferred to the capacitor CLd. However, due to the intra-block crosstalk, the charges of other bits spill into the capacitor CLd.

Then, the terminal 106 becomes high level,
The switching transistor TSd is turned on (FIG. 18-d). Furthermore, the high level output from the shift register 203 is shifted, and the switching transistors TS1 and TS2 are sequentially turned on (FIGS. 18-e-).
FIG. 18-f).

As a result, the capacitors CL1 and CL are
2, the optical information after intra-block crosstalk of the first block transferred to CLd and accumulated and the information of the dummy bit are sent to the differential amplifier 303, and from the optical information after intra-block crosstalk, after intra-block crosstalk Outputs obtained by subtracting the information of the dummy bits are sequentially read. The multiplier 304 outputs a circuit constant of 1 / (1
Multiply −ηCT) to get the output without the original crosstalk. When the information of the first block is read, a high level is applied to the terminal 104, and the switching transistors RS1, RS2, RSd are simultaneously turned on (FIG. 18-g).

By this, the capacitors CL1 and CL
2. CLd residual charges are completely discharged. When the residual charges of the capacitors CL1, CL2, CLd are completely discharged, the shift register 201 shifts, and a high level is output from the second parallel terminal. As a result, the switching transistors T21, T22, T2d are turned on (FIG. 18-b), and the capacitor CS of the second block is turned on.
The charges accumulated in 21, CS22, CS2d are transferred to the capacitors CL1, CL2, CLd. At the same time, a high level is output from the first parallel terminal of the shift register 202, and the switching transistor R11,
R12 and R1d are turned on (FIG. 18-h), and the residual charges of the capacitors CS11, CS12, and CS1d are completely discharged. And like the case of the first block,
The terminal 106 becomes high level, and the shift register 203 shifts the switching transistor TS.
1, TS2, TSd are turned on, and the capacitor CL
The difference between the optical information after the intra-block crosstalk of the second block and the information of the dummy bit accumulated in CL1, CL2, and CLd is sequentially read, and the circuit constant 1 / (1-η
CT) is multiplied to obtain the output when there is no original crosstalk (FIGS. 18-d to 18-f).

Similarly, in the case of the third block, the discharging operation of the capacitors CS21, CS22, CS2d of the second block is performed in parallel with the transfer operation (FIG. 18-c) (FIG. 18-i), and so on. Then, the above operation is repeated for each block.

FIG. 19 shows another embodiment of the present invention. Figure 1
The dummy bit 9 of the embodiment shown in FIG. 17 is provided with dark dummy sensors S1d to S3d which are always in a dark state. In a general optical sensor, the dark output may increase as the temperature rises, and the quality of the read signal may deteriorate. In this case, the signal charge Q0 is the original signal charge Qs and the dark output charge Qd.
Is the sum form (Q0 = Qs + Qd). Even when the dark output increases in this way, when the dark outputs of the photosensors in the block are the same, a dark dummy sensor is provided as in the method of FIG. 19 and the same reading as in the embodiment of FIG. 17 is performed. In addition to the correction of intra-block crosstalk, it is possible to subtract the dark output for each block by performing
It is clear that is obtained by setting Q0 = Qs + Qd. This makes it possible to significantly improve the quality of the read signal even when the dark output is increased.

The above embodiments have been described for the case where the photosensor is of the photoconductive type, but it goes without saying that the present invention is not limited to this and can be applied to various photosensors such as photodiodes and phototransistors.

Further, in the present embodiment, the case of a one-dimensional line sensor is shown, but also in a color line sensor in which a plurality of rows of photosensors are arranged, a two-dimensional area sensor, etc., a plurality of signals are connected by matrix connection. It is obvious that the present invention can be applied to the case of reading in parallel.

An example of a facsimile having a communication function as an image information processing apparatus configured by using photoelectric conversion according to the present invention may have the same configuration as that shown in FIG.

[0256]

As is apparent from the above description, according to the first photoelectric conversion device of the present invention, the charge transfer time is adjusted with respect to the variation in the capacitance value and the resistance value which occurs in each photoelectric conversion device. As a result, in each photoelectric conversion device, an original output voltage with no intra-block crosstalk can be obtained with a simple circuit configuration.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross portion capacitance CP is eliminated, or the ratio of the cross portion capacitance CP and the load capacitance CL is increased. Countermeasures are unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. There is no possibility that the signal output voltage drops due to the increase in CL.

Further, according to the present invention, the original output voltage can be obtained even if the load capacitance CL is made small as long as the transfer efficiency can be secured. Therefore, by reducing the load capacitance CL as much as possible in circuit formation, As is clear from FIG. 7, a large output voltage can be obtained with a small amount of input charge.

This shows that it is possible to reduce the amount of charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or a state where the amount of incident light is small, that is, the light source for illuminating the original has low brightness. Since it can be used even in the state of, the cost of the photoelectric conversion device can be reduced.

Further, according to the second photoelectric conversion device of the present invention, it is possible to obtain an original output voltage having no intra-block crosstalk in which the black signal is increased by the white signal with a simple circuit configuration.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross portion capacitance CP is eliminated, or the ratio between the cross portion capacitance CP and the load capacitance CL is increased. Countermeasures are unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. There is no possibility that the signal output voltage drops due to the increase in CL.

Furthermore, according to the present invention, since the original output voltage can be obtained even when the load capacitance CL is made small, it is apparent from the equation 7 by reducing the load capacitance CL as much as possible in forming a circuit. Thus, a large output voltage can be obtained with a small amount of input charge.

This means that it is possible to reduce the amount of charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or when the amount of incident light is small, that is, the light source for illuminating the original has low brightness. Since it can be used even in the state of, the cost of the photoelectric conversion device can be reduced.

Further, according to the third photoelectric conversion device of the present invention, it is possible to obtain an original output voltage having no intra-block crosstalk in which the black signal is increased by the white signal, with a simple circuit configuration.

Therefore, in order to eliminate or reduce the intra-block crosstalk that has been conventionally performed, the cross portion capacitance CP is eliminated, or the ratio of the cross portion capacitance CP and the load capacitance CL is increased. Countermeasures are unnecessary. Therefore, there is a problem with these countermeasures, that is, a shield layer must be separately provided, the wiring yield is reduced by reducing the wiring width to reduce the cross portion capacitance CP, or the load capacitance is decreased. There is no possibility that the signal output voltage drops due to the increase in CL.

Further, according to the present invention, the cross resistance in the block for each photoelectric conversion device due to the variation of the common resistance R _COM and the load capacitance C _{L which} are parasitically generated, the common resistance is newly added to adjust the common resistance. It can be completely eliminated by adjusting the variable resistance R _X and variable capacitance C _{X of the} monomultivibrator circuit.

Furthermore, according to the present invention, since the original output voltage can be obtained even when the load capacitance CL is made small, it is apparent from the equation 7 by reducing the load capacitance CL as much as possible in circuit formation. Thus, a large output voltage can be obtained with a small amount of input charge.

This means that it is possible to reduce the amount of charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or a state in which the amount of incident light is small, that is, the light source for illuminating the original has low brightness. Since it can be used even in the state of, the cost of the photoelectric conversion device can be reduced.

Further, according to the fourth photoelectric conversion device of the present invention, since the intra-block crosstalk of the matrix-connected photoelectric conversion device can be corrected with a simple structure, the photoelectric conversion device with excellent signal quality can be manufactured at low cost. Can be provided to.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a photoelectric conversion device according to an embodiment of a first photoelectric conversion device of the present invention.

FIG. 2 is a schematic cross-sectional view of a photoelectric conversion unit according to the photoelectric conversion device of FIG.

FIG. 3 is a schematic plan view of a photoelectric conversion unit according to the photoelectric conversion device of FIG.

FIG. 4 is a schematic plan view of a sensor unit according to the present embodiment.

5 is a schematic cross-sectional view of the sensor unit of FIG. 4 taken along the line AA ′.

FIG. 6 is a schematic configuration diagram showing an example of a facsimile having a communication function as an image information processing apparatus configured by using the sensor unit according to the present embodiment.

FIG. 7 is an equivalent circuit diagram of the photoelectric conversion device according to the first example of the second photoelectric conversion device of the present invention.

FIG. 8 is a simulation diagram illustrating intra-block crosstalk in the photoelectric conversion device in FIG. 7.

FIG. 9 is a simulation diagram illustrating intra-block crosstalk in the photoelectric conversion device in FIG. 7.

FIG. 10 is a schematic plan view of a sensor unit according to the present embodiment.

FIG. 11 is a schematic cross-sectional view of the sensor unit of FIG. 10 taken along the line AA ′.

FIG. 12 is a simulation diagram illustrating intra-block crosstalk in a photoelectric conversion device according to a second embodiment of the second photoelectric conversion device of the present invention.

FIG. 13 is an equivalent circuit diagram of the photoelectric conversion device according to the first embodiment of the third photoelectric conversion device of the present invention.

FIG. 14 is a schematic plan view of a sensor unit according to the present embodiment.

15 is a schematic cross-sectional view of the sensor unit of FIG. 14 taken along the line AA ′.

FIG. 16 is a block diagram of a parallel-serial conversion unit of the first exemplary embodiment of the fourth photoelectric conversion device of the present invention.

FIG. 17 is an equivalent circuit of the photoelectric conversion device of the second embodiment of the fourth photoelectric conversion device of the present invention.

FIG. 18 is a timing chart for explaining the operation of the photoelectric conversion device according to the second embodiment.

FIG. 19 is an equivalent circuit of a photoelectric conversion device of another embodiment of the fourth photoelectric conversion device of the present invention.

FIG. 20 is an equivalent circuit diagram of a conventional photoelectric conversion device.

FIG. 21 is a timing chart diagram for explaining the operation of the photoelectric conversion device of FIGS. 1 and 20.

FIG. 22 is a conceptual diagram for considering intra-block crosstalk.

FIG. 23 is a simulation diagram illustrating intra-block crosstalk in a conventional photoelectric conversion device.

FIG. 24 is an equivalent circuit of a conventional photoelectric conversion device.

FIG. 25 is a timing chart for explaining the operation of the conventional photoelectric conversion device of FIG.

[Explanation of symbols]

S _{1-1 to} S _36-48 photoelectric conversion element C _{S1-1 to} C _S36-48 storage capacitor T _{1-1 to} T _36-48 transfer TFT L _{1 to} L ₄₈ matrix signal wiring R _{1-1 to} R _{36 -48} Reset TFT C _{L1 to} C _L48 Load capacitance T _{SW1 to} T _SW48 Read switch U _{SW1 to} U _SW48 Transfer switch C _{T1 to} C _T48 Read capacitor V _SW Reset switch SR1 Shift register SR2 Shift register R _{SW1 to} R _SW48 reset switch _101-103 matrix signal line 203 shift register 301 averaging circuit 302 multiplication circuit 303 differential AMP 304 multiplication circuit CS11-CS32 storage capacity S11-S32 optical sensor CS1d, CS2d, CS3d storage capacity

Claims (7)

[Claims] 1. At least a plurality of optical sensors, a first switch means for sequentially extracting a fixed number of output signals of the optical sensors as one block, and a block for one block extracted by the first switch means. A first accumulating means for accumulating a signal; a matrix connecting part for connecting the first accumulating means with the plurality of photosensors; and a one-block signal for accumulating in the first accumulating means. In a photoelectric conversion device having two switch means and a second storage means for storing one block of signals extracted by the second switch means, the ON time of the second switch means is adjusted. A photoelectric conversion device comprising means. 2. At least a plurality of optical sensors, a first switch means for sequentially extracting a fixed number of output signals of the optical sensors as one block, and one block for one block taken out by the first switch means. A first accumulating means for accumulating a signal; a matrix connecting part for connecting the first accumulating means with the plurality of photosensors; and a one-block signal for accumulating in the first accumulating means. In a photoelectric conversion device having two switch means and a second storage means for storing the signal of one block extracted by the second switch means, at least one electrode of the first storage means is provided. A photoelectric conversion device, characterized in that it is connected for one block and is connected to a constant potential through a common resistance sufficiently larger than a ground wiring resistance generated parasitically on the electrode. 3. At least a plurality of optical sensors, a first switch means for sequentially extracting a fixed number of output signals of the optical sensors as one block, and one block taken out by the first switch means. A first accumulating means for accumulating a signal; a matrix connecting part for connecting the first accumulating means with the plurality of photosensors; and a one-block signal for accumulating in the first accumulating means. In a photoelectric conversion device having two switch means and a second storage means for storing the signal of one block extracted by the second switch means, at least one electrode of the first storage means is provided. Connected for one block and connected to a constant potential through a common resistor,
A photoelectric conversion device comprising means for adjusting the resistance value of the common resistor and means for adjusting the on-time of the second switch means. 4. A plurality of photosensors, a switch means for sequentially taking out a constant of each output signal of each photosensor as one block, an accumulating means for accumulating the signal of one block taken out by the switch means, In a photoelectric conversion device having a matrix connection unit that connects a storage unit and the optical sensor, and a signal reading unit that sequentially extracts signals for one block stored in the storage unit, a photoelectric conversion device of one block stored in the storage unit Calculating means for obtaining an average value of the signals and multiplying the average value by a constant determined by the configuration of the photoelectric conversion device; and a differential for subtracting the calculated value obtained by the calculating means from each signal of the one block. A photoelectric conversion device comprising: 5. The photoelectric conversion device according to claim 4, wherein the signal reading unit that sequentially extracts the signals for one block includes a parallel-serial conversion unit. 6. A storage means for storing the output signal of the photosensor for one block, and a storage means for dummy bits having the same structure as the storage means, and the signal output of the dummy bit is calculated. The photoelectric conversion device according to claim 4, wherein the photoelectric conversion device is used as a value. 7. Always 1 for each block of the photosensor.
7. The photoelectric conversion device according to claim 6, further comprising a dark dummy sensor that outputs a dark output of a bit, and a storage unit for the dummy bit that stores an output of the dark dummy sensor.