JP2967953B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device and, more particularly, to a photoelectric conversion device suitably used for an input unit such as a facsimile, an image reader, a digital copying machine, and an electronic blackboard.

[0002]

2. Description of the Related Art In recent years, a long line sensor having an equal-magnification optical system has been developed as a photoelectric conversion device for miniaturization and high performance of a facsimile, an image reader, and the like.

Conventionally, this type of line sensor has a signal processing integrated circuit (hereinafter, referred to as an IC) in which a switch element or the like is configured for each photoelectric conversion element arranged in a row. Connected and configured. However, according to the facsimile G3 standard, the number of the photoelectric conversion elements needs to be 1,728 in A4 size. For this reason, the number of mounting steps is increased, and satisfactory manufacturing cost and reliability cannot be obtained.

On the other hand, the number of ICs for signal processing is reduced,
As a configuration for reducing the number of mounting steps, a configuration using matrix wiring has conventionally been adopted.

[0005] A thin film transistor (hereinafter, referred to as a TFT) is used as a switching element, and an integrated structure including a photoelectric conversion element, a TFT, a matrix wiring, and the like is provided, so that the function of an IC for signal processing is improved. Attempts have also been made to provide a low-cost, high-speed, long contact-type image reading device at low cost.

Further, in order to reduce the manufacturing cost and provide a highly reliable long contact type image reading device, the photoelectric conversion layer of the photoelectric conversion element and the semiconductor layer of the TFT are made of the same material, for example, amorphous silicon. Formed, photoelectric conversion element, TF
A method of integrally forming T, matrix wiring, and the like on the same substrate using the same manufacturing process has also been developed.

Further, in order to reduce the size and cost,
There has also been proposed a photoelectric conversion device in which a photoelectric conversion element directly detects reflected light from a document via a transparent spacer such as glass without using an equal-magnification fiber lens array.

FIG. 7 is an equivalent circuit diagram of the conventional photoelectric conversion device that we proposed earlier.

[0009] The optical information incident on the photoelectric conversion elements S _1-1 to S _36-48 are accumulated from the photoelectric conversion elements S _1-1 to S _36-48 capacitor C _S1-1 ~C _S36-48, transferring TFT T _{1-1 to} T
_36-48, through the matrix signal wirings L ₁ ~L _48, the parallel voltage outputs. Further, the readout signal is converted into a serial signal by the readout switch IC and is extracted to the outside. Note that the residual charges stored in the storage capacitors C _{S1-1 to} C _S36-48 are reset by the reset TFTs R _{1-1 to} R _36-48 .

Here, the readout switch IC is a
Load capacitor C in the signal wiring section _L1~ C_L48And read
Switch T_SW1~ T_SW48Between the transfer switch U
_SW1~ U_SW48And reading capacitor C_T1~ C_T48And
And readout capacitor C_T1~ C_T48Reset
Reset switch V_SWIs provided.

[0011] transfer switch U _SW1 ~U _SW48 is connected to the wiring of the matrix signal wirings L ₁ ~L _48, stored in the load capacitor C _L1 -C _L48 formed in the matrix signal wiring L ₁ ~L ₄₈ the obtained charge, a switch for transferring to the read capacitor C _T1 -C _T48, are simultaneously driven by a transfer pulse G _t.

The read switches T _{SW1 to} T _SW48 are connected to the respective read capacitors and are sequentially switched so that the potentials of the read capacitors C _{T1 to} C _T48 are sequentially read out of the photoelectric conversion device via the amplifier Amp. Switches for reading, and are sequentially driven by the shift register SR2.

R _{SW1 to} R _SW48 are provided between the load capacitors C _{L1 to} C _L48 formed in the matrix signal wiring section and the transfer switches U _{SW1 to} U _SW48, and
The potential of _L1 -C _L48 is a reset switch for resetting the reset potential V _R, it is driven by the reset pulse C _res.

V _SW is a read capacitor C _T1.
The potential of -C _T48 is a reset switch for resetting the reset potential V _R, driven by a reset pulse g _res.

In the configuration example of the photoelectric conversion device of this conventional example, photoelectric conversion elements having a total number of pixels of 1,728 bits are grouped into 48 blocks each of which is divided into 36 blocks. Each operation proceeds sequentially in units of this block. FIG. 8 shows a timing chart when a document having a uniform image density is read by a conventional photoelectric conversion device.

The photoelectric conversion elements S _{1-1 to} S in the first block
_The optical information incident on _1-48 is stored in storage capacitors C _S1-1 -C
_Stored as charges in _s1-48 . After a certain time, a voltage pulse is applied from the shift register SR ₁ to the first gate driving line G _1, T _1-1 through T _1-48 of the transfer TFT is turned ON. Thereby, the charges of the storage capacitors C _{S1-1 to} C _s1-48 are transferred to the load capacitors C _{L1 to} C _L48 through the matrix signal wirings L _{1 to} L ₄₈ . The gate pulse width t ₁ required for this transfer (shown in FIG. 8) is determined by the value of the smaller capacitance value of the storage capacitor C _S and the load capacitor C _L and the ON resistance R _t of the transfer TFT T Depends on the time constant.

The storage capacitor C _S 10～20PF, load capacitor C _L is a suitable value 100～300PF, the ON resistance R _t a-Si: a high resistance and a few MΩ in TFT using an H Therefore, this time constant is 10 to 4
It becomes 0 μsec.

[0018] By the application of followed by the gate drive signal G _t,
The transfer switches U _{SW1 to} U _SW48 are simultaneously turned on, and the signal charges stored in the load capacitors C _{L1 to} C _L48 are simultaneously transferred to the read capacitors C _{T1 to} C _T48 . Length _t of gate pulse Gt required for this transfer
₃ (shown in FIG. 8) is the ON resistance R of the transfer switch U _SW
u and depends on the time constant determined by the value of the smaller capacitance of the load capacitor C _L and a read capacitor C _T.

[0019] The load capacitor C _L is 100~300p
F, the read capacitor C _T is 10~20pF an appropriate value, ON resistance Ru is because it can select the 3k~5kΩ With general analog switches, the time constant can be below the shorter value 100 nsec.

[0020] Subsequently, by the shift register SR ₂ is the voltage pulse is sequentially applied to the gate drive lines g ₁ to g _48, the signal charges of the first block transferred to the read capacitor C _T1 -C _T48, read Switch T
_It is converted to a serial signal by _{SW1 to} T _SW48 , and the amplifier Amp
And is taken _out of the photoelectric conversion device as an output voltage _Vout .

During the period t ₄ (shown in FIG. 8) during which the signal output for one block is output, the input resistance including the ON resistance Rt of the readout switch T _SW and the wiring capacitance of the amplifier Amp, and the response speed of the amplifier. However, since it can be selected from 1 to 2 μsec per bit, it is about 50 to 100 μsec for 48 bits.

In this read operation, the reset pulse g _res is applied to the reset switch V _SW during the latter half period t ₅ (shown in FIG. 8) of the period in which the voltage pulses applied to g _{1 to} g ₄₈ are high voltage (high). Applied sequentially. Thus, in this second half period t _5, read switch T _SW and a reset switch V _SW is turned ON at the same time, the read capacitor C _T1 -C _T48 is reset to sequentially reset potential V _R.

The gate pulse g required for this reset
The length t ₅ of the _res is, the ON resistance Rv of the reset switch V _SW, depends on the time constant determined by the values of the ON resistance Rt and read capacitor C _T of the read switch T _SW, the capacitor C _T for reading 10 to 20 pF is appropriate, and if a general-purpose analog switch is used for the ON resistances Rv and Rt, the resistance can be selected to be 50 to 300 Ω.
This time constant can be a short value of 100 nsec or less.

In parallel with this signal reading operation,
Reset pulses C _res are _output to reset switches R _{SW1 to} R _SW1.
By applying the voltage to _SW48 , the load capacitors C _L1 -C
_L48 is reset at the same time.

The gate pulse C required for this reset
_res length t ₂ (shown in FIG. 8) depends on the time constant determined by the values of the resistor and load capacitor C _L of the ON resistance Rr, matrix signal wires of the reset switch R _SW,
The value is about several μsec. After the reset operation is completed, the voltage pulse to the gate driving line G ₂ is applied from the shift register SR _1, the transfer operation of the second block starts. At the same time as this transfer operation, the reset block T of the first block is used.
R _1-48 from FT of R _1-1 is turned ON, the charge storage capacitor C _S1-1 ~C _S1-48 of the first block are reset to the reset potential V _R, ready for the next accumulating operation. Hereinafter, data for one line is output by sequentially driving the gate drive lines G ₃ , G ₄ ,.

[0026]

However, in a conventional matrix-connected photoelectric conversion device, even when the amount of charge accumulated by the sensor is the same, the output voltage differs depending on the amount of charge of other bits in the block. (Hereinafter referred to as intra-block crosstalk). In order to consider the change in the output voltage due to the crosstalk in the block, one block as shown in FIG. 9 is made up of 3 bits, the load capacitor value of each bit is CL, and the cross section capacitance value is CP. Consider a matrix circuit.

Each terminal 1 to 3 of such a matrix circuit
Output voltage V1 when signal charges Q1 to Q3 are input to
V3 is represented by an equation.

[0028]

(Equation 1) The output voltage when the input charge is Q1 = Q2 = Q3 = Q0 is

[0029]

(Equation 2) Becomes

When the input electric charge is Q1 = Q2 = Q3 = 0, similarly, V1 = V2 = V3 = 0 from the equation.

However, if the input charge is Q1 = Q, Q2
In the case of = Q3 = 0, V1 = a.Q1 ＝ VO V2 = V3 = b.Q1、0, and the output voltage is different even if the input charge amount is the same.

Here, based on the equation, the output voltage Vi at the terminal i when the number of bits in one block is N can be described as the equation.

[0033]

(Equation 3) When the change in the output voltage due to the intra-block crosstalk is the largest, only one of the N bits has an input charge amount of zero.
This is the case where the input charge amount of the other (N-1) bits is Q0 (or the reverse case). This input charge amount is 0
The output voltage of the load capacitor CL of the bit corresponding to
Assuming W0,

[0034]

(Equation 4) When the output voltage of the load capacitor CL of the bit corresponding to the input charge amount Q0 is VWQ,

[0035]

(Equation 5) Further, using the value of VW0, the intra-block crosstalk amount XCT at the terminal i is defined as follows.

[0036]

(Equation 6) Here, VW is the original output voltage of the terminal i when there is no intra-block crosstalk of the bit corresponding to the input charge amount Q0.

[0037]

(Equation 7) Further, the crosstalk amount XCT is also consistent with the crosstalk amount for the output voltage of the CT after the charge transfer from the CL to the CT by transfer switches U _SW in FIG. The equation shows that as the intra-block crosstalk amount XCT approaches 0, the obtained output approaches the original output voltage value and the change due to intra-block crosstalk is small.

In a reproduced image using a document reading signal, a condition under which crosstalk in a block is likely to be a problem is when a black document reading signal is increased by a white document reading signal.

Here, the change over time of the crosstalk in the block of the conventional example shown in FIG. 7 will be considered. FIG. 10 shows that the input charge amount of the load capacitor C _L1 is 0 and the load capacitors C _L2 to C _L
When the input charge amount of _L48 is Q0, the voltages V _CL1 , V _{CL2 to} V _CL48 of the load capacitors C _L1 , C _{L2 to} C _L48 ,
And capacitors C _T1, C _T2 ~C _T48 of the read voltage shows the time course of the V _CT1, V _CT2 ~V _CT48 and block crosstalk amount XCT.

Here, when T = 0, the transfer switch U _SW is ON.
The read capacitor C _T is 10 pF, the load capacitor C _L is 200 pF, the ON resistance of the transfer switch U _SW is 4 kΩ, and the common resistance R _COM = 10
The simulation is performed as Ω (the common resistance R _COM here is a parasitically generated resistance). Where T = chi 'is a time satisfying XCT = 0, the charge transfer efficiency α from the load capacitor C _L to the read capacitor C _T is at this timing is found to be about 30%. Generally, it is considered that the transfer efficiency α is required to be 80% or more.

In order to suppress such a change in the output voltage due to the cross stroke in the block, as is apparent from the equation, the cross portion capacitance CP is eliminated, or the ratio between the cross portion capacitance CP and the load capacitance CL is reduced. It is conceivable to increase it. Specific measures for these measures are described in JP-A-62-67864 and JP-A-62-67865.

However, in these countermeasures, a shield layer must be separately provided between the wirings in order to prevent the formation of the cross-part capacitance CP, or the width of the wiring is narrowed to reduce the cross-part capacitance CP. As a result, new problems such as a reduction in production yield and a decrease in signal output voltage due to an increase in the load capacitance CL occur.

The present invention has been made in view of the above problems, and provides a low-cost photoelectric conversion device having excellent signal quality by enabling crosstalk in a block to be corrected with a simple configuration. The purpose is to achieve low cost of equipment.

[0044]

The photoelectric conversion device according to the present invention comprises at least a plurality of optical sensors, first switch means for sequentially taking out a predetermined number of output signals of the optical sensors as one block, and A first storage unit having a capacitance value C _L for storing one block of signals taken out by one switch unit; a matrix connection unit connecting the first storage unit to the plurality of optical sensors; A second block for sequentially extracting signals for one block stored in the first storage unit;
And a second storage means for storing one block of signals taken out by the second switch means, wherein at least one electrode of the first storage means has one electrode. connected blocks, and is connected to a constant potential through a common resistance of the resistance value R _COM, the first product C _L · R _COM capacitance value C _L and the common resistance resistance R _COM accumulation means 5. 0 × 10 ^-9 F ・ Ω
It is characterized by the above.

[0045]

According to the present invention, one electrode of the first storage means has one electrode.
Connected blocks, and is connected to a constant potential through a common resistance of the resistance value R _COM, the first product C _L · R _COM capacitance value C _L and the common resistance resistance R _COM accumulation means 5. by such a 0 × 10 ^-9 F · Ω or more, when the block crosstalk amount XCT becomes 0, the charge transfer efficiency α from the load capacitor C _L to the read capacitor C _T is 80% or more It is like that.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an embodiment according to the present invention, and shows an equivalent circuit diagram of a photoelectric conversion device. In the present embodiment, the photoelectric conversion element unit, the storage capacitor unit, and the TF formed on the same substrate
The configuration of the photoelectric conversion unit such as the T unit, the matrix signal wiring unit, and the gate drive wiring unit is basically the same as the equivalent circuit diagram of the conventional photoelectric conversion device shown in FIG.

The point that the photoelectric conversion device of the present embodiment differs from the conventional photoelectric conversion device in terms of an equivalent circuit is that the load capacitors C _L1 to C _L1 .
One of the common fixed potential electrode C _L48 (hereinafter referred to as the ground electrode) is that is grounded through a common resistor R _COM.

Hereinafter, the operation of the photoelectric conversion device of this embodiment will be described, but the description of the elements and timings that perform the same operations as in the conventional example will be omitted.

[0050] The photoelectric conversion element S _1-1 to S of the first block
_The optical information incident on _1-48 is converted into a _photocurrent and stored as charges in the storage capacitors C _{S1-1 to} C _S1-48 . After a certain time, the first voltage pulse for transfer t ₁ hour added to the gate drive lines G _1, switches the T _1-1 through T _1-48 of transferring TFT to the ON state. The storage capacitors C _S1-1 to C _S
Charge of _S1-48 is through the matrix signal wirings L ₁ ~L _48, is transferred to the load capacitor C _L1 -C _L48, the potential V _L1 ~V _L48 of each load capacitor increases.

At this time, crosstalk in the block occurs due to the cross capacitance CP of the matrix signal lines L _{1 to} L ₄₈ .

[0052] By the application of followed by the gate drive signal G _t,
The transfer switches U _{SW1 to} U _SW48 are _turned on at the same time, and the signal charges stored in the load capacitors C _{L1 to} C _L48 are simultaneously transferred to the read capacitors C _{T1 to} C _T48 .

At this time, since all the ground electrodes of the load capacitors C _{L1 to} C _L48 are connected, the ground electrode potential V _COM of the bit whose input electric charge is 0 becomes the ground electrode V _COM of the bit whose input electric charge is Q0. Same as potential. Ground electrode potential V
_COM indicates that the total input charge of the bit whose input charge amount is not zero passes through the transfer switch U _SW and the read capacitor C _T.
At the moment it is transferred to.

At the same time, the potential V _L of the load capacitor C _L of the bit whose input charge amount is zero also drops greatly, but it takes time to return to the ground potential due to the common resistor R _COM . Therefore, the charge from the read capacitor C _T bit of amount input charge zero to the load capacitor C _L is transferred, the potential of the read capacitor C _T of amount input charge zero bits V _CT
Decreases to a minimum value. As the ground electrode potential V _COM returns to the ground potential, V _CT rises and saturates to a certain value. The time constant of the time the load capacitor C _L and a read capacitor C _T value as transfer switches T _SW of smaller capacitance value of
Is determined by the ON resistance.

Eventually, the potential determined by VW0 in the equation and the load capacitor C _L and the read capacitor C _T.

[0056]

(Equation 8) become.

The above operation will be described with reference to FIG. Figure 2 is a view similar to FIG. 10, the read capacitor C _T 10 pF, the load capacitor C _L is 200 pF, ON resistance of the transfer switch U _SW is 4k, is the same as FIG. 10. The simulation is performed with the common resistance R _COM set to 25Ω.

[0058] According to FIG. 2, the potential V _CT1 of input charge amount zero at a 1-bit read capacitor C _T1, decreases from V _R, rising eventually are further increased becomes V _R. Here, T = χ ″ (T ≒ 110 nsec) becomes XCT =
Is a 0. The time, the charge transfer efficiency α from the load capacitor C _L to the read capacitor C _T is at this timing is found to be about 80%. The value of χ ″ is C _L
Since it depends on R _COM , to make the charge transfer efficiency α 80% or more, C _L · R _COM ≧ 200 pF × 25Ω = 5.0
× 10 ⁻⁹ F · Ω may be used.

In FIG. 2, by turning on the transfer switch T _SW from T = 0 to T = χ ″, the crosstalk in the block where the black signal is increased by the white signal can be made zero. .

Another simulation result will be described with reference to FIG. FIG. 3 is a diagram similar to FIG. 10, in which the input charge amount of each bit and the resistance and capacitance of each element are shown in FIG.
Is the same as The simulation is performed with the common resistance R _COM set to 70Ω. That is, C _L · R _COM = 200
This is the case where pF × 70Ω = 1.4 × 10 ⁻⁸ F · Ω. At the timing of T = χ when the crosstalk amount XCT = 0, the transfer efficiency α similar to that in FIG. 10 is about 85%.

Therefore, in FIG. 3, by turning on the transfer switch T _SW during the period from T = 0 to T = χ, the crosstalk in the block in which the black signal is increased by the white signal can be made zero. .

As apparent from the above description, according to the present invention, it is possible to obtain an original output voltage with no crosstalk in a block in which a black signal is increased by a white signal with a simple circuit configuration.

Therefore, in order to eliminate or reduce the crosstalk in the block conventionally performed, the countermeasure such as eliminating the cross portion capacitance CP or increasing the ratio between the cross portion capacitance CP and the load capacitance CL is adopted. There is no need for a method. Therefore, the problems associated with these countermeasures, that is, a shield layer must be separately provided, the yield in manufacturing is reduced in order to reduce the cross-section capacitance CP by reducing the wiring width, or the load capacitance is reduced. The signal output voltage drops due to the increase in CL,
There is no occurrence.

Furthermore, according to the present invention, even when the load capacitance CL is reduced, the original output voltage can be obtained. Therefore, by reducing the load capacitance CL as much as possible in terms of circuit formation, it becomes clear from the equation. In addition, a large output voltage can be obtained with a small input charge amount.

This indicates that the amount of electric charge generated by the optical sensor can be reduced, and that a low-sensitivity optical sensor can be used, or that the amount of incident light is small, that is, the light source for illuminating the original has low luminance. Therefore, the photoelectric conversion device can be used at a low cost.

FIGS. 4 and 5 are a schematic sectional view and a plan view of a photoelectric conversion unit according to the photoelectric conversion device of this embodiment.

In this embodiment, a-Si: H is used, and the photoelectric conversion element section 1, the storage capacitor section 2, the TFT sections 3 and 4, the matrix signal wiring section 5, the gate drive wiring section 6, the common capacitor section 7, and the like. Are integrally formed on the translucent insulating substrate 10 by the same process.

On the translucent insulating substrate 10, a first conductor layer 24 of Al, Cr, etc., a first insulating layer 25 of SiN, etc.
a-Si: H photoconductive semiconductor layer 26, n ⁺ type a
-Si: H ohmic contact layer 27, Al, Cr
And the like, a second conductor layer 28 is formed.

In the photoelectric conversion element section 1, 30 and 3
Reference numeral 1 denotes an upper electrode wiring. The signal light L ′ reflected by the document P changes the conductivity of the photoconductive semiconductor layer 26 made of a-Si: H, and the upper electrode wiring 30, which faces in a comb shape,
The current flowing between 31 is changed. Reference numeral 32 denotes a metal light-shielding layer, which is connected to an appropriate drive source to
(Source electrode or drain electrode) and 31 (drain electrode or source electrode) may be used as a control electrode (gate electrode).

The storage capacitor section 2 includes a lower electrode wiring 33
The first insulating layer 25 and the photoconductive semiconductor layer 26 formed on the lower electrode wiring 33;
And a wiring continuous with the upper electrode wiring 31 formed on the photoelectric conversion element portion 1 formed thereon. The structure of the storage capacitor unit 2 is a so-called MIS capacitor structure. Both positive and negative bias conditions can be used, but stable capacitance and frequency characteristics can be obtained by using the lower electrode wiring 33 in a state where it is always negatively biased.

The TFT sections 3 and 4 are provided with a lower electrode wiring 34 serving as a gate electrode and a second insulating layer 2 serving as a gate insulating layer.
5, the semiconductor layer 26, and the upper electrode wiring 3 serving as a source electrode
5 and an upper electrode wiring 36 serving as a drain electrode.

In the matrix signal wiring section 5, the individual signal wiring 22 made of the first conductive layer, the insulating layer 25 covering the individual signal wiring 22, the semiconductor layer 26, the ohmic contact layer 27, and the individual signal wiring are formed on the substrate 10. The common signal wiring 37 made of the second conductive layer is sequentially stacked so as to cross the wiring. 38 denotes an individual signal wiring 22 and a common signal wiring 37
A contact hole 39 for making an ohmic contact with the capacitor 39 is a ground wiring of the storage capacitor unit 2.

In the wiring section 6 of the gate line for driving the TFT, the individual gate wiring 40 made of the first conductive layer 24, the insulating layer 25 covering the individual gate wiring 40, the semiconductor layer 26, the ohmic contact layer 27, and a common gate wiring 41 composed of the second conductive layer 28 is sequentially stacked so as to cross the individual gate wiring 40. Reference numeral 42 denotes a contact hole for making ohmic contact between the individual gate wiring 40 and the common gate wiring 41.

The common capacitor section 7 includes a lower electrode wiring 22 serving as an individual signal wiring, a first insulating layer 25 and a photoconductive semiconductor layer 26 formed on the lower electrode wiring 22, and a photoconductive semiconductor layer 26. And an upper layer electrode wiring 43 formed of the second conductive layer 28 formed thereon. The structure of the common capacitor unit 7 is the same as that of the MIS capacitor as the storage capacitor unit 2. Although either positive or negative bias conditions can be used, stable capacitance and frequency characteristics can be obtained by using the upper layer electrode wiring 43 in a state where it is always positively biased.

As described above, the photoelectric conversion device of this embodiment is
All of the photoelectric conversion element section, storage capacitor section, TFT section, matrix signal wiring section, gate drive wiring section, and common capacitor section have a laminated structure of a photoconductive semiconductor layer, an insulating layer, a conductor layer, and the like. They are formed simultaneously by the same process.

Further, on the second conductive layer 28, the passivation layer 11 made of SiN or the like for mainly protecting and stabilizing the semiconductor layer surfaces of the photoelectric conversion element portion 1 and the TFT portions 3 and 4, and the original P A friction-resistant layer 8 made of microsheet glass or the like is formed to protect the photoelectric conversion element and the like from friction.

Between the passivation layer 11 and the wear-resistant layer 8, an antistatic layer 15 made of a light-transmitting conductive layer is formed.

The antistatic layer 15 is composed of the original P and the wear-resistant layer 8.
It is arranged in order to prevent static electricity generated by friction with the negative electrode from adversely affecting the photoelectric conversion element and the like. Since the illumination light L and the signal light L ′ need to be transmitted as the material of the antistatic layer 15, an oxide semiconductor transparent conductive film such as ITO is used.

In this embodiment, the anti-abrasion layer on which the antistatic layer is formed is adhered on the passivation layer 11 by an adhesive layer.

In the present embodiment, a photoelectric conversion device for directly detecting the reflected light from the original without using the same-size fiber lens array or the like, that is, a so-called perfect contact type structure is adopted.
A system such as a facsimile can be made very compact, and the degree of freedom of a mechanical design in configuring the system is increased.

It goes without saying that the present invention can also be used for a contact reading type image reading apparatus using a 1: 1 fiber lens or the like.

FIG. 6 is a schematic configuration diagram showing an example of a facsimile having a communication function as an image information processing apparatus configured using the sensor unit according to the present embodiment.

Here, reference numeral 102 denotes a feeding roller as feeding means for feeding the original P toward the reading position;
Are separation pieces for reliably separating and feeding the documents P one by one. Reference numeral 106 denotes a platen roller which is provided at a reading position with respect to the sensor unit, regulates a surface to be read of the document P, and serves as a conveying means for conveying the document P.

In the illustrated example, PP is a recording medium in the form of a roll paper, in which image information read by a sensor unit or, in the case of a facsimile apparatus, image information transmitted from outside is reproduced. 110 is a recording head as recording means for performing the image formation,
Various types such as a thermal head and an ink jet recording head can be used. The recording head may be of a serial type or a line type. Reference numeral 112 denotes a platen roller as transporting means for transporting the recording medium P to a recording position of the recording head 110 and regulating the recording surface thereof.

Reference numeral 120 denotes an operation panel provided with switches and messages for accepting operation inputs as input / output means, and a display unit for notifying the status of the apparatus.

Reference numeral 130 denotes a system control board as control means, which includes a control unit (controller) for controlling each unit, a drive circuit (driver) for the photoelectric conversion element,
An image information processing unit (processor), a transmission / reception unit, and the like are provided. 140 is the power supply of the device.

As recording means used in the information processing apparatus of the present invention, for example, US Pat.
It is preferable that the typical structure and principle are disclosed in the specification of 4740796. According to this method, at least one of the electrothermal transducers corresponding to the recorded information and having a rapid temperature rise exceeding the nucleate boiling is applied to the electrothermal transducer disposed corresponding to the sheet or the liquid path holding the liquid (ink). By applying a drive signal, heat energy is generated in the electrothermal transducer, causing the film to boil on the heat-acting surface of the recording head. As a result, bubbles in the liquid (ink) corresponding to the drive signal one-to-one. Is effective because The growth of this bubble,
The liquid (ink) is discharged through the discharge opening by contraction to form at least one droplet.

Further, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, a combination of a plurality of recording heads as disclosed in the above specification is used. Either a configuration that satisfies the length or a configuration as one integrally formed recording head may be used.

In addition, the print head of the exchangeable chip type, which can be electrically connected to the apparatus main body and supplied with ink from the apparatus main body by being attached to the apparatus main body, or the print head itself has an ink The present invention is also effective when a cartridge type recording head provided integrally with a tank is used.

[0090]

As is apparent from the above description, according to the present invention, it is possible to obtain an original output voltage having no crosstalk in a block in which a black signal is increased by a white signal with a simple circuit configuration.

Therefore, in order to eliminate or reduce the crosstalk in the block conventionally performed, the cross portion capacitance CP is eliminated, or the ratio between the cross portion capacitance CP and the load capacitance CL is increased. No countermeasures are required. Therefore, the problems associated with these countermeasures, that is, a shield layer must be separately provided, the yield in manufacturing is reduced in order to reduce the cross-section capacitance CP by reducing the wiring width, or the load capacitance is reduced. The signal output voltage does not decrease due to the increase in CL.

Further, according to the present invention, even when the load capacitance CL is reduced, the original output voltage can be obtained. Therefore, by reducing the load capacitance CL as much as possible in terms of circuit formation, it becomes clear from the equation. In addition, a large output voltage can be obtained with a small input charge amount.

This indicates that it is possible to reduce the amount of electric charge generated by the optical sensor, and it is possible to use a low-sensitivity optical sensor, or to reduce the amount of incident light, that is, if the light source for illuminating the original has low luminance. Therefore, the photoelectric conversion device can be used at a low cost.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a photoelectric conversion device according to an embodiment of the present invention.

FIG. 2 is a simulation diagram illustrating crosstalk in a block of the photoelectric conversion device in FIG. 1;

FIG. 3 is a simulation diagram illustrating crosstalk in a block of the photoelectric conversion device in FIG. 1;

FIG. 4 is a schematic cross-sectional view of a photoelectric conversion unit according to the photoelectric conversion device of FIG.

FIG. 5 is a schematic plan view of a photoelectric conversion unit according to the photoelectric conversion device of FIG.

FIG. 6 is a schematic configuration diagram illustrating an example of a facsimile having a communication function as an image information processing device configured using the sensor unit according to the present embodiment.

FIG. 7 is an equivalent circuit diagram of a conventional photoelectric conversion device.

FIG. 8 is a timing chart for explaining the operation of the photoelectric conversion device shown in FIGS. 1 and 7;

FIG. 9 is a conceptual diagram for considering intra-block crosstalk.

FIG. 10 is a simulation diagram illustrating crosstalk in a block of a conventional photoelectric conversion device.

[Explanation of symbols]

S _1-1 to S _36-48 photoelectric conversion element C _S1-1 ~C _S36-48 storage capacitor T _1-1 through T _36-48 transfer TFT L ₁ ~L ₄₈ matrix signal wires R _1-1 to R _{36 -48} reset TFT C _{L1 to} C _L48 load capacitor T _{SW1 to} T _SW48 read switch U _{SW1 to} U _SW48 transfer switch C _{T1 to} C _T48 read capacitor V _SW reset switch SR1 shift register SR2 shift register R _{SW1 to} R _SW48 reset switch

Claims (1)

(57) [Claims] At least a plurality of optical sensors, first switch means for sequentially taking out output signals of the optical sensors as one block at a time, and signals of one block taken out by the first switch means Capacity value C for storing
_L , a first storage unit, a matrix connection unit connecting the first storage unit to the plurality of optical sensors, and a first block for sequentially extracting signals for one block stored in the first storage unit. A second switch means, and a second switch means for storing the signal for one block extracted by the second switch means.
In the photoelectric conversion device having a storage unit, a one electrode of at least the first storage means are connected one block, and connected through a common resistance of the resistance value R _COM at a constant potential, said first storage The product C _L · R _COM of the capacitance value C _{L of the} means and the resistance value R _COM of the common resistor is 5.0.
× 10 ⁻⁹ F · Ω or more.