JPH05166946A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an interlayer insulating film without inflicting damage on a gate oxide film and a capacitor dielectric film by a method wherein when the layer insulating film is formed by a plasma CVD method, a gate electrode and a capacitor electrode are kept electrically connecting with a substrate and after the layer insulating film is formed, the electrical connection is cut. CONSTITUTION:A first metallic wiring 17-1 is formed and thereafter, when the wiring 17-1 is etched, the electrical connection of a gate electrode 13-1 with a drain 14-2 or a source 14-1 and the electrical connection of the electrode 13-1 with a substrate 10 via a contact hole 16-3 are kept leaving without being cut. A layer insulating film 18 is formed on the whole surfaces of a BPSG film 15 and the wiring 17-1. At this time, as the potentials of the electrode 13-1, the source 14-1, the drain 14-2 and the substrate 10 are set at the same potential, damage is never inflicted on a thin gate oxide film. After this, a contact hole 19-1 and cut regions 19-2 and 19-3 of the wiring 17-1 are also opened, and the above electrical connections are cut.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to charge-up prevention in forming an insulating film between metal wiring layers by using plasma CVD.

[0002]

2. Description of the Related Art In a semiconductor device, particularly a semiconductor integrated circuit in which MOS transistors are integrated, two or more layers of metal wiring may be used. Plasma CVD is used to form an interlayer insulating film between two or more metal wiring layers. This is because the metal used for the wiring is mainly aluminum having a low melting point, and the plasma CVD can lower the formation temperature of the insulating film thereon, so that the wiring can be prevented from being damaged.

However, when the plasma CVD is used to form the insulating film after the metal wiring is thus formed, the electric charge on the metal wiring due to plasma (hereinafter referred to as charge-up) occurs. This charge-up may change the potential of the gate electrode or the capacitor electrode of the MOS transistor connected to the metal wiring, damage the gate oxide film or the dielectric film of the capacitor, or cause dielectric breakdown in the worst case. This is one of the factors that reduce the yield in the manufacture of semiconductor integrated circuits.

As means for solving such problems, there are a method of increasing the frequency of the plasma source, a method of optimizing the energy of plasma, a method of adjusting the gas flow rate to the reaction vessel, and the like. However, it is not a fundamental solution because there is a problem with the quality of the formed insulating film.

[0005]

As described above, in forming an insulating film after forming a metal wiring according to the prior art, the gate oxide film or the dielectric film of the capacitor may be damaged due to charge-up of the metal wiring, or in the worst case. Had the drawback of causing dielectric breakdown.

Therefore, an object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device which eliminates the above-mentioned defects and does not damage the gate oxide film or the dielectric film of the capacitor.

[0007]

In order to achieve the above object, in the present invention, a step of forming a first insulating film on a part of a surface region of a semiconductor substrate, and a step of forming a first insulating film on the first insulating film are performed. Forming a first wiring layer; depositing a second insulating film on the first wiring layer and on the semiconductor substrate; selectively removing the second insulating film; Forming a first contact hole reaching the wiring layer and a second contact hole reaching the semiconductor substrate, and on the second insulating film, in the first contact hole, and in the second contact hole. And a step of forming a second wiring layer, and plasma C on the second wiring layer and on the second insulating film.
Forming a third insulating film by a VD method, and selectively removing the third insulating film to electrically connect the first wiring layer of the second wiring layer to the semiconductor substrate A step of forming an opening larger than the wiring width of the second wiring layer on the region to be formed, and a step of removing the second wiring layer through the opening in a self-aligned manner. A method of manufacturing a semiconductor device is provided.

Further, a step of forming a first insulating film on a part of the surface region of the semiconductor substrate, a step of forming a first wiring layer on the first insulating film, and a step of forming the first wiring layer. A step of depositing a second insulating film on the semiconductor substrate and on the semiconductor substrate; and a first contact hole reaching the first wiring layer by selectively removing the second insulating film and reaching the semiconductor substrate. Forming a second contact hole, forming a third insulating film on a part of the second insulating film, and forming a second insulating film on the second insulating film, the third insulating film and the third insulating film. Forming a second wiring layer in the first contact hole and in the second contact hole; on the second wiring layer, on the second insulating film, and on the third insulating film And a step of forming a fourth insulating film by a plasma CVD method, and selectively removing the fourth insulating film An area that electrically connects the first wiring layer to the semiconductor substrate in the second wiring layer and is larger than the wiring width of the second wiring layer on the third insulating film. And a step of removing the second wiring layer in a self-aligned manner through the opening,
A method for manufacturing a semiconductor device, wherein the etching rate of the fourth insulating film is higher than that of the third insulating film.

Further, a step of forming a first insulating film on a part of the surface region of the semiconductor substrate, a step of forming a first wiring layer on the first insulating film, and a step of forming the first wiring layer. A step of depositing a second insulating film on the semiconductor substrate and on the semiconductor substrate; and a first contact hole reaching the first wiring layer by selectively removing the second insulating film and reaching the semiconductor substrate. A step of forming a second contact hole, a step of forming a semiconductor film on a portion of the second insulating film, a step of oxidizing the surface of the semiconductor film to form a third insulating film, A step of forming a second wiring layer on the second insulating film, on the third insulating film, in the first contact hole and in the second contact hole; and on the second wiring layer And plasma CVD on the second insulating film and the third insulating film.
Forming a fourth insulating film by a method, and selectively removing the fourth insulating film to electrically connect the first wiring layer of the second wiring layer to the semiconductor substrate A step of forming an opening portion that is a region and is larger than the wiring width of the second wiring layer on the third insulating film; and forming the opening portion of the second wiring layer on the third insulating film. And a step of removing the fourth insulating film in a self-aligned manner, the etching rate of the fourth insulating film being higher than that of the semiconductor film.

[0010]

According to such a method, after the metal wiring is formed,
The insulating film can be formed without damaging the gate oxide film or the dielectric film of the capacitor even by using plasma CVD which is a low temperature process. This is because the metal wiring layer is electrically connected to the semiconductor substrate, the source region, the drain region, the gate electrode, and the capacitor electrode, so that they have the same potential, and the gate oxide film sandwiched between these and the dielectric film of the capacitor. This is because there is no potential difference. Therefore, the gate oxide film and the dielectric film of the capacitor are not damaged or cause dielectric breakdown.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 to 3 are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1, the P-type silicon substrate 10 is selectively oxidized to form a film having a thickness of 5 in the element isolation region 10-1.
A silicon oxide film 11 of 00 nm is formed. Then P
Type silicon substrate 10 and gate oxide film 12 having a film thickness of 20 nm
Further, a polysilicon layer 13 having a film thickness of 300 nm is formed by the CVD method. After patterning with a photoresist, the polysilicon layer 13 is etched by the reactive ion etching method (hereinafter abbreviated as RIE method) using the photoresist as a mask to form the gate electrode 13-1 and necessary wiring. The substrate 10 is formed by the ion implantation method.
N-type impurities such as phosphorus and arsenic are implanted into the element region 10-2 using the gate electrode 13-1 and the like as a mask. Further, P-type impurities such as boron are implanted into the ground region 10-3 of the substrate 10. Subsequently, the source 14-1, the drain 14-2, and the ground portion 14-3 are formed by heat treatment. Next, substrate 1
A BPSG film 15 is formed on the entire surface of 0 by the CVD method.
After patterning with a photoresist, a contact hole 16 is formed in a boron-phosphosilicate glass (hereinafter abbreviated as BPSG) film 15 by RIE using this photoresist as a mask. In the conventional method, the contact hole 16-1 reaching the gate electrode 13 and the source 14-1
Or contact hole 16 reaching the drain 14-2
2 was formed, but in this embodiment, the contact hole 16-3 reaching the ground portion 14-3 is also formed. Then, the photoresist is removed.

Next, as shown in FIG. 2, a metal wiring layer 17 having a thickness of 800 nm, for example, an aluminum alloy wiring layer, is formed on the entire surface of the BPSG film 15 by a sputtering method. After coating a photoresist on the metal wiring layer and patterning it, the photoresist is used as a mask for etching by the RIE method to form the first metal wiring 17-1. Here, when the first metal wiring 17-1 is etched, electrical connection between the gate electrode 13-1 and the drain 14-2 or the source 14-1 and the gate electrode 13-1 and the contact hole 16-
The electrical connection with the substrate 10 via 3 is left uncut. After removing the photoresist, an interlayer insulating film 18 made of silicon oxide is formed on the entire surfaces of the BPSG film 15 and the first metal wiring 17-1 by the plasma CVD method. here,
Since the gate electrode 13, the source 14-1, the drain 14-2, and the substrate 10 are electrically connected and have the same potential, the thin gate oxide film is not damaged. Next, a photoresist is applied to the entire surface and patterned, and then a contact hole 19-1 is formed using this photoresist as a mask. At the same time when the contact hole 19-1 is formed, the cutting region 19 of the first metal wiring 17-1 is formed.
-2 and 19-3 are also opened. Here, the cutting area 19-2,
The opening diameter of 19-3 is set larger than the wiring width of the first metal wiring 17-1. [FIG. 4] is a plan view of the areas A to A ′ in FIG. 2 showing this state. Then, the photoresist is removed.

Next, as shown in FIG. 3, the interlayer insulating film 18 and the contact holes 19-1, 19-2, 19-3.
A metal wiring layer having a film thickness of 800 nm, for example, an aluminum alloy wiring layer, is formed on the entire surface by sputtering. After applying a photoresist on the metal wiring layer and patterning it, the second metal wiring 110 is formed by etching by the RIE method using this photoresist as a mask. At the same time, the cutting area 19
The first metal wirings 17 in -2 and 19-3 are also etched and removed from the openings in a self-aligned manner. Then, the cutting area 1
Since the opening diameters of 9-2 and 19-3 are set to be larger than the wiring width of the first metal wiring 17, the electrical connection between the gate electrode 13 and the drain 14-2 and the substrate 10 is cut off. A portion of the first metal wiring 17 including the ground portion 14-3 may be left as an inactive portion, but this may be used as a wiring element.

As a first embodiment, the MO is formed in the element region.
Although an S-transistor is formed, if the element has a thin oxide film that is easily damaged by plasma CVD,
M with floating gate like non-volatile memory
It may be an OS transistor, a capacitor used in a DRAM memory cell, or the like.

Further, although the ground portion 14-3 is formed in the region isolated by the selective oxidation method, a thick oxide film in the element isolation region may be formed by opening in order to prevent the inactive region from increasing.

Further, although the first embodiment shows the application to the two-layer metal wiring, it may be one-layer metal wiring or multi-layer metal wiring having three or more layers. In the case of two or more layers of metal wiring, the number of times of photo-etching does not have to be particularly increased as in the first embodiment, but when the present invention is used for more metal wiring, the number of times of photo-etching is increased. In the case of the single-layer metal wiring, unlike the first embodiment, the photo-etching process for opening the cutting region is slightly increased, but self-alignment is performed after the cutting region is opened without forming the second-layer metal wiring. RI metal wiring to
Remove with E etc.

Although the P-type silicon substrate is used in the first embodiment, an N-type silicon substrate may be used. In this case, the source and drain are implanted with P-type impurities and the ground region is doped with N-type impurities. inject. The same applies when the semiconductor element is composed of CMOS.

Further, in the first embodiment, impurities are introduced into the ground portion, but this is to reduce the contact resistance. If sufficient grounding can be obtained even if there is a resistance of about the Schottky barrier, the first metal wiring layer and the substrate may be directly contacted without introducing impurities into the grounding portion.

By the way, in the first embodiment, it is necessary to make the cutting regions 19-2 and 19-3 of the first metal wiring 17-1 larger than the wiring width of the first metal wiring 17-1 in order to cut the wiring. Although necessary, there is a risk that etching will proceed to a position below the first metal wiring 17-1 when the contact hole is formed in this portion. In order to prevent this, an etching stopper may be placed under the first metal wiring layer in the cut region. This is utilized in the second embodiment. A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described. [FIG. 5] to [FIG. 7] are cross-sectional views showing this manufacturing method in the order of steps.

As shown in FIG. 5, the P-type silicon substrate 20 is selectively oxidized to a film thickness of 500 n in the element isolation region 20-1.
m silicon oxide film 21 is formed. Subsequently, the entire surface of the P-type silicon substrate 20 is thermally oxidized to form the oxide film 2 having a film thickness of 20 nm.
2, a polysilicon layer 23 having a film thickness of 300 nm is further formed by the CVD method. After patterning with a photoresist, the polysilicon layer and the oxide film are etched by the RIE method using this photoresist as a mask to form the gate oxide film 2
2-1, the gate electrode 23-1, and necessary wiring are formed.
After removing the photoresist, the substrate 2 is formed by ion implantation.
N-type impurities such as phosphorus and arsenic are implanted into the element region 20-2 of 0 using the gate electrode 23-1 and the like as a mask. Further, P-type impurities such as boron are implanted into the ground region 20-3 of the substrate 20. Subsequently, these impurities are heat-treated to be in an electrically active state to form a source 24-1, a drain 24-2 and a ground section 24-3. Next, CV is applied to the entire surface of the substrate 10.
The BPSG film 25 is formed by the D method. Further BPSG
A polysilicon layer is formed on the entire surface of the film 25 by the CVD method, and the photoresist is patterned so as to leave only a predetermined region of the cut region of the first metal wiring to be formed later. The surface of the polysilicon layer is etched by dry etching using this photoresist as a mask, and then the polysilicon is thermally oxidized. In this way, the etching stopper 2
6 was formed. Next, after patterning with a photoresist on the BPSG film 25 and the etching stopper 26, B is formed by the RIE method using the photoresist as a mask.
Contact hole 27 reaching PSG film 25 to the gate electrode
-1, a contact hole 27-2 reaching the source 24-1 or the drain 24-2, and a contact hole 27-3 reaching the substrate 20 via the ground portion 24-3. Then, the photoresist is removed.

Next, as shown in FIG. 6, as in the first embodiment, a film thickness of 8 is formed on the entire surface of the BPSG film 25 by the sputtering method.
00 nm metal wiring layer 28, for example, aluminum alloy wiring layer,
To form. After coating a photoresist on the metal wiring layer and patterning it, the photoresist is used as a mask for etching by the RIE method to form the first metal wiring 28-1. Again, when the first metal wiring 28-1 is etched here, the gate electrode 23-1 and the drain 24-
2 and the electrical connection between the gate electrode 23-1 and the substrate 20 via the contact hole 27-3 is left uncut. After removing the photoresist, BP
An interlayer insulating film 29 made of silicon oxide is formed on the entire surfaces of the SG film 25 and the first metal wiring 28-1 by plasma CVD. Here, since the gate electrode 23-1, the source 24-1, the drain 24-2, and the substrate 20 are electrically connected and have the same potential, even if charge-up occurs during plasma CVD, thin gate oxidation is performed. Does not damage the film. Next, a photoresist is applied to the entire surface and patterned, and then a contact hole 210-1 is formed using this photoresist as a mask. At the same time when the contact hole 210-1 is formed, the first metal wiring 2 is formed.
The cutting areas 210-2 and 210-3 of 8-1 are also opened.
Here, the opening holes of the cutting regions 210-2 and 210-3 are made larger than the wiring width of the first metal wiring 28-1 and smaller than the etching stopper 26. FIG. 8 is a plan view of the B to B ′ region of FIG. 6 showing this. When hydrogen dilute carbon tetrafluoride is used as the etching gas for RIE, the layer formed of polysilicon and the silicon oxide film functions as an etching stopper. Therefore, unlike the first embodiment, etching does not proceed below the first metal wiring layer at the time of opening by etching. Then, the photoresist is removed.

After that, as shown in FIG. 7, the same steps as in the first embodiment are carried out. A film thickness of 800 n is formed on the entire surface of the interlayer insulating film 29 and on the first metal wiring 28-1 by the sputtering method.
A metal wiring layer of m, for example, an aluminum alloy wiring layer is formed. After applying a photoresist on the metal wiring layer and patterning it, the second metal wiring 211 is formed by etching by the RIE method using this photoresist as a mask. At this time, the first metal wiring 28-1 in the cutting regions 210-2 and 210-3 is also etched and removed at the same time. Therefore, the electrical connection between the gate electrode 23 and the drain 24-2 and the substrate 20 is cut off. Here, as in the first embodiment, the portion of the first metal wiring 28-1 including the grounding portion 24-3 may be left as an inactive portion, but this may be used as an element of the wiring.

As a second embodiment, MO is formed in the element region.
An S-transistor was formed, but like the first embodiment,
If the device has a thin oxide film, which is easily damaged by plasma CVD, it has an M with a floating gate.
It may be an OS transistor, a capacitor used in a DRAM memory cell, or the like.

Although the ground portion 24-3 is formed in the region isolated by the selective oxidation method, a thick oxide film in the element isolation region may be formed by opening in order to prevent the inactive region from increasing. Also, the second embodiment has shown the application to the two-layer metal wiring, but it may be one-layer metal wiring or multi-layer wiring having three or more layers.

Although the P-type silicon substrate is used in the second embodiment, an N-type silicon substrate may be used. In this case, the source and drain are implanted with P-type impurities and the ground region is doped with N-type impurities. inject. The same applies when the semiconductor element is composed of CMOS.

Also, in the second embodiment, impurities are introduced into the ground portion, but this is to reduce the contact resistance. If sufficient grounding can be obtained even if there is a resistance of about the Schottky barrier, the first metal wiring layer and the substrate may be directly contacted without introducing impurities into the grounding portion.

In the second embodiment, a film obtained by oxidizing the surface of polysilicon is used as the etching stopper. However, a nitride film or the like may be used as long as it has an inter-layer insulating film formed thereon and etching selectivity. An insulating film may be used. Further, high resistance polysilicon or the like may be regarded as an insulating film and used.

[0029]

As described above, according to the method of manufacturing a semiconductor device of the present invention, after the metal wiring is formed, the gate oxide film and the dielectric film of the capacitor are damaged even if plasma CVD which is a low temperature process is used. The insulating film can be formed without using. This is because the metal wiring layer is electrically connected to the semiconductor substrate, the source region, the drain region, the gate electrode, and the capacitor electrode, so that they have the same potential, and the gate oxide film sandwiched between these and the dielectric film of the capacitor. This is because there is no potential difference. Therefore, the gate oxide film and the dielectric film of the capacitor are not damaged or cause dielectric breakdown.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a plan view of a region AA ′ in FIG. 2;

FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 8 is a plan view of a B to B ′ area in FIG. 6;

[Explanation of symbols]

10, 20 P-type silicon substrate 10-1, 20-1 Element isolation region 10-2, 20-2 Element region 10-3, 20-3 Ground region 11, 21 Silicon oxide film 12-1, 22-1 Gate oxidation Films 13-1, 23-1 Gate electrodes 14-1, 24-1 Sources 14-2, 24-2 Drains 14-3, 24-3 Ground parts 15, 25 Insulating films 26 Etching stoppers 16, 27, 19-1 , 210-1 Contact hole 17-1, 28-1 First metal wiring 18, 29 Inter-layer insulation film 19-2, 19-3, 210-2, 210-3 First metal wiring cutting area 110, 211 Second metal wiring

Claims (3)

[Claims] 1. A step of forming a first insulating film on a part of a surface region of a semiconductor substrate, a step of forming a first wiring layer on the first insulating film, and a step of forming the first wiring layer. Depositing a second insulating film on the semiconductor substrate and on the semiconductor substrate, and selectively removing the second insulating film to reach the first wiring layer and reach the semiconductor substrate A step of forming a second contact hole, a step of forming a second wiring layer on the second insulating film, in the first contact hole, and in the second contact hole; Forming a third insulating film on the wiring layer and the second insulating film by a plasma CVD method, and removing the third insulating film selectively from the second wiring layer. The second wiring is provided on a region that electrically connects the first wiring layer and the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of forming an opening larger than a wiring width of a layer; and a step of removing the second wiring layer through the opening in a self-aligned manner. 2. A step of forming a first insulating film on a part of a surface region of a semiconductor substrate, a step of forming a first wiring layer on the first insulating film, and a step of forming the first wiring layer. Depositing a second insulating film on the semiconductor substrate and on the semiconductor substrate, and selectively removing the second insulating film to reach the first wiring layer and reach the semiconductor substrate Forming a second contact hole, forming a third insulating film on a portion of the second insulating film, forming a second insulating film on the second insulating film, the third insulating film, and the third insulating film. Forming a second wiring layer in the first contact hole and in the second contact hole; on the second wiring layer, on the second insulating film, and on the third insulating film And a step of forming a fourth insulating film by a plasma CVD method, and selectively removing the fourth insulating film. An area that electrically connects the first wiring layer to the semiconductor substrate in the second wiring layer and is larger than the wiring width of the second wiring layer on the third insulating film. And a step of removing the second wiring layer in a self-aligned manner through the opening, wherein the etching rate of the fourth insulating film is higher than that of the third insulating film. And a method for manufacturing a semiconductor device. 3. A step of forming a first insulating film on a part of a surface region of a semiconductor substrate, a step of forming a first wiring layer on the first insulating film, the first wiring layer Depositing a second insulating film on the semiconductor substrate and on the semiconductor substrate, and selectively removing the second insulating film to reach the first wiring layer and reach the semiconductor substrate Forming a second contact hole, forming a semiconductor film on a portion of the second insulating film, forming a third insulating film by oxidizing the surface of the semiconductor film, Forming a second wiring layer on the second insulating film, on the third insulating film, in the first contact hole and in the second contact hole, and on the second wiring layer And a fourth insulating film formed on the second insulating film and the third insulating film by a plasma CVD method. A step of forming a film, which is a region for electrically removing the fourth insulating film to electrically connect the first wiring layer to the semiconductor substrate in the second wiring layer, Forming an opening larger than the wiring width of the second wiring layer on the insulating film, and removing the second wiring layer on the third insulating film in a self-aligned manner through the opening. The method of manufacturing a semiconductor device, wherein: the etching rate of the fourth insulating film is higher than that of the semiconductor film.