JPH05160403A - Thin film transistor - Google Patents

Abstract

(57) [Summary] [Configuration] In a thin film transistor having a CMOS structure,
A thin film transistor in which the channel regions of the P-channel thin film transistor and the N-channel thin film transistor are formed to have a film thickness thinner than either the maximum width of the depletion layer of the P-channel thin film transistor or the maximum width of the depletion layer of the N-channel thin film transistor. [Effect] It is possible to construct a CMOS thin film transistor having a P-channel type thin film transistor and an N-channel type thin film transistor having the same characteristics and having a large ON current and a small OFF current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor in which a P channel type thin film transistor and an N channel type thin film transistor are integrated.

[0002]

2. Description of the Related Art In recent years, active research has been conducted on a technique for forming a thin film transistor on an insulating substrate. This technology is applied to an active matrix panel that realizes a high-quality thin display using an inexpensive transparent insulating substrate, a three-dimensional integrated circuit that forms active elements such as transistors on a normal semiconductor integrated circuit, or an inexpensive and high-performance integrated circuit. Many applications are expected, such as high-performance image sensors and high-density memory.

In some of these applications, basically, a thin film transistor is used only as a switching element, but it is desirable that a driving circuit required for the switching is simultaneously composed of a thin film transistor. For example, in an active matrix panel, a thin film transistor is arranged in each of the pixels arranged in a matrix to switch display data. At the same time, if the peripheral driving circuit can be integrated with the thin film transistor, the burden of mounting can be reduced and The cost and size of the entire system can be reduced. That is, it is necessary to form a logic circuit with thin film transistors.

In this case, a complementary structure (CMOS) is required more than in the case of a normal semiconductor integrated circuit. this is,
This is because, when a logic circuit is formed by thin film transistors, the number of elements is generally large, and power consumption becomes extremely large unless a complementary structure is used. For example, when a peripheral drive circuit of an active matrix panel is built in with thin film transistors, a number of shift registers, buffers, analog switches, etc. corresponding to the number of pixels are required.

Generally, a shift register of 500 stages or more must be built in. Further, it can be easily inferred that a large number of elements are required in the case of a three-dimensional integrated circuit, an image sensor, a high-density memory, or the like. When the number of elements is large as described above, it is extremely effective to make the thin film transistors have a complementary structure in order to reduce the power consumption. The complementary thin film transistor is composed of a P-channel thin film transistor and an N-channel thin film transistor. Of these thin film transistors,
Since one of them is always in the off state, a through current does not flow between the power supplies, and the power consumption can be significantly reduced.

However, the complementary thin film transistor has the following drawbacks, and has not been sufficiently studied so far.

(1) The manufacturing method is complicated because both the P-channel type and the N-channel type are integrated.

(2) Along with this, the manufacturing cost is high.

(3) The characteristic balance of the thin film transistor is sufficient.

(4) It is difficult to match the characteristics of the P-channel type thin film transistor and the characteristics of the N-channel type thin film transistor.

(5) In order to have these characteristics, it is necessary to add extra steps such as adding appropriate impurities to the channel portion.

Due to these drawbacks, complementary thin film transistors have not reached the level of practical use.

[0013]

SUMMARY OF THE INVENTION The present invention is intended to eliminate such drawbacks all at once, and an object of the present invention is to provide a P-channel type having excellent characteristics and a small characteristic difference. It is an object to provide a complementary thin film transistor including an N-channel thin film transistor at a low cost by a simple manufacturing method.

[0014]

According to the present invention, the channel region is formed of a non-doped silicon thin film, and the conductivity type of the silicon thin film in the source / drain regions is P type or N type. A complementary thin film transistor, which is a thin film transistor; and silicon thin films in the channel regions of the two types of thin film transistors, which are formed in the same layer, and the thickness of the silicon thin film is the same as that of the two types of thin film transistors. It is intended to provide a complementary thin film transistor characterized by being thinner than the maximum width of any depletion layer that can be formed on the surface of a silicon thin film.

[0015]

Example 1 Hereinafter, a complementary thin film transistor characterized in that a channel region is formed of a non-doped silicon thin film and a P-channel type or an N-channel type thin film transistor is realized depending on the conductivity type of a source / drain will be described. A detailed description will be given based on an example.

FIG. 1 is a sectional view showing the structure of a complementary thin film transistor according to the present invention. 101 is glass, quartz,
An insulating substrate such as a semiconductor integrated circuit substrate including a passivation film, on which a P-channel thin film transistor 1 is formed.
02 and the N-channel type thin film transistor 103 are formed to form a complementary type thin film transistor. 10
Reference numeral 4 is a channel region of a P-channel type thin film transistor made of a non-doped silicon thin film. Reference numeral 105 is a source region made of a P-type silicon thin film doped with an acceptor such as boron, and 106 is a drain region similarly configured. 107 is a gate insulating film such as Sio _2.
08 is a gate electrode made of polycrystalline silicon, metal, or the like, 109
Is an interlayer insulating film such as Sio ₂ . Reference numerals 110 and 111 are made of a conductor such as metal, and are a source electrode and a drain electrode, respectively. Reference numeral 112 is a channel region of an N-channel thin film transistor made of a non-doped silicon thin film. Reference numeral 113 is a source region made of an N-type silicon thin film doped with a donor such as phosphorus or arsenic, and 114 is a similarly configured drain region. 115 is a gate insulating film, 116 is a gate electrode, 117 is a source electrode, 118
Is a drain electrode.

As is apparent from this figure, the present invention uses both non-doped silicon thin films as the channel regions of P-channel type and N-channel type thin film transistors.
Further, basically, the P-channel thin transistor and the N-channel thin film transistor are characterized by being distinguished only by the conductivity type of the source / drain regions.

The effects of the present invention realized by these features will be described below.

The effect of using non-doped silicon thin films as the channel regions of the P-channel type and N-channel type thin film transistors will be described.

By using a non-doped silicon thin film, that is, a silicon thin film close to an intrinsic semiconductor, as a channel region of both types of thin film transistors, a leak current (hereinafter referred to as O
It is possible to minimize the FF current). In a normal transistor using single crystal silicon, a P-type substrate for an N-channel type and an N-type substrate for a P-channel type are used to form an extremely good PN junction, so that an OFF current between a source and a drain is reduced. Although it has been reduced, generally, a silicon thin film on an insulating substrate cannot be single-crystallized and becomes a polycrystalline state or an amorphous state.
No junction can be formed and therefore the OFF current cannot be reduced.

FIG. 2 is data of an experiment conducted by the present applicant and is a graph showing the relation between the impurity concentration in the silicon thin film in the channel region of the N-channel thin film transistor and the OFF current. The impurity is boron, which is intended to make the channel region P-type. The doping is performed by an ion implantation method, the horizontal axis of the graph is the doping amount of boron, and the vertical axis is the OFF current at a gate voltage of 0V. As can be seen from this graph, the OFF current becomes the minimum when the doping amount is 0, that is, when the non-doped silicon thin film close to the intrinsic semiconductor is used. This is because the leak current of the PN junction increases as the impurity concentration increases. On the contrary, when the channel region is N-type, it goes without saying that the transistor becomes a depletion type and the OFF current increases. Therefore, the OFF current becomes the minimum when the non-doped silicon thin film is used. That is, in order to reduce the OFF current, it is effective to increase the resistance value of the channel region as much as possible rather than using a PN junction as in a transistor using single crystal silicon. Although the above description has been made for the N-channel thin film transistor, the same holds true for the P-channel thin film transistor. Therefore, in both types of thin film transistors, the OFF current can be minimized by using the non-doped silicon thin film in the channel region.

Next, a P-channel type thin film transistor and N
The effect of distinguishing the channel type thin film transistor only by the conductivity type of the source / drain regions will be described. Thereby, the manufacturing process of the complementary thin film transistor can be significantly simplified. Therefore, it is possible to significantly improve the yield and reduce the cost. FIG. 3 is a diagram showing an example of a method of manufacturing the complementary thin film transistor shown in FIG.

First, as shown in FIG. 3A, the insulating substrate 30
After depositing the non-doped silicon thin films 302 and 303 on the substrate 1, a desired pattern is formed. A P-channel thin film transistor is formed at 302 and an N-channel thin film transistor is formed at 303. Next, as shown in FIG. 3B, the gate insulating film 304 is formed by thermally oxidizing the non-doped silicon thin films 302 and 303. Alternatively, the gate insulating film may be deposited on the outside by a vapor phase growth method or the like. After that, by depositing the gate electrode 305,
A desired pattern is formed. Of course, different gate electrode materials may be used for the P-channel thin film transistor and the N-channel thin film transistor, such as P-type silicon thin film and N-type silicon thin film.

Next, as shown in FIG. 3C, a mask material 306 such as a photoresist is formed in a region to be an N-channel thin film transistor, and an acceptor element 307 such as boron is ion-implanted into the P-channel thin film transistor. A P-type silicon thin film which becomes the source region 308 and the drain region 309 is formed by doping the inside. Further, as shown in FIG. 3D, similarly, a mask material 310 such as a photoresist is formed in a region to be a P-channel type thin film transistor, and a donor element 3 such as phosphorus or arsenic 3 is formed.
11 is doped into the N-channel type thin film transistor by the ion implantation method to form an N-type silicon thin film to be the source region 312 and the drain region 313. Finally, as shown in FIG. 3E, after depositing an interlayer insulating film 314, a contact hole is opened, and a source electrode 315 and a drain electrode 316, N of a P-channel thin film transistor are formed.
The source electrode 317 and the drain electrode 318 of the channel thin film transistor are formed, and the complementary transistor is completed.

As can be seen, the complementary thin film transistor according to the present invention can be manufactured by a very simple method.
This is because both the P-channel type thin film transistor and the N-channel type thin film transistor use a non-doped silicon thin film as a channel region. Therefore, it is not necessary to use an N-type substrate for the P-channel transistor and a P-type substrate for the N-channel transistor, unlike the conventional complementary transistor. That is, it is not necessary to change the conductivity type of the channel region in the two types of transistors.

As a result, it is possible to omit the step of adding impurities to the channel region of each transistor and forming the necessary pattern. In addition, each transistor is separated in an island shape on the insulating substrate, and no special element separation process is required. Further, along with this, there is no parasitic MOS effect as in a normal semiconductor integrated circuit, and it is not necessary to form a channel stopper.
For these reasons, in the thin film transistor according to the present invention, P-channel type and N-channel type thin film transistors can be realized only by changing the conductivity type of the source / drain regions. Therefore, the manufacturing process thereof is extremely simple as compared with the conventional complementary transistor. For example, the number of pattern formation steps is 10 or more in the conventional complementary transistor, but only 6 in the complementary transistor according to the present invention. The fact that the manufacturing process can be simplified in this way has a great effect that the manufacturing cost can be reduced and the manufacturing yield can be improved, and a significantly low cost can be achieved as a whole.

(Embodiment 2) In the present invention, the silicon thin films in the channel regions of both the P-channel type thin film transistor and the N-channel type thin film transistor are formed of the same layer, and the thickness of the silicon thin film is set to the above two types. The present invention also provides a complementary thin film transistor, which is characterized in that it is thinner than the maximum width of any depletion layer that can be formed on the surface of the silicon thin film of the above thin film transistor, which will be described in detail below based on examples.

FIG. 4 is a sectional view showing the vicinity of the channel region of the complementary thin film transistor according to the present invention. Figure 4
4A shows a P-channel thin film transistor, and FIG. 4B shows an N-channel thin film transistor.
On the insulating substrate 401, source regions 402 and 408, drain regions 403 and 409, gate insulating films 404 and 410,
A thin film transistor having gate electrodes 405 and 411 is formed. The non-doped silicon thin films 406 and 412 in the channel region are composed of the same layer and therefore have the same film thickness tsi. Although the depletion layers 407 and 413 spread on the surface of the silicon thin film with the application of the gate voltage, the width χP of the depletion layer in the P-channel thin film transistor and the width χN of the depletion layer in the N-channel thin film transistor are respectively expressed by the following equations. Given in.

[0029]

[Equation 1]

Here, q is the unit charge amount, ε is the dielectric constant of the silicon thin film, φs is the bending amount of the energy band on the surface of the silicon thin film, ND is the secret of the trap which acts as a donor equivalently, and NA is the acceptor equivalently. It is the density of the trap that acts as. As described above, the silicon thin film is in a polycrystalline or amorphous state and has many crystal defects, and this acts as a trap. In the energy band diagram, the trap forming a level between the Fermi level and the conduction band acts as a donor, and the trap forming a level between the Fermi level and the valence band acts as an acceptor. The level of each trap is determined by the arrangement of silicon atoms, and is generally ND
And NA are not equal.

FIG. 4 shows the case where ND is larger than NA, and therefore χP is smaller than χN. When the gate voltage is further increased, the spread width of each depletion layer reaches the maximum value, and the inversion layer starts to be formed on the surface of the silicon thin film. The gate voltage at this time is the threshold voltage, and even if the gate voltage is further increased, the depletion layer does not spread anymore, and the carrier density in the inversion layer only increases. Maximum width of depletion layer χPmax and χNm in P-channel and N-channel thin film transistors
The ax and the threshold voltages VthP and VthN are given by the following equations.

[0032]

[Equation 2]

Here, φfP and φfN are Fermi energies in P-channel and N-channel thin film transistors, Cox is a gate insulating film capacitance per unit area, and VFB is a flat band voltage.

In the complementary thin film transistor according to the present invention, the silicon thin film tsi is formed by the above χPmax and χNma.
It is configured to be smaller than any of x.

The effects of the present invention realized by this will be described below.

When the film thickness (tsi) of the silicon thin film is smaller than the maximum width (χPmax and χNmax) in which the depletion layer can spread, the depletion layer cannot spread beyond tsi. Therefore, when the depletion layer width reaches tsi, an inversion layer is immediately formed on the surface of the silicon thin film. That is, the threshold voltage of the transistor is reduced. Normally, since there are extremely high density traps in the silicon thin film, the threshold voltage becomes high,
According to the present invention, the driving voltage of the thin film transistor can be lowered by reducing the threshold voltage, and the current (ON current) flowing when the transistor is in the on state can be increased. Therefore, the thin film transistor can be easily used and a higher speed operation is possible.

The threshold voltage at this time is given by the following equation.

[0038]

[Equation 3]

In the case of the example in FIG. 4, ND> NA and χP <χN
Is. Therefore, when tsi is reduced, the threshold voltage of the N-channel thin film transistor starts to decrease earlier than that of the P-channel thin film transistor. However, when tsi is further reduced to fall within the film thickness range provided by the present invention, the difference in threshold voltage between the P-channel thin film transistor and the N-channel thin film transistor becomes small. This state is shown in FIG. The horizontal axis is tsi, and the vertical axis is the absolute value of the threshold voltage. Reference numeral 501 is an N-channel thin film transistor, and 502 is a P-channel thin film transistor. As can be seen from this graph, the threshold voltages of the two approaches rapidly in the region where tsi is smaller than χPmax. This is because in the above equation, ND is larger than NA, and thus the tsi dependence of the threshold voltages of the two transistors is different. Therefore, according to the present invention, it becomes possible to bring the threshold voltages of the P-channel type and N-channel type thin film transistors close to each other and reduce the characteristic difference. This has a great effect on the complementary transistor.

Although the above description has been made on the assumption that ND> NA, the same holds true for NA <ND.

(Embodiment 3) FIG. 6 shows another embodiment of the present invention. The P-channel type thin film transistor 616 and the N-channel type thin film transistor 6 are formed on the insulating substrate 601.
17 is formed and constitutes a complementary thin film transistor. Reference numeral 602 is a gate electrode, 603 is a gate insulating film, and 604 is a channel region of a P-channel thin film transistor made of a non-doped silicon thin film. 60
Reference numeral 5 is a source region made of a P-type silicon thin film doped with an acceptor such as boron, and 606 is a drain region similarly configured. 607 is an interlayer insulating film,
Reference numeral 608 is a source electrode and 609 is a drain electrode. 6
Reference numeral 10 is a gate electrode, and 611 is a channel region of an N-channel thin film transistor made of a non-doped silicon thin film. Reference numeral 612 denotes a source region formed of an N-type silicon thin film doped with a donor such as phosphorus or arsenic.
Reference numeral 3 is a drain region having the same structure. 614 is a source electrode and 615 is a drain electrode.

As is apparent from the figure, all the effects of the present invention described above are also established in this embodiment. That is, even if the channel region is located on the gate electrode, or the silicon thin film of the source / drain region is formed of a layer different from the silicon thin film of the channel region, or the incidental structure is changed, the present invention can be realized. However, the same effect can be obtained.

[0043]

As described above, according to the present invention, since the threshold voltage is low, the ON current is large and the OFF current is small, and the P-channel type and N-channel type thin film transistors having uniform characteristics are used. It has many excellent effects of providing a complementary thin film transistor at low cost by a simple manufacturing method.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment showing the manufacture of a complementary thin film transistor according to the present invention.

FIG. 2 is a graph showing the relationship between the impurity concentration in the channel region and the OFF current.

3A to 3E are views showing a method of manufacturing the complementary thin film transistor according to the present invention shown in FIG.

4A and 4B are diagrams showing the vicinity of a channel region of a thin film transistor according to the present invention.

FIG. 5 is a graph showing the relationship between the film thickness of the silicon thin film in the channel region and the threshold voltage.

FIG. 6 is a diagram showing a second embodiment showing the structure of a complementary thin film transistor according to the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9056-4M H01L 29/78 311 H

Claims (1)

[Claims] 1. A P-channel type thin film transistor having source and drain regions doped with P type impurities formed on a substrate, and an N channel having source and drain regions doped with N type impurities. A channel type thin film transistor, and a film thickness of a channel region of the P channel type thin film transistor and the N channel type thin film transistor is a maximum width of a depletion layer of the P channel type thin film transistor or a depletion layer of the N channel type thin film transistor. A thin film transistor, which is formed to be thinner than any of the maximum widths in which it can spread.