JPH05160163A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device having a transistor in which a channel layer is thin and carrier concentration is increased. A quantum well structure having a first semiconductor layer as a quantum well layer and a second semiconductor layer as a semiconductor barrier layer, a first semiconductor layer as a channel layer, and a first semiconductor layer as a
A semiconductor device having one atomic layer of impurity atoms. A first semiconductor layer made of In _X Ga _1-X As, if the value of x is 0.05 through 0.25, the layer of impurity atoms may be one atomic layer or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure suitable for a GaAs / InGaAs field effect transistor (FET).

[0002]

2. Description of the Related Art A semiconductor device having a heterojunction FET using a conventional (Al, In, Ga) As-based crystal is disclosed in Proceedings of IDM 88,
(1988) pp. 692-695 (IEDM8
8, pp 692-695). This ultra high-speed FET has a high concentration (3 × 10 ¹⁸ cm ~ ³ ) in the GaAs layer.
Heterostructure Insulated-Gate Filtration Transistor (HIGFET; Hetero-structure Insulated-Gate Fis)
Eld Effect Transistor), gate length 0.3μm
In the case of, the conductance resistance (hereinafter, referred to as K value) was 6.5.

[0003]

In the above-mentioned prior art, since the GaAs layer uniformly doped with Si is used as the n-type channel layer, the carrier concentration of the channel is 6 × 10 ^18.
It will not be activated if it exceeds about cm ~ ³ . Further, when the thickness of the channel layer is reduced, a sufficient carrier concentration cannot be obtained. Therefore, there is a problem that a transistor having a high K value cannot be obtained.

An object of the present invention is to provide a semiconductor device having a transistor having a thin channel layer and an increased carrier concentration.

[0005]

Means for Solving the Problems The above-mentioned objects are (1) first
In the semiconductor device having a quantum well structure in which the semiconductor layer is a quantum well layer and the second semiconductor layer is a semiconductor barrier layer, and the first semiconductor layer is a channel layer, the first semiconductor layer is an impurity. (2) A semiconductor device having one atomic layer of atoms, (2) In the semiconductor device according to the above-mentioned 1, the position of the one atomic layer of the impurity atom is the second semiconductor from the center of the first semiconductor layer. (3) The semiconductor device according to the above 1 or 2, wherein the first semiconductor layer is In _X G
a _1-x As and the second semiconductor layer is made of GaAs or Al _y Ga _1-y As. (4) The semiconductor device according to the above 3,
The value of x of _X Ga _1-X As is in the range of 0.05 to 0.25, (5) In the semiconductor device according to the above 3 or 4, the impurity atom is Si
(6) The above-mentioned 1, 2
Or in the semiconductor device according to 3, the impurity atom is n
Type impurity atoms, and a p-type semiconductor layer is further provided in contact with the first semiconductor layer,
(7) In the semiconductor device according to any one of 1 to 6 above, the first semiconductor layer and the second semiconductor layer are
A semiconductor device having lattice constants different from each other; (8) a quantum well structure in which the first semiconductor layer is a quantum well layer and the second semiconductor layer is a semiconductor barrier layer; In a semiconductor device having a semiconductor layer as a channel layer,
The first semiconductor layer is made of In _X Ga _{1 -X} As, and the value of x is in the range of 0.05 to 0.25. Further, the first semiconductor layer has an impurity atom between them. (9) A semiconductor device having a layer, (9) In the semiconductor device described in (8), the layer of the impurity atoms has a thickness of 10 Å or less, (10) The above-mentioned item (8) or (9). In the semiconductor device according to the above item 11, the first semiconductor layer and the second semiconductor layer have different lattice constants from each other, (11) In the semiconductor device according to the above 8 or 9, the impurity atom Is Si
(12) A first semiconductor layer is provided as a quantum well layer on a substrate, and a second semiconductor layer is provided as a semiconductor barrier layer on one side of the first semiconductor layer. A third semiconductor layer is provided as a semiconductor barrier layer on the other side of the first semiconductor layer to form a quantum well structure, and the first semiconductor layer has one atomic layer of impurity atoms. , And the second semiconductor layer has a lattice constant different from that of the first semiconductor layer, and the third semiconductor layer has a lattice constant equal to that of the first semiconductor layer. the semiconductor device characterized by having, (13) in the semiconductor device of the above 12, wherein said first semiconductor layer is a semiconductor device characterized by comprising the _{in X Ga 1-X as,} (14) above 13, wherein Of the above In _X Ga _1-X As The value of x in the semiconductor device is in the range of 0.05 to 0.25. (15) In the semiconductor device described in 13 or 14, the impurity atom is Si. It is achieved by the semiconductor device.

In the present invention, the layer of impurity atoms may be a partial two-atom layer, or even a part in which no impurity atom exists may be one atomic layer on average. When the material described in the above item 8 is used, it may have one atomic layer or more. N-type F as an impurity atom
It is preferable to use Si, Se, Sn, S, Te or the like when forming the ET, and Be, C or the like when forming the p-type FET.

[0007]

[Operation] In FIG. 1, GaAs (3000 Å) / In _x Ga
₁ × 10 Si atoms are formed on one atomic plane at the center of the quantum well layer of the quantum well structure composed of _1-x As (film thickness d) / GaAs.
The relationship between the film thickness and the sheet carrier concentration when ¹³ cm ^{2 is} added is shown. In composition ratio x of the In _x Ga _1-x As at this time is 0.2. As is clear from FIG. 1, the sheet carrier concentration increases as d increases. For GaAs (that is, when d = 0), the sheet carrier concentration is 4 × 10.
¹² cm to ² but 6.8 × 10 ^{12 for} In _x Ga _1-x As
The activation rate increases up to cm ~ ² .

FIG. 2 shows the dependence of the sheet carrier concentration on the atomic plane position where Si is added. GaAs (thickness 3000
Å) semiconductor barrier layer 12, GaAs (thickness 500
The quantum well layer 11 made of In _x Ga _1-x As (thickness 100 Å) having an In composition ratio of 0.2 is inserted between the semiconductor barrier layers 10 made of 0 Å), and Si (N _Si =
A sample obtained by atomic layer doping of 1 × 10 ¹³ cm ² is shown. The positions of the atomic layer-doped surface are the position A (the center of the quantum well layer 11), the position B (the position 50 Å from the interface of the semiconductor barrier layer 12), and the position C (the position 50 Å from the interface of the semiconductor barrier layer 10). ).

The sample at the position A is 5.5 × 1 as shown in FIG.
A sheet carrier concentration of 0 ¹² cm- ² was obtained, at position B 6.6 × 10 ¹² cm- ² and at position C 6.2 × 10 ¹²
The activation was even higher at cm- ² .

As described above, a high-concentration channel can be obtained by doping the channel of the HIGFET with a Si atomic layer, and a higher-concentration channel can be obtained by controlling the position of the atomic layer-doped surface.

Further, in FIG. 6, undoped GaAs / In
_X Ga _1-X As (thickness 100 Å) / undoped GaAs structure, In composition ratio in the case of atomic layer doping of Si with a sheet carrier concentration of 1 × 10 ¹³ cm to ² in the central portion of the In _X Ga _1-X As layer And the sheet carrier concentration and electron mobility are shown. The sheet carrier concentration increases with the In composition ratio, and the mobility decreases conversely.

FIG. 7 shows the In composition ratio dependence of the sheet resistance in the same sample as that shown in FIG. The sheet resistance shows a low value in the In composition range of 0.05 to 0.25, and sharply increases when the In composition is less than 0.05 and exceeds 0.25.

An atomic layer-doped structure is used for the quantum well layer as the channel of the FET, and In _X Ga _1-X As is used as the material.
6 is used, the In composition is 0.05 or more and GaA
A high-concentration channel can be obtained as compared with the s channel, and the parasitic resistance can be reduced by selecting the In composition of 0.05 to 0.25 from FIG.

[0014]

EXAMPLE 1 A sectional view of a semiconductor device according to an example of the present invention is shown in FIG.
First, a method of manufacturing this semiconductor device will be described. Semi-insulating GaAs substrate 1 by molecular beam epitaxy (MBE) method
A buffer layer 2 (thickness 3000 Å) made of undoped GaAs and a semiconductor barrier layer 3 made of p-type GaAs
(Thickness 2900Å, p-type impurity Be, impurity concentration 3 × 1
0 ¹⁶ cm to ³ ), a p-type semiconductor layer 4 ′ made of p-type In _0.2 Ga _0.8 As (thickness 100 Å, p-type impurity Be), a quantum well layer 4 made of undoped In _0.2 Ga _0.8 As (thickness 1
00Å) and a semiconductor barrier layer 5 (thickness 100Å) made of undoped Al _0.3 Ga _0.7 As. The Si atomic layer-doped surface 20 is provided while interrupting the growth of the quantum well layer 4.
This position was 50 Å directly under the semiconductor barrier layer 5.
Further, the sheet carrier concentration at this time is 5 × 10 ¹² cm to ²
Met. In addition, In re-evaporation during InGaAs growth,
The growth temperature was 500 ° C. in order to suppress the diffusion of Si.

Furthermore, a portion corresponding to the ohmic region is removed by etching by a normal photolithography process, and a high concentration n-type InGaAs is selectively removed at the portion removed by metalorganic chemical vapor deposition (MOCVD).
Layer 6 was grown epitaxially. Then, the source electrode 7 and the drain electrode 8 were formed using AuGe type alloy through a photolithography process and a vapor deposition process. further,
A gate portion was formed by electron beam drawing, and Ti / Al was deposited to form a gate electrode 9. Gate length is 0.3μ
m. In the HIGFET thus obtained, since the high concentration thin film channel was used, the K value of the transistor characteristic was 14.

Embodiment 2 FIG. 4 shows a sectional view of a semiconductor device according to a second embodiment of the present invention. By the MBE method, the buffer layer 2 made of undoped GaAs and the p-type GaAs are formed on the semi-insulating GaAs substrate 1.
Composed of a semiconductor barrier layer 3 (thickness 3000 Å, p-type impurity Be, impurity concentration 3 × 10 ¹⁶ cm ³ ), undoped In
_0.1 Ga quantum well layer 4 made of _0.9 As (thickness 100
Å), and the semiconductor barrier layer 5 (thickness 150 A) made of undoped Al _0.3 Ga _0.7 As is sequentially epitaxially grown. The Si atomic layer-doped surface 20 was provided at the center of the quantum well layer 4 by interrupting the growth thereof. At this time, the sheet carrier concentration was set to 5 × 10 ¹² cm- ² . Epitaxial growth and atomic layer doping were performed at a substrate temperature of 500 ° C.

Further, a portion corresponding to the ohmic region was removed by etching by a normal photolithography process, and a high concentration n-type InGaAs layer 6 was selectively epitaxially grown on the portion removed by the MOCVD method. Then, the source electrode 7 and the drain electrode 8 were formed using AuGe type alloy through a photolithography process and a vapor deposition process. Further, a gate portion was formed by electron beam drawing, Ti / Al was vapor-deposited to form a gate electrode 9, and a FET was produced. The gate length of the transistor is 0.3μ
m. In the above transistor, a high-concentration channel can be manufactured and parasitic resistance can be suppressed, so that the K value of the transistor characteristic was 14.

Embodiment 3 FIG. 5 shows a sectional view of a semiconductor device according to a third embodiment of the present invention. This embodiment is the third embodiment of the second embodiment, which is composed of p-type In _0.1 Al _0.9 As between the semiconductor barrier layer 3 and the quantum well layer 4.
The semiconductor layer 13 (thickness 100 Å) is inserted.

The method of manufacturing the transistor is the same as that of the second embodiment except that the third semiconductor layer 13 is formed. In this embodiment, the high-concentration n-type InGaA formed by selective growth is used.
Since the s layer 6 has the same composition of In _0.1 Ga _0.9 As as the quantum well layer 4, epitaxial growth can be performed on the third semiconductor layer 13 with lattice matching. For this reason,
The stress on the end face of the channel layer was relieved, and the reliability of the transistor was improved. Although the above-mentioned embodiments describe the case of the n-type FET, similarly, Be or C (carbon) can be added as the p-type impurity to form the p-type FET.

[0020]

According to the present invention, it is possible to form a high concentration thin film channel by atomic layer doping of impurities.
The K value of ET was improved about twice as much as the conventional one. Also,
In composition ratio of 0.0 as a layer forming a channel of FET
When In _x Ga ₁ -x As of 5 to 0.25 was used, the activation rate of atomic layer-doped Si was high and a high concentration channel could be formed. Further, as a layer that constitutes the channel of the FET, In _x Ga _{1 -x} A with an In composition ratio of 0.25 or less is used.
When s was used, the mobility did not decrease so much, the sheet resistance did not increase, and a transistor with low parasitic resistance was realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a film thickness of an InGaAs layer and a sheet carrier concentration.

FIG. 2 is a diagram showing an atomic plane for atomic layer doping.

FIG. 3 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an In composition ratio of an In _X Ga _1-X As layer, a sheet carrier concentration, and an electron mobility.

FIG. 7 is a diagram showing the In composition ratio dependence of the sheet resistance of an In _X Ga _1-X As layer.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 buffer layer 3, 5, 10, 12 semiconductor barrier layer 4, 11 quantum well layer 4'p type semiconductor layer 6 high concentration n type InGaAs layer 7 source electrode 8 drain electrode 9 gate electrode 13 third Semiconductor layer 20 Si atomic layer doped surface

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeyuki Hiruma 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (15)

[Claims] 1. A semiconductor device having a quantum well structure in which a first semiconductor layer is a quantum well layer and a second semiconductor layer is a semiconductor barrier layer, and the first semiconductor layer is a channel layer. The semiconductor device of 1 has a 1 atomic layer of an impurity atom, The semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the position of one atomic layer of the impurity atoms is closer to the interface side with the second semiconductor layer than the central portion of the first semiconductor layer. A semiconductor device characterized by. 3. The semiconductor device according to claim 1, wherein the first semiconductor layer is made of In _X Ga _{1 -X} As.
The semiconductor device, wherein the second semiconductor layer is made of GaAs or Al _y Ga _1-y As. 4. The semiconductor device according to claim 3, wherein the value of x of In _X Ga _1-X As is in the range of 0.05 to 0.25. 5. The semiconductor device according to claim 3, wherein the impurity atom is Si. 6. The semiconductor device according to claim 1, wherein the impurity atom is an n-type impurity atom, and a p-type semiconductor layer is provided in contact with the first semiconductor layer. Semiconductor device. 7. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer have different lattice constants from each other. 8. A semiconductor device having a quantum well structure in which a first semiconductor layer is a quantum well layer and a second semiconductor layer is a semiconductor barrier layer, and the first semiconductor layer is a channel layer. The first semiconductor layer is made of In _X Ga _1-X As, the value of x is in the range of 0.05 to 0.25, and the first semiconductor layer is a layer of impurity atoms between them. A semiconductor device comprising: 9. The semiconductor device according to claim 8, wherein the layer of the impurity atoms has a thickness of 10 Å or less. 10. The semiconductor device according to claim 8 or 9, wherein the first semiconductor layer and the second semiconductor layer have different lattice constants from each other. 11. The semiconductor device according to claim 8 or 9, wherein the impurity atom is Si. 12. A first semiconductor layer is provided as a quantum well layer on a substrate, and a second semiconductor layer is provided as a semiconductor barrier layer on one side of the first semiconductor layer, and the first semiconductor layer is provided. Third quantum semiconductor layers are provided as semiconductor barrier layers on the other side to form a quantum well structure, and the first semiconductor layer has one atomic layer of impurity atoms and constitutes a channel layer. The second semiconductor layer has a lattice constant different from that of the first semiconductor layer, and the third semiconductor layer has a lattice constant equal to that of the first semiconductor layer. .. 13. The semiconductor device according to claim 12,
The first semiconductor layer is a semiconductor device characterized by comprising the In _X Ga _1-X As. 14. The semiconductor device according to claim 13,
The value of x of In _X Ga _1-X As is 0.05 to 0.2.
A semiconductor device having a range of 5. 15. The semiconductor device according to claim 13, wherein the impurity atom is Si.