JP2708492B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a heterojunction, and more particularly to a method for manufacturing a field effect transistor having a small parasitic resistance.

[Conventional technology]

In recent years, in AlGaAs / GaAs superlattices, the Japanese Journal of Applied Physics, 11
(1985) pages 1498 to 1502 (Jpn. J. Appl. Vol. 24,
As discussed in No. 11, pp. 1498 to 1502), it is known that impurity ion implantation causes interdiffusion between Al and Ga to cause disorder.

[Problems to be solved by the invention]

The above-mentioned prior art causes disorder due to ion implantation. For example, when applied to a field-effect transistor, it is difficult to form a shallow n-type region. Has also been diffused, making it difficult to control the threshold value.

An object of the present invention is to provide an electronic device, particularly a field-effect transistor, without disordering a channel portion.
It is to selectively disorder only the ohmic region having a heterojunction.

[Means for solving the problem]

The object of the present invention is to provide a semiconductor device, comprising: a semiconductor substrate having a third III-V semiconductor layer having an impurity concentration higher than the first and second III-V semiconductor layers and a third III-V semiconductor layer; Forming a first, second and third group III-V semiconductor layers in this order under the condition that the forbidden band width is different from that of the third and third group III-V semiconductor layers; III
A third III before or during the formation of the group V semiconductor layer;
A step of forming an atomic layer dope composed of impurity atoms of the group-V semiconductor layer, a step of selectively removing the third group III-V semiconductor layer and a part of the atomic layer dope, and after the step of selectively removing, The method can be achieved by a method of manufacturing a semiconductor device including a step of disordering by a heat treatment between the third III-V semiconductor layer which remains selectively and the second III-V semiconductor layer. For example, in a method of manufacturing a field-effect transistor having a Si-doped GaAs / AlGaAs heterostructure, the Si concentration of the Si-doped GaAs layer forming the ohmic region is increased relative to the Si concentration of the channel portion, and the Si-doped GaAs is further increased. Si in the lower part of the layer (in the layer or at the interface with the lower layer)
And heat treatment.

[Action]

The operation of the present invention will be described with reference to FIGS. 1 (a) to 1 (c). Molecular beam epitaxy (MBE) on GaAs substrate 1
Undoped GaAs2, AlGaAs3, and Si-doped GaAs4 are sequentially epitaxially grown by using the MOCVD method or the MOCVD method (FIG. 1A). At this time, the Si-doped GaAs layer 4
An atomic layer doping of Si is applied to the lower part in the inside (not shown). 1B, the Si-doped GaAs layer 4 and a part of the atomic layer doping of Si are selectively removed by dry etching, and then an SiO ₂ film 5 is deposited. Next, moving to FIG. 1 (c), when heat treatment is performed,
Are diffused into AlGaAs3 and the disordered region 6
Is formed. For reference, FIG. 2 shows the relationship between the Si concentration of the Si-doped GaAs layer 4 and the thickness of the disordered region 6 when heat treatment is performed at 700 ° C. for 3 hours without performing atomic layer doping.

5 × 10 ¹⁸ cm ^{−3 for} the Si-doped GaAs layer 4 and 2 × 1 for the AlGaAs layer 3
When doped with ¹⁸ cm ⁻³ Si, the thickness of 6 is formed to be about 50 nm, but almost no disorder occurs at the interface between 3 and 2 because the Si concentration is low. This achieves selective disordering of only six. This utilizes an increase in disorder due to an increase in the Si concentration, selectively disordering only the hetero interface in the heavily doped region and causing contact attributable to band discontinuity ΔE _c at the hetero interface. This is to reduce the resistance ρ _c .

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Reference Example 1 First, as Reference Example 1 of the present invention, a case in which atomic layer doping is not performed will be described with reference to FIGS. 3 (a) to 3 (d). As shown in FIG. 3A, an undoped GaAs layer 12 (500 nm thick) is formed on a semi-insulating GaAs substrate 11 by MBE.
m), undoped Al _0.3 Ga _0.7 As layer 13 (thickness 6 nm), Si-doped AlGaAs layer 14 (thickness 35 nm, Si concentration 2.4 × 10 ¹⁸ cm ⁻³ ), undoped Al _0.3 Ga _0.7 As layer 15 (thickness 10 nm) ), Si-doped n
^{A + −} GaAs layer 16 (160 nm thick, Si concentration 5 × 10 ¹⁸ cm ⁻³ ) is sequentially epitaxially grown. Next, an SiO ₂ film 17 (thickness: 20 nm) is deposited by a vapor phase growth method (CVD method), and then a photomask 18 for performing a recess etching for forming a gate electrode is formed. 3 (b), the SiO ₂ film 17 is removed by a CF ₄ -based reactive ion etching (RIE) method.
The n ⁺ -GaAs layer 16 is removed by RIE using Cl ₂ F ₂ gas.

Subsequently, after removing the photomask 18 and the SiO ₂ 17 all,
The SiO ₂ film 19 (20 nm) is deposited again by the CVD method. Next, referring to FIG. 3C, after the crystal surface is protected by the SiO ₂ film 19, a heat treatment is performed at 700 ° C. for 3 hours in a H ₂ gas flow. 700
If the heat treatment is performed at a high temperature higher than ℃, it will be less than 1 hour,
For protection of the channel portion, a lower heat treatment is preferable.

When the heating is performed at a high temperature of 800 ° C. or more, a so-called rapid thermal annealing method of lamp heating is preferably used. By heat treatment of the by Si diffusion from the n ⁺ -GaAs layer 16, disordered layer 20 is formed, the hetero interface between the n ⁺ -GaAs layer 16 and the undoped Al _0.3 Ga _0.7 As layer 15 is disordered. If the n ⁺ -GaAs layer 16 is doped with 8 × 10 ¹⁸ cm ⁻³ of Si, the hetero interface between undoped Al _0.3 Ga _{0.7 As} 13 and undoped GaAs 12 can be disordered. Next, referring to FIG. 3 (d), AuGe combined electrodes 100 and 100 'serving as source / drain electrodes are formed using photolithography. Further, Al is deposited and lifted off as a gate electrode material to form the gate electrode 101, and the field effect transistor is completed. In this FET structure, the contact resistance between the n ⁺ -GaAs layer 16 and the undoped Al _0.3 Ga _0.7 As layer 15 is about 1 /
It became 10.

Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. 4 to 4D. As shown in FIG. 4 (a), a semi-insulating GaAs substrate 21 is formed.
Be doped GaAs layer 22 (thickness 500 nm, Be concentration 3 × 10 ¹⁶ cm ⁻³ ), Si doped GaAs layer 23 (thickness 35 nm, Si concentration 1.5 × 10 ¹⁸ cm ⁻³ ), undoped Al _0.3 Ga _0.7 As layer 24 (thickness 15 nm), undoped GaAs layer 25 (thickness 5 nm), Si-doped A
l _0.3 Ga _0.7 As layer 26 (5 nm thick, Si concentration 3.5 × 10 ¹⁸ cm ^-3 ), S
An i-doped GaAs layer 27 (5 nm thick, Si concentration 5 × 10 ¹⁸ cm ⁻³ ) is sequentially laminated. At this time, the lower layer in the Si-doped GaAs layer 27
Is applied. The doping level is about 1 × 10 ¹³ cm ⁻² (corresponding to 1 × 10 ¹⁹ cm ⁻³ or more).

Furthermore, an SiO ₂ film 28 (200 nm thick) and a photomask 29 for recess etching are formed on the crystal surface.

4 (b), the SiO ₂ film 28 is removed by CF ₄ -based RIE, and then the Si-doped GaAs layers 27 and 30 are removed by RIE using CCl ₂ F ₂ gas.

Further, by immersing in J100, Si-doped Al _0.3 Ga
_{The 0.7} As layer 26 and the photomask 29 are removed.

Next, moving to FIG. 4 (c), after removing the SiO ₂ 28,
An SiO ₂ film 31 (thickness: 200 nm) is deposited on the entire surface. Further, the entire sample was heat-treated by the same method as that shown in Reference Example 1,
The disordered layer 32 is formed. Atomic layer doping allows disordering at relatively low temperatures.

4 (d), the source / drain electrodes 33 and 33 'and the gate electrode 34 are formed in exactly the same steps as in Reference Example 1 to complete the field effect transistor. this
In the FET, between layers 27 and 26, between layers 26 and 25, and layers 25 to 24
Since the hetero interface between the layers 24 and 23 was disordered, the contact resistance formed by these hetero interfaces was reduced, and was reduced to 1/10 or less of the structure without disorder.

[Effects of the Invention] According to the present invention, for example, 2DEG (Two-Dimentional Elec)
tron Gas) FET and HIGFET (Hetero Insulated gat)
In e), since a disordered region can be formed at a low temperature of 700 ° C. or less only in a predetermined region after crystal growth, the contact resistance at the hetero interface can be reduced, and there is no variation between wafers and high throughput. Can form a disordered layer.

In addition, by controlling the annealing temperature and the Si concentration, the diffusion distance of Si can be easily controlled, so that there is an effect of suppressing the short channel effect in the field effect transistor.

[Brief description of the drawings]

1 (a) to 1 (c) are cross-sectional views for explaining the operation of the present invention, FIG. 2 is a diagram showing the relationship between the Si concentration and the thickness of the disordered layer, and FIG. 3A to 3D are cross-sectional views of Embodiment 1 of the present invention, and FIGS. 4A to 4D.
FIG. 1 is a sectional view of a first embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... substrate 2 ... undoped GaAs layer 3 ... AlGaAs
Layer, 4 ... Si-doped GaAs layer, 5 ... SiO ₂ film, 6 ... disordered layer, 11 ... semi-insulating GaAs substrate, 12 ... undoped Ga
As layer, 13 ... undoped Al _0.3 Ga _0.7 As layer, 14 ... Si doped AlGaAs layer, 15 ... undoped Al _0.3 Ga _0.7 As layer, 16 ...
Si-doped GaAs layer, 17, 19 ... SiO ₂ film, 18 ... photomask, 20 ... disordered layer, 100, 100 '.... source and drain electrodes, 101 ... gate electrode, 21 ... semi-insulating GaAs substrate, 22 ... Be-doped GaAs layer, 23 ... Si-doped GaAs layer, 24
…… undoped Al _0.3 Ga _0.7 As layer, 25… undoped GaAs
Layer, 26 ... Si-doped Al _0.3 Ga _0.7 As layer, 27 ... Si-doped Ga
As layer, 28, 31 ... SiO ₂ film, 29 ... photomask, 30 ... electron layer doping region, 32 ... disordered layer, 33, 33 '...
Source / drain electrodes, 34 ... gate electrodes.

Continuing on the front page (72) Inventor Osamu Kagaya 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-187667 (JP, A)

Claims (3)

(57) [Claims] An impurity concentration of a third III-V semiconductor layer on a semiconductor substrate is higher than an impurity concentration of the first and second III-V semiconductor layers, and the third III-V semiconductor layer is Under the condition that the semiconductor layer and the second III-V semiconductor layer have different band gaps, the first, second, and third semiconductor layers are different.
Forming a III-V semiconductor layer in this order;
Forming an atomic layer dope comprising impurity atoms of the third III-V semiconductor layer before or during the formation of the third III-V semiconductor layer; and forming the third III-V semiconductor layer. Selectively removing a layer and a part of the atomic layer doping, and the third III-V semiconductor layer and the second III-V semiconductor selectively remaining after the selective removing step. A method for manufacturing a semiconductor device, comprising a step of disordering layers by heat treatment. 2. The semiconductor device according to claim 1, wherein said second III-V semiconductor layer is AlGaA.
2. The method according to claim 1, wherein s is used, GaAs is used as the third group III-V semiconductor layer, and Si is used as the impurity to be added. 3. The method according to claim 2, wherein the concentration of Si added to the third group III-V semiconductor layer is 5 × 10 ¹⁸ cm ⁻³ or more.