JP2514948B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device using a heterojunction, and particularly to a method suitable for a field effect transistor having a small parasitic resistance.

[Conventional technology]

In recent years, regarding AlGaAs / GaAs superlattices, as discussed on pages 25 to 33 of the material of the 13th research conference of Optical Technology Joint Research Institute, Optical Application System Technology Research Association It is known that when injected and heat-treated, the hetero interface is broken and the superlattice is disordered. this is,
It is considered to be caused by mutual diffusion of Ga and Al due to the diffusion of Si.

[Problems to be solved by the invention]

Since the above-mentioned conventional technique uses Si ion implantation, HEMT ( H
When applying the igh E lectron M obility T ransistor) or MESFET, there is liable to occur a so-called short channel effect.

The object of the present invention is to reduce the parasitic resistance by disordering the hetero interface without using ion implantation,
In addition, it is to manufacture a transistor with a short channel effect.

[Means for solving problems]

The above-mentioned object is a method for manufacturing a semiconductor device having a step of laminating a plurality of semiconductor layers including a heterojunction on a semiconductor substrate, wherein a cap layer pattern having a different coefficient of thermal expansion from that of the substrate semiconductor material is predetermined. A step of selectively forming a heterojunction on a disordered semiconductor region, and thermally distorting the semiconductor layer stacked under the cap layer pattern to selectively disorder the heterojunction region corresponding to the pattern And a heat treatment step for producing the semiconductor device.

As shown in Table 1, the coefficient of thermal expansion is based on GaAs Materials that form a cap layer pattern remarkably with the plate include SiO ₂ and Si ₃ N ₄ as insulating film materials and Si as semiconductor materials. To form the cap layer pattern, these materials are Ga
It can be easily formed by forming a film on the AlGaAs / GaAs hero junction layer laminated on the As substrate and selectively etching it by a known pattern forming method, for example, dry etching. After that, when heat treatment is performed in AsH ₃ , the cap layer pattern causes thermal strain in the laminated crystal below, and as a result, the hetero interface under the pattern region is disordered, but the exposed portion on the substrate ( Under the region where the cap layer pattern is removed), the hetero interface is retained and selective disordering is achieved.

[Action]

When a material having a coefficient of thermal expansion significantly different from that of the GaAs substrate shown in Table 1 is formed as a cap layer pattern on a semiconductor layer having a heterojunction and heat treatment is performed, thermal strain occurs on the substrate side. In Fig. ₂ , materials with different thermal expansion coefficients (SiO ₂ , SiN, Si) are selectively formed on the AlGaAs / GaAs heterojunction layer.
2 when formed as a cap layer and heat treated in AsH ₃
Characteristic curves 12 and 13 show profiles of Ga and Si in the depth direction by secondary ion mass spectrometry. The characteristic curve 10 in FIG. 2 is a profile of Al in the case where the cap layer pattern is not formed on the uppermost GaAs substrate, and the interface with GaAs is steep. Characteristic curve 11 in Fig. 2 shows the cap layer
This is a region where SiO ₂ is formed, Al is diffused, and the hetero interface is disordered. Therefore, selective disordering is performed, and since ions are not implanted as in the prior art, almost no Si diffusion occurs as shown in the characteristic curve 13. Here, disordered means that Al inter-diffuses with Ga of the adjacent GaAs layer, as shown in curve 11, to cause Al in the GaAs layer that does not originally contain Al.
Is present, the crystal structure does not change, but the composition of the crystal layer has changed. By changing the energy gap based on this disorder, a semiconductor device with reduced parasitic resistance and less short channel effect is realized.

〔Example〕

An embodiment of the present invention will be described below with reference to the sectional process drawing of FIG. In this embodiment, the case of a GaAs / AlGaAs heterojunction crystal is described, but other InP, InGaAs, InAlAs,
It can also be applied to compound semiconductor materials such as InGaAsP.

1 (a) to 1 (c) show the manufacturing process of the embodiment. First, in FIG. 1A, an undoped GaAs layer 2 (film thickness 0.5 μm) and an undoped AlGaA are formed on a semi-insulating GaAs substrate 1 by molecular beam epitaxy or metal organic chemical vapor deposition.
s3 (60 Å), n-type AlGaAs layer 4 (300 Å), n-type GaAs layer 5 (200
Å) is laminated.

Next, moving to FIG. 1B, a SiO ₂ film or SiN film 6 is deposited as a cap layer on the entire surface of the substrate by a thermal decomposition chemical vapor deposition method, a sputtering method or a plasma induced chemical vapor deposition method. Next, using the photoresist as a mask, the cap layer 6 is selectively removed by reactive ion etching,
The cap layer pattern 6 as shown in the drawing is formed by leaving it only in the ohmic region of the transistor. Next, heat treatment is performed at 900 ° C. for 30 seconds in an AsH ₃ + H ₂ mixed gas atmosphere. This time,
Only the heterojunction portion 7 below the cap layer 6 is selectively disordered, and the heterojunction 7a of the portion 5a not covered by the cap layer 6 is retained.

Next, moving to Fig. 1 (c), AuGe is formed in the disordered region 7.
Source / drain electrodes 8 formed by lift-off of alloy
Then, Al is similarly formed in the region 7a where the heterojunction is held by the lift-off method to form the gate electrode 9 to complete the modulation-doped field effect transistor.

When the characteristics of the field-effect transistor completed in this way and the conventional non-disordered transistor are compared, the conventional one has a parasitic resistance of transistor width w = 10 μm.
Although it was 60 Ω per unit, it decreased to 20 Ω in this example. Also, as a short channel effect, when the conventional gate length is reduced from Lg = 1 μm to 0.5 μm, the threshold voltage Vth
Shifted to a negative value of about 0.4V, but in this embodiment it is 0.05V.
It became extremely small.

〔The invention's effect〕

According to the present invention, the hetero interface can be selectively disordered without performing ion implantation, so that the parasitic resistance in the ohmic region can be reduced and a transistor without a short channel effect can be manufactured.

[Brief description of drawings]

1 (a), (b) and (c) are sectional views of an embodiment of the present invention, and FIG. 2 is a depth profile profile of Ga, Al and Si by secondary ion mass spectrometry. . 1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs, 3 ...
… Undoped AlGaAs, 4 …… n-type AlGaAs, 5 …… n-type Ga
As, 6 ... Insulating film, 7 ... Hetero interface.

Claims (5)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising a step of laminating a plurality of semiconductor layers including a heterojunction on a semiconductor substrate, wherein a cap layer pattern having a coefficient of thermal expansion different from that of a substrate semiconductor material is predetermined. Selectively forming the heterojunction on a disordered semiconductor region, and thermally distorting the semiconductor layer stacked under the cap layer pattern to selectively disorder the heterojunction region corresponding to the pattern. A method for manufacturing a semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the semiconductor is composed of a compound semiconductor, and the cap layer pattern is composed of a thin film pattern made of at least one of an insulator, a metal and a semiconductor. Manufacturing method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the cap layer pattern is a thin film pattern made of at least one of SiO ₂ , Si ₃ N ₄ and Si. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of selectively disordering only the ohmic region of the active element having the heterojunction. . 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a field effect transistor.