JPH05158820A - Bus controlling system - Google Patents

Abstract

PURPOSE:To surely detect the fault of a two-way control circuit, and to prevent the two-way buses of two or more processors from turning to an output side at a time by detecting that the switching signal of the two-way bus becomes faulty in a sub-processor, and turning the two-way bus of that processor to an input side by that output. CONSTITUTION:The output of an IO control register (CRG) 20 is inputted to a timing register (TMR) 23, and next, the output of the TMR 23 is inputted to the TMR 24, and when both these outputs are '1', it is detected as the fault by a NAMD circuit 25. By inputting a signal detected by the NAMD circuit 25 to an AND circuit 26, the enable of a two-way buffer (BUF) 21 is suppressed, and the BUF 21 is turned to the state of an IN side. Next, when the two-way switching signal becomes faulty, the fault is detected by the TMRs 23 and 24 when the two-way switching signals of channel controllers (CHU) 2 to 5 become '1' extending over two or more clocks, and the two-way switching signals are turned to '0' 3-clocks after that. Thus, heat generation in an IC can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system, and more particularly to a bus control system for bidirectionally controlling a bus when a bidirectional bus control signal fails.

[0002]

2. Description of the Related Art Generally, a bidirectional bus is used for data transfer between a plurality of processing devices, and is an effective means for transmitting / receiving data between the processing devices with one interface.

FIG. 4 is a block diagram showing an example of a conventional bidirectional bus control system. In FIG. 4, the information processing system of this example comprises one input / output processing unit (hereinafter, IOP) 10 and four channel processing units (hereinafter, CHU) 22 to 25, and data of each CHU 22 to 25 is transmitted via a bidirectional bus. Had been transferred. The bidirectional control of the processing device is performed by the IOP 10, which comprises a 3-bit +1 counter circuit (CNT) 102 and a decode circuit (DEC) 103 which receives the output of the CNT 102 as an input. IOP10
In the bidirectional control, the least significant bit of the CNT 102 is input to the enable of the bidirectional buffer (hereinafter, BUF) 101.
Each of the CHUs 22 to 25 inputs the output of the DEC 103 into the IO control register (hereinafter CRG) 202 via the transmission register (hereinafter RG) 104 to 107 and BU outputs the output.
It controls F201.

FIG. 5 is a time chart for explaining the operation in FIG. When the input / output enable 101a of the IOP 10 is "1", the BUF 101 is input (hereinafter referred to as I
N) side, and when it is "0", it is set to the output (hereinafter OUT) side. The CHUs 22 to 25 set the BUF 201 to the OUT side when the CRG 202 is "1" and set the IN side when the CRG 202 is "0". The ICP 10 repeats transmission / reception every clock and each C
The HUs 22 to 25 transmit data once every eight clocks. When the bidirectional control circuit and the bidirectional control signal fail, a parity error occurs due to data competition between the processing devices, thereby detecting the failure. However, since the error cannot be identified as a failure of the bidirectional control circuit and the bidirectional control signal, the failure data was collected without doing anything at the time of detection, and then the processing device that detected the error was reset.

[0005]

In this conventional bus control method, a parity error does not always occur, and even if it occurs, it cannot be immediately identified as a bidirectional control error. Until the failure information is collected, when the bidirectional switching signal (GR202 output) is left at "1" as shown in FIG. 5, the bus of one processing unit becomes the input side and the other One or more of the processing devices in the above are left on the output side. Therefore, a load is applied to the data bus of the processing device on the input side, and the processing device generates heat. As a result, there is a problem that the processing device may be destroyed by heat.

[0006]

According to the bus control method of the present invention, data is transferred between one main processing unit and at least one sub processing unit by a bidirectional bus, and the main processing unit and each of the sub processing units are connected. In a bus control method of an information processing system in which transmission / reception instructions are alternately given to a processing device at regular intervals, a bidirectional control circuit failure causes the bidirectional bus in the processing device to remain facing the output side. And a bus switching means for directing the bidirectional bus of the processing device to the input side when the failure is detected.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the bus control system of the present invention.

In FIG. 1, this embodiment comprises one input / output processing unit (hereinafter IOP) 1 and four channel processing units (hereinafter CHU) 2 to 5.

The IOP 1 is a BUF 11, a CNT 12 formed of a 3-bit register, a DEC 13 for decoding the output of the CNT 12, and a bidirectional switching instruction signal for sending bidirectional switching instruction signals a, ~ d to each CHU 2, ~ 5. Registers (hereinafter SWR) 14, 17 and IOP1 and CHU2
5 to 5, a bidirectional data bus e. Also each CHU
The CRG 20 (for example, CHU 2) receives the bidirectional switching instruction signal a from the SWR 14, and a timing register (hereinafter TMR) 23 that receives the output of the CRG 20 as an input.
TMR24 that receives the output of TMR23 and TMR2
3 and the TMR 24 both output "1" when the NAND circuit 25 outputs "0" and the NAND circuit 25 outputs both the detection signal 201a and CRG22 "1" outputs "1". Consists of.

Next, the operation of this embodiment will be described.
FIG. 2 is a time chart during normal operation of this embodiment,
FIG. 3 is a time chart when the bidirectional switching instruction signal fails in this embodiment.

During normal operation, as shown in FIG.
2 always counts up by +1 and the output signal controls the bus. The output signal 101a of the least significant bit of the CNT12 enables the DEC and the enable for switching the BUF11.
13 enable is input. The enable of the BUF11 faces the OUT side when it is "0", and faces the IN side when it is "1". When the DEC 13 is enabled, all outputs are set to "0" when it is "0", and when it is "1", the upper 2 bits of the CNT 12 are input and decoded. The output of the DEC 13 is taken into the SWRs 14 to 17. The output bidirectional switching instruction signals a, ~ d are CRGs in CHU2, ~ 5.
It is taken in by 22 and its output is inputted to the enable of the BUF 21 through the AND circuit 26. BUF21 is C
When the RG 22 is "1", it faces the OUT side, and when it is "0", it faces the IN side. The output of the CRG 22 is input to the TMR 23 at the same time, the output of the TMR 23 is input to the TMR 24 next, and when both are "1", the NAND circuit 25 detects the failure. The signal detected by the NAND circuit 25 is input to the AND circuit 26 to inhibit the enable of the BUF21,
Set the UF21 to the IN side. Next, as shown in FIG. 3, when the bidirectional switching signal fails, when the bidirectional switching instruction signal of CHU2 to 5 becomes "1" for 2 clocks or more, T
The failure is detected by the MRs 23 and 24, and the bidirectional switching signal is set to "0" three clocks later.

[0012]

As described above, according to the bus control method of the present invention, it is detected that the switching signal of the bidirectional bus has failed in the sub processing unit, and the output thereof is used to output the bidirectional bus of the processing unit. By setting the input side, the failure of the bidirectional control circuit can be reliably detected, and the bidirectional buses of two or more processing devices can be prevented from becoming the output side at the same time. It has the effect of suppressing the destruction of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus control system of the present invention.

FIG. 2 is a time chart during normal operation of this embodiment.

FIG. 3 is a time chart when a bidirectional switching instruction signal fails in this embodiment.

FIG. 4 is a block diagram showing an example of a conventional bidirectional bus control system.

5 is a time chart for explaining the operation in FIG.

[Explanation of symbols]

1, 10 Input / output control device (IOP) 2, ~ 5, 22, ~ 25 Channel control device (CH
U) 11, 21, 101, 201 Bidirectional buffer (BU
F) 12,102 +1 counter circuit (CNT) 13,103 decoding circuit (DEC) 14, to 17 bidirectional switching instruction register 20, 202 IO control register (CRG) 23, 24 timing register (TMR) 25 NAND circuit 26 AND circuit

Claims (1)

[Claims] 1. A bidirectional bus is used to transfer data between one main processing device and at least one sub processing device, and a transmission / reception instruction is fixed from the main processing device to each sub processing device. In a bus control method for an information processing system that alternates at intervals, a detection means for detecting that the bidirectional bus in the processing device remains facing the output side due to a failure of the bidirectional control circuit; And a bus switching means for directing the bidirectional bus of the processing device to the input side when the bus control method is detected.