JPH05289896A - Fault tolerant computer - Google Patents

Abstract

PURPOSE:To reduce a hardware of a snooper, and to simplify the monitoring operation by switching a system bus monitored by the snooper with a switching circuit. CONSTITUTION:Before a fault is detected in a data exclusive bus 003, a code 602 and data 603 pass through a code exclusive bus 002 and the data exclusive bus 003, respectively, and a snooper 103 monitors the data 603 on the data exclusive bus 003. After a fault is detected in the data exclusive bus 003, both a code 604 and data 605, 606 pass through the code exclusive bus 002. A switching circuit 105 switches monitoring of the snooper 103 from the data exclusive bus 003 to the code exclusive bus 002. The snooper 103 executes monitoring of the bus only when the data 605 and 600 flow on the code exclusive bus 002. That is, in the case of fault of the code exclusive bus 002, the data exclusive bus 003 is monitored, and in the case of a fault of the data exclusive bus 003, the code exclusive bus 002 is monitored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault tolerant computer aiming at, for example, 24/7 operation.

[0002]

2. Description of the Related Art FIG. 6 shows, for example, US Pat.
FIG. 54 illustrates a conventional fault tolerant computer shown at 54. In the figure, the processor modules 100 and 200 and the memory module 001 are connected to the system buses 002 and 003, and the processor module 100 is a processor 101 and a cache memory 10.
2 and the bus interface 104. Each processor module uses an empty system bus,
Even if an error occurs in one bus, it is designed with fault tolerance so that the other bus can handle the error. This fault tolerant computer builds a multiprocessor system that performs exclusive control.

However, when constructing a multiprocessor system in which this fault tolerant computer does not perform exclusive control, the consistency of the cache memory must be maintained. FIG. 7 is a diagram showing a fault-tolerant computer assuming a multiprocessor system that does not perform exclusive control. 001,002,003,10
Reference numerals 0, 101, 102, 104 and 200 are the same as those of the conventional device. Reference numerals 103a and 103b are snoopers that monitor the system buses 002 and 003, respectively.

In FIG. 7, the processor module 10
0 uses system bus 002, snooper 10
3a monitors the system bus 002, and when the processor module 100 uses the system bus 003, the snooper 103b monitors the system bus 003. In this example, it is necessary to provide the same number of system busts corresponding to one to one for a plurality of system buses.

[0005]

In the fault tolerant computer, since the system buses 002 and 003 operate independently, two snoopers are required for each system bus, and there is a drawback that the amount of hardware is large. It was Further, since it is necessary to control the two snoopers, there is a drawback that the monitoring operation becomes complicated and it is difficult to increase the speed.

It is an object of the present invention to provide a fault tolerant computer which can reduce the increase in the amount of hardware even if there are a plurality of system buses and can simplify the monitoring operation.

[0007]

A fault-tolerant computer of the present invention serves as a common path for transferring information between a memory module (storage device) for storing information and a memory module and a processor module (processing means). A processor module (processing means) having a plurality of system buses and the following elements is provided. (A) a processor (arithmetic unit) that processes information; (b) a number of snoopers less than the number of system buses that monitor the plurality of system buses; (c) a bus that the snooper should monitor between the snoopers and the system buses. (D) A switching control unit that performs error check of information transferred from the system bus and switches the switching circuit according to the situation.

[0008]

In the fault tolerant computer of the present invention, the system bus monitored by the snooper can be switched by providing the switching circuit, so that one snooper is not required for each system bus. Therefore, the snooper hardware can be made smaller,
Since the monitoring operation can be simplified, speeding up is easy.

[0009]

【Example】

Example 1. FIG. 1 is a diagram showing an embodiment of a fault tolerant computer according to the present invention, in which 001 is a memory module, and system buses 002 and 003 are connected to the memory module, and the processor module 100 and the processor are connected from the respective system buses. Module 200 is connected. Processor module 100
Comprises a processor 101 and a cache memory 102,
Reference numeral 103 is a snooper, and 105 is a switching circuit that selects a bus monitored by the snooper 103. A bus interface 104 checks the information transferred from the system bus and switches the switching circuit according to the result. 1
Reference numerals 11, 112, 113 and 114 represent internal buses.

FIG. 2 is a block diagram of the switching circuit 105 shown in FIG. Reference numeral 301 is a switching control circuit for selecting a bus monitored by the snooper 103, and reference numerals 302 and 303 are tristate buffers. 311 is a data discrimination control signal that is output to indicate that the processor 101 sends data to the internal bus 111. 312 is a data detection control signal. When the bus interface 104 detects a bus failure of the system buses 002 and 003, the failure is detected. Is an error bus discrimination signal that is transmitted to the switching control circuit 301.

FIG. 3 shows the bus interface 104 in FIG.
It is a block diagram of. Reference numeral 401 is a bus control circuit for selecting a bus according to the data discrimination control signal 311 and the state of the system bus and for detecting an error by checking the parity of the code and data flowing on the bus, and 402, 403, 404, 40
Reference numeral 5 is a tristate buffer. First, the case of normal operation will be described. In the normal state, the two system buses are used by using 002 exclusively for code and 003 exclusively for data.

In FIG. 3, the bus interface 104
The bus control circuit 401 in the system bus 0 when the processor 101 reads the code of the memory module 001.
System buffer 0, when the buffers 402 and 403 connected to 02 are activated and the processor 101 reads or writes data in the memory module 001.
The buffers 405 and 404 connected to 03 are activated. In either case, the parity check of the code or data entering the processor module 100 is performed. As a result of the check, if there is no error in both data and code, the switching control circuit 301 in the switching circuit determines the snooper 1
Buffer 303 is activated so that 03 monitors data dedicated bus 003. As a result, Snooper 10
3 monitors only the data dedicated bus 003 when normal.

Next, the case where the bus control circuit 401 detects a failure in the code dedicated bus 002 by the parity check will be described. Figure 4 shows a dedicated code bus 002
FIG. 6 is a diagram showing a movement of information on a system bus connected to a bus interface when a failure occurs in the device. 501
Is a time when the code dedicated bus 002 fails, 502 is a code before the code dedicated bus 002 fails, 503 is data before the code dedicated bus 002 fails, 504 is a code after the code dedicated bus 002 fails, 505 , 50
Data 6 is data after the code-dedicated bus 002 fails. The dashed line indicates the bus monitored by the snooper. Figure 3
In the bus control circuit 401,
The detection of the failure of No. 2 is transmitted to the switching control circuit 301 using the error bus discrimination signal 312, and the buffer 40
2 and 403 are made negative, and buffer 40 is used at the time of reading.
5, the buffer 404 is activated at the time of writing.
In FIG. 2, the switching control circuit 301 is a bus control circuit 40.
1 receives the error bus discrimination signal 312 from the buffer 3
02 is made negative, and the code and data flowing on the data dedicated bus 003 are discriminated by looking at the data discrimination control signal 311. Only when the data flows, the buffer 303
To activate. At the same time, the bus control circuit 401 passes both the code and the data to the data dedicated bus 003, and also performs the parity check on the code and the data.

This operation will be described with reference to FIG. 4. Before the failure is detected, the code 502 passes the code dedicated bus 002, the data dedicated bus 003 passes the data 503, and the snooper operates on the system bus 003. The data 503 of FIG. After a failure is detected in the code-dedicated bus 002, the code 504 and the data 505 are also explained as described above.
Both 506 and 506 also pass to the data dedicated bus 003. At that time,
The snooper 103 transmits data 50 on the dedicated data bus 003.
The bus is monitored only when 5 and 506 are flowing.

The case where the bus control circuit 401 detects a failure in the data dedicated bus 003 by the parity check will be described. FIG. 5 is an explanatory diagram when a failure occurs in the data dedicated bus 003. 601 is a data dedicated bus 0
03 is the time of the failure, 602 is a code before the data dedicated bus 003 fails, 603 is data before the data dedicated bus 003 fails, 604 is a code after the data dedicated bus 003 fails, and 605 and 606 are data. This is data after the dedicated bus 003 fails. The broken line indicates the bus monitored by the snooper as in FIG. In FIG. 3, the bus control circuit 401 transmits the fact that the failure of the data dedicated bus 003 is detected to the switching control circuit 301 by using the error bus discrimination signal 312, makes the buffers 404 and 405 negative, and reads the buffer. The buffer 402 is activated during writing. In FIG. 2, the switching control circuit 301 receives the error bus discrimination signal 312 from the bus control circuit 401, makes the buffer 303 negative, and discriminates the code and data flowing on the code dedicated bus 002 by observing the data discrimination control signal 311. , Activates the buffer 302 only when data flows. The bus control circuit 401 passes both the code and the data to the code-dedicated bus 002, and also performs a parity check on the code and the data.

This operation will be described with reference to FIG. 5. Before a failure is detected in the data-dedicated bus 003, the code-dedicated bus 002 has the code 602 and the data-dedicated bus 003.
603 data is passed to the snooper
The data 603 on 03 is monitored. Data dedicated bus 00
After the failure is detected in 3, the code 604 and the data 60
Both 5 and 606 also pass the code dedicated bus 002. The switching circuit switches the snooper monitoring from the data dedicated bus 003 to the code dedicated bus 002. The snooper 103 monitors the bus only when the data 605 and 600 are flowing on the code dedicated bus 002.

As described above, according to this embodiment, one is used as a code dedicated bus and the other is used as a data dedicated bus when operating normally, and when one fails, the code and data pass to the other. A redundant bus is used for each processor module, and each processor module has a switching circuit that switches snooper monitoring from the data dedicated bus to the code dedicated bus when the data dedicated bus fails. And the code dedicated bus fails, the data dedicated bus is monitored,
When the data exclusive bus fails, the code exclusive bus can be monitored, and the hardware amount of the snooper can be reduced.

Example 2. In the first embodiment, the bus control circuit performs a parity check to detect a failure, but the failure detection method may be another method, such as an ECC code check, a reciprocal check, or a CRC.

Example 3. In the first embodiment, an example in which one snooper is used for monitoring operation for two system buses is shown. However, the number of system buses is further increased. For example, four systems are monitored by two snoopers. It is also possible to support more complicated networks such as.

Example 4. In the first embodiment, the duplex bus is used separately for the code dedicated bus and the data dedicated bus. However, even during normal operation, the code and data are passed through each bus and the switching circuit sees the data discrimination control signal. By doing so, it is possible to apply a method in which it is determined that data will pass through the bus and the monitoring destination of the snooper is determined. The bus monitored by the snooper is not limited to data, and may include a code.

[0021]

As described above, according to the fault tolerant computer of the present invention, by providing the switching circuit, the bus monitored by the snooper can be switched, so that the hardware amount of the snooper can be reduced and the monitoring operation can be performed. Can be simplified.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of a duplex bus according to the present invention.

FIG. 2 is a configuration diagram showing a switching circuit according to an embodiment of the present invention.

FIG. 3 is a configuration diagram showing a bus interface according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an operation when a code-dedicated bus fails according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an operation when a data dedicated bus fails according to an embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional fault tolerant computer having a redundant bus.

FIG. 7 is a diagram showing a configuration of a fault tolerant computer having a redundant bus and a snooper.

[Explanation of symbols]

 001 memory module 002 system bus, code dedicated bus 003 system bus, data dedicated bus 100 processor module 1 200 processor module N 101 processor 102 cache memory 103 snooper 104 bus interface 105 switching circuit 111 to 114 internal bus 301 switching control circuit 302 to 303 Tristate buffer 311 Data discrimination control signal 312 Error bus discrimination signal 401 Bus control circuit 402 to 405 Tristate buffer 501 Code dedicated bus failure occurrence time 502 Code dedicated bus Pre-fault code 503 Code dedicated bus Pre-fault data 504 Code dedicated bus Code after failure 505-506 Code dedicated bus Data after failure 601 Data dedicated bus Failure occurrence time 602 Data dedicated bus Disabled before the code 603 the data en pre-fault data 604 data en post-fault code 605-606 data en post-fault data

Claims (1)

[Claims] 1. A fault tolerant computer having the following elements: (a) a storage device for storing information; (b) a plurality of system buses for transferring the information stored in the storage device; (c) the following elements: (C1) an arithmetic unit for processing information stored in the storage device via the system bus, (c2) a number of snoopers less than the number of system buses monitoring the plurality of system buses, ( c3)
A switching circuit between the snooper and the system bus for selecting a bus to be monitored by the snooper, (c4) switching control means for switching the switching circuit according to the situation.