JPH05151777A - Semiconductor integrated circuit with power consumption control circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption. CONSTITUTION:A clock signal 1 and a read/write control signal 2 are supplied to a power consumption control circuit 11 and the clock signal 1 is outputted as a read control signal 5 or a write control signal 6 corresponding to the control signal 2 by the power consumption control circuit 11. A write part 8 is stopped while write is operated and a write part 7 is stopped while read is operated since these two control signals 5, 6 are outputted selectively. Then, power consumption in a synchronous memory is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a power consumption control circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional synchronous memory, as shown in FIG. 3, a clock signal 1 for operating a reading section 7 and a writing section 8 and a reading control for controlling a reading permission gate 9 and a writing permission gate 10. The write signal 2 is supplied, and reading and writing of data from the memory cell 3 designated by the address section 4 by these signals 1 and 2 are controlled.

The operation will be described below. In the conventional synchronous memory, the reading unit 7 and the writing unit 8 operate in synchronization with the clock signal 1. If the read / write control signal 2 specifies read, the read permission gate 9 is opened, and the address unit 4 is accessed via the read unit 7.
The data is read from the memory cell 3 designated by.

On the other hand, if the control signal 2 specifies writing, the write permission gate 10 is opened, and data is written in the memory cell 3 designated by the address section 4 via the writing section 8. Then, a series of these operations proceed in synchronization with the clock signal 1 to realize the operation as the synchronous memory.

[0005]

However, in this conventional synchronous memory 2, the read / write control signal 2 selects read or write, and at the time of write, the write section 8 is synchronized with the clock signal 1. Are operating, but at this time, the unnecessary read operation unit 7 is operating in synchronization with the clock signal 1.

Since a circuit irrelevant to the designated operation is operating in this way, there is a problem that the power consumption is large. Moreover, when the power consumption is large, there is also a problem that the power supply section of the entire system including the memory also becomes large.

[0007]

The gist of the first invention of the present application is as follows.
In a semiconductor integrated circuit including a memory cell, a reading unit that reads data from the memory cell in response to a clock signal when reading, and a writing unit that writes data to the memory cell in response to a clock signal when writing, a read operation That is, a power consumption control circuit for supplying a clock signal to only one of the reading means and the writing means in response to a control signal designating one of the writing operations is provided.

A second aspect of the present invention is a semiconductor integrated circuit including an X-adic counter that advances in response to a clock signal and a Y-adic counter that advances in response to a clock signal. That is, the power consumption control circuit that supplies the clock signal to only either the X-adic counter or the Y-adic counter in response to the selection signal for selecting one of the Y-adic counter.

[0009]

The power consumption control circuit supplies the clock signal to only one of the reading means and the writing means, or to either one of the X-adic counter and the Y-adic counter, and does not supply it to the other.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings through embodiments. FIG. 1 shows a synchronous memory with a power consumption control circuit as a first embodiment of the present invention. This synchronous memory with power consumption control circuit is switched between a read operation and a write operation depending on the state of the read / write control signal 2.

The clock signal 1 and the read / write control signal 2 are input to the power consumption control circuit 11. At the time of reading, the read control signal 5 activates the reading section 7 as shown in FIG. Since the read / write control signal 2 opens the read enable gate 9, the data of the memory cell 3 designated by the address section 4 is output. At this time, the writing unit 8 is deactivated by the writing control signal 6 of the power consumption control circuit 11, and its operation is stopped.

On the other hand, during the write operation, the power consumption control circuit 11 activates the write section 8 using the write control signal 6 as shown in FIG. reading,
The write control signal 2 opens the write enable gate 10,
Data is written in the memory cell 3 designated by the address section 4. At this time, the reading unit 7 uses the power consumption control circuit 1
It is deactivated by the read control signal 5 of 1, and the operation is stopped.

FIG. 2 shows a second embodiment in which the present invention is applied to an X-adic / Y-adic switching circuit. This X-adic / Y-adic counter switching circuit is X-adic depending on the state of the counter select signal 12.
The binary counter 13 or the Y-ary counter 14 can be selected.
When the X-adic counter 13 is operating, the Y-adic counter control signal 15 is in a standby state, and the Y-adic counter 14 does not operate. On the other hand, when the Y-adic counter 14 is operating, the X-adic counter control signal 16 is in a standby state and the X-adic counter 13 does not operate. Therefore, the X-adic and Y-adic counters 13 and 14 are inactivated while maintaining the previous state without being reset, and the X-adic and Y-adic numbers can be freely combined and used.

[0014]

As described above, according to the present invention, since the power consumption control circuit stops the circuits which are unnecessary for operation, the power consumption of the integrated circuit can be greatly reduced, and the power supply circuit of the whole system is small. It has the effect that it can be converted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional synchronous memory.

FIG. 4 is a timing chart of the first embodiment.

[Explanation of symbols]

 1 clock signal 2 read / write signal 3 memory cell 4 address section 5 read enable signal 6 write enable signal 7 read section 8 write section 9 read enable gate 10 write enable gate 11 power consumption control circuit 12 counter select signal 13 X-adic counter 14 Y-adic counter 15 Y-adic counter control signal 16 X-adic counter control signal

Claims (2)

[Claims] 1. A semiconductor integrated circuit comprising: a memory cell; a reading means for reading data from the memory cell in response to a clock signal during reading; and a writing means for writing data in the memory cell in response to a clock signal during writing. 2. A semiconductor integrated circuit according to claim 1, further comprising a power consumption control circuit that supplies a clock signal to only one of the reading unit and the writing unit in response to a control signal designating either the reading operation or the writing operation. 2. A semiconductor integrated circuit comprising an X-adic counter that advances in response to a clock signal, and a Y-adic counter that advances in response to a clock signal, wherein either an X-adic counter or a Y-adic counter is provided. A semiconductor integrated circuit comprising a power consumption control circuit for supplying a clock signal only to either an X-adic counter or a Y-adic counter in response to a selection signal for selecting one of them.