JPH05144943A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide an output cell which operates stably by lowering noises which are carried on a power supply line when a number of output cells of a semiconductor integrated circuit operate simultaneously. CONSTITUTION:In a semiconductor integrated circuit device of master slice method using a three-layer wiring, two kinds of output cells are used, which are an A-type cell whose power supply line consists of a first layer of a wiring layer 8 and a second layer of wiring layers 1, 2 and a B-type cell whose power supply line consists of a first layer of a wiring layer 8, a second layer of a wiring layer 3 and a third layer of wiring layers 4, 5. Thereby, noises carried on a power supply line are separated to wirings of two layers and three layers, thereby lowering noises of a semiconductor integrated circuit device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In a conventional master slice type semiconductor integrated circuit device, an input cell, an output cell and an internal cell are composed of two layers of wiring.

Recently, various three-layer wiring cells have been developed, but only two-layer wiring cells are used as output cells.

[0004]

Currently, the design rule of semiconductor design is as small as 1.0 μm, 0.8 μm, 0.6 μm, etc., and the output cell itself is downsized, or the conventional design rules A large number of input cells and output cells are provided on the semiconductor chip by making the width of the cell narrower than before.

On the other hand, the cell driving frequency has changed from the order of MHz to several hundred MHz. This allows
The number of output cells operating at substantially the same time (actually several tens of nanoseconds) increased. Since the cell driving frequency has increased, the noise on the output terminal and the power supply line has increased compared to the conventional case.

For this reason, if the conventional design method is used as it is, noise increases when a large number of output cells on the same semiconductor chip operate simultaneously at a high frequency. ) Has to be restricted more than before.

Therefore, an object of the present invention is to provide a group of output cells on the same semiconductor chip that reduce noise on the power supply line during operation of the output cells and operate stably.

[0008]

According to the present invention, in a master slice type semiconductor integrated circuit device using a three-layer wiring, a power supply line is a cell A type having a first wiring layer and a second wiring layer. It is composed of two types of output cells, that is, a cell B type composed by utilizing the wiring layers of the first layer, the second layer and the third layer.

[0009]

By using the A and B type cells as the output cells, the noise of the A type cell is placed on the power supply line of the second layer and the noise of the B type cell is placed on the power line of the third layer. Therefore, the noise is lower than the conventional one because the power supply line on which the noise is generated is different.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a schematic view of a mask (after the contacts of the first and second layers) of the semiconductor integrated circuit device of the present invention, and FIG. 2B is a sectional view in the lateral direction thereof. Figure 1
Then, the illustration of the wiring 8 of the first layer is omitted.

In FIG. 1, a cell A has the same structure as the conventional example and is composed of two-layer wiring. The contact 6 connects the wirings 1 (V _SS ) and 2 (V _DD ) of the second layer to the first layer. The cell B is a cell composed of three layers of wiring. In the cell of B, 3 is the wiring of the second layer,
First-layer wiring 8 and third-layer wiring 4 (V _SS ) and 5 (V _DD ).
It is provided to connect with. The first layer and the second layer are connected by a contact 6. The wiring was formed of an aluminum layer.

As is apparent from FIG. 1, the A type is a cell composed of two wiring layers, while the B type is a cell composed of three wiring layers. When the A type cell is operated, noise is mainly on the second wiring layers 1 and 2. On the other hand, when the B type cell operates, noise is mainly transferred to the third wiring layers 4 and 5. When both A and B types are used, A type noise can be separated from the second layer and B type noise can be separated into the third layer. That is, the A type cell and the B type cell are not affected by the noise of the other party.

From the above, by using both A and B type cells, the noise can be separated into the power supply lines of the second layer and the third layer, and the noise of the power supply line can be made lower than before. it can. Therefore, by alternately arranging the cells A and B, or by arranging them arbitrarily,
Noise can be reduced.

Reference numeral 9 denotes the N well 11 and the first-layer wiring 8
, 10 is an insulator, and 12 is a Si substrate.

A specific example will be described below. CM
In the output cell of the OS1.5 μm gate array, the output waveforms of the conventional 15 mA cell having only the two-layer wiring (A type) and the two-layer (A type) and three-layer (B type) mixed wiring 15 mA cells according to the present invention are shown. It shows in comparison with FIG.
Both A and B type cells are arranged alternately.

FIG. 2 (a) is a voltage waveform diagram of an operated output cell, and FIG. 2 (b) is a voltage waveform diagram of a static output cell adjacent thereto. This is obtained by operating only one output cell and observing the noise waveform of the adjacent output cell. In the figure, 15 is the output waveform of the operation output cell, and the noise at the level of 5 V when the adjacent output cells are stationary has the waveform 1 when only the conventional cell is used.
According to the present invention, however, the amplitude is remarkably narrow, as shown by the waveform 13.

As described above, according to the present invention, the level fluctuation of the output waveform voltage can be reduced more than ever before.

[0018]

According to the present invention, when the output cells operate simultaneously, noise on the output line is lower than in the prior art, so that the cells are less likely to malfunction and operate stably when a large number of cells change at the same time. The number of possible cells can be increased. As a result, the degree of freedom in semiconductor design can be increased.

[Brief description of drawings]

FIG. 1A is a schematic view of a mask (after the first and second contact layers) of a semiconductor integrated circuit device of the present invention, and FIG.
Is its cross-section

2A is an output waveform diagram of an operation output cell, and FIG. 2B shows an output waveform of a static output cell adjacent to the operation output cell, comparing the semiconductor integrated circuit device of the present invention with a conventional example. Figure

[Explanation of symbols]

 1 Wiring of 2nd Layer 2 Wiring of 2nd Layer 3 Wiring of 2nd Layer 4 Wiring of 3rd Layer 5 Wiring of 3rd Layer 6 Contact between 1st Layer and 2nd Layer 7 Contact between 2nd Layer and 3rd Layer 8 1 Wiring of the layer 9 Contact between N well and wiring 8 of the first layer 10 Insulator 11 N well 12 Si substrate

Claims (1)

[Claims] 1. A master slice type semiconductor integrated circuit device using three-layer wiring, wherein a power supply line is a first type cell having first and second wiring layers,
A semiconductor integrated circuit device including a second type cell and two types of output cells configured by using the first, second and third wiring layers.