JP3353397B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type or standard cell type semiconductor integrated circuit, and more particularly to an improvement in power supply wiring in an internal cell column region.

[0002]

2. Description of the Related Art Conventionally, power supply wiring of a semiconductor integrated circuit using a master slice method or a standard cell method has a power supply structure as shown in FIGS. FIG.
In the example, a first-layer power supply wiring is provided for each cell column in the cell column direction. FIG. 4 has orthogonal second-layer power supply wires provided for the purpose of reinforcing the first-layer power supply wires in the cell column direction.

The width of the power supply wiring shown in FIG. 3 is to keep the potential drop due to the resistance of the power supply wiring in the center part of the cell row within an allowable range, and to prevent electromigration caused by the current flowing through the power supply wiring for a long time. It is determined in consideration of. Further, the power supply wirings 13 and 14 in the vertical direction in FIG. 4 are provided for the purpose of reinforcing the power supply wiring in the cell column direction, and the width of the power supply wiring in the cell column direction can be made narrower than the configuration in FIG.

[0004]

However, in a semiconductor integrated circuit using a master slice system or a standard cell system, the arrangement of logic cells constituting a mounted logic circuit is automatically performed, and high-speed operation cells and clocks are not provided. There is a possibility that cells with large current consumption, such as buffers, may be arranged in the same cell column, and the power line in the cell column direction has a uniform width in the cell column region in order to cope with the aforementioned potential drop and electromigration. In the power supply configuration of FIG. 3, there is a problem that the height of the cell is increased and the chip size is increased.

Further, in the power supply configuration of FIG. 4, the width of the power supply line in the cell column direction can be set narrower than that of FIG.
It is necessary to increase the number of power supply wires in the vertical direction appropriately, and the number of wiring tracks to be fastened by the power supply wires in the vertical direction increases. There was a problem that the size became large.

[0006]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit comprising a chip in which a plurality of cell columns in which a plurality of logic cells are disposed are arranged in multiple stages. In a direction perpendicular to the chip, a plurality of cell columns are arranged in the peripheral portion of the chip, and a power supply line formed by an N-th layer wiring (N is a natural number) is connected to the power supply line. Are arranged in the cell column direction every
The wiring of the Mth layer different from the layer (M is a natural number different from N)
And the power supply unit of one of the logic cells is adjacent to the cell column direction power supply wiring of the predetermined cell column in which the one logic cell is arranged and the predetermined cell column. And a wiring formed by an N-th layer wiring, which is arranged in a direction perpendicular to the column direction so as to electrically connect only the cell column direction power supply wiring of the cell column to be connected with the shortest distance. Features.

[0007]

[0008]

In the semiconductor integrated circuit configured as described above, a logic cell consuming a large amount of current is selected, and its power supply section includes a cell column direction power supply wiring provided in a cell column including the logic cell. By being electrically connected to two or more power supply lines in the cell column direction by the shortest wiring, the current flowing into or out of the power supply unit is distributed to a plurality of power supply lines in the cell column direction by the shortest wiring. Is done.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram schematically showing a power supply configuration in a cell column region of a semiconductor integrated circuit according to one embodiment of the present invention. As shown in the figure, VDD is applied to each logic cell 4 from the chip peripheral portion 2 via the second-layer metal wiring 5, the through hole 9 and the first-layer metal wiring 7 in the cell column direction. Similarly, a VSS potential is applied to each logic cell 4 from the chip peripheral portion 2 via the second-layer metal wiring 6 and the first-layer metal wiring 8 in the cell column direction. The logic cell 10 is a logic cell selected from the logic cells constituting the circuit in consideration of the magnitude of power consumption, and its power supply unit has a second-layer metal wiring 11 and a second-layer metal wiring 11 orthogonal to the cell column direction. The metal wiring 12 is connected to the VDD wiring 7 and the VSS wiring 8 provided for the upper and lower cell rows sandwiching the cell row at the shortest distance.

FIG. 2 is a diagram schematically showing a physical wiring pattern (inverter circuit) of one cell included in a logic cell library constituting a semiconductor integrated circuit according to one embodiment of the present invention. As shown in FIG.
The SS power supply unit 81 includes a contact hole 15 for establishing conduction between the diffusion region or the polysilicon gate 21 and the first-layer metal wiring, a first-layer metal wiring, a VDD second-layer metal wiring 11, a VSS second-layer metal wiring 12, Through hole 9
It is composed of Although not shown in this figure, the VDD second-layer metal wiring 11 and the VSS second-layer metal wiring 12 are the cells provided in the adjacent cell columns when the semiconductor integrated circuit shown in FIG. Column direction VDD1
It extends to a position where it reaches the metal wiring 7 of the first layer and the metal wiring 8 of the VSS first layer, respectively.

[0012]

According to the present invention, the power supply impedance of a logic cell having a large current consumption selected in consideration of the operation of a logic circuit can be set low, so that a power supply in a cell column direction provided over the entire internal cell column region is provided. When the present invention is applied to a semiconductor integrated circuit having a power supply line orthogonal to the reinforcing cell row shown in FIG. 4, the number of the orthogonal power supply lines can be set small, and as a result, the chip area can be reduced. .

In the embodiment of the present invention, the power supply wiring in the cell column direction is described as the first-layer metal wiring in the semiconductor integrated circuit using the two wiring layers. Even in the case of wiring, the same effect can be obtained by using the shortest distance connection wiring as the first layer metal wiring.

Further, in a semiconductor integrated circuit using three or more wiring layers, a single wiring layer different from the wiring layer used for the power supply wiring in the cell column direction or a plurality of wiring layers different from each other is used for the shortest distance connection wiring. This has a similar effect.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a power supply configuration of a cell column region of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram schematically showing a physical wiring pattern of one cell (inverter circuit) included in a logic cell library constituting the semiconductor integrated circuit of the present invention.

FIG. 3 is a diagram schematically illustrating a power supply configuration of a cell column region of a conventional semiconductor integrated circuit.

FIG. 4 is a diagram schematically illustrating a power supply configuration of a cell column region of a conventional semiconductor integrated circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 2 ... Peripheral part which comprises an input / output etc. 3 ... Cell row 4 ... Logic cell 5 ... VDD 2nd layer metal wiring (cell row orthogonal direction) 6 ... VSS second layer metal wiring (cell column orthogonal direction) 7... VDD first layer metal wiring (cell column direction) 8... VSS first layer metal wiring (cell column direction) 9... 1-2 interlayer through hole 10 ... Logic cell selected from the circuit 11 ... Second-layer metal wiring for electrically connecting the VDD power supply to the VDD power supply wiring in the cell row direction on both sides 12 ... VSS power supply and the cell row on both sides Second-layer metal wiring for electrically connecting to direction VSS power supply wiring 13... Cell row direction VDD Second-layer metal wiring orthogonal to cell row for reinforcing first-layer metal wiring 14... Cell row direction In cell row to reinforce VSS first layer metal wiring Orthogonal VSS second layer metal wiring 15 contact hole 16 P-well region 17 N + diffusion region 18 P + diffusion region 19 P + guard ring 20 N + guard ring 21 ... Polysilicon gate 71 ... Logic cell VDD power supply section 81 ... Logic cell VSS power supply section

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit comprising a chip in which a plurality of cell columns in which a plurality of logic cells are disposed are arranged in multiple stages, wherein the multi-stage cell columns are sandwiched in a direction orthogonal to the column direction of the cell columns. The wiring (N
Is a natural number. ), And an M-th layer wiring (M is a natural number different from N) that is connected to the power wiring and is arranged in the cell column direction for each cell column and is different from the N layer. A cell column direction power supply line, and a cell adjacent to the predetermined cell column in the cell column direction power supply line of a predetermined cell column in which the one logic cell is arranged, in a power supply unit of one logic cell A wiring formed in the direction perpendicular to the column direction and electrically formed by an N-th layer wiring so that only the cell column direction power supply wiring of the column is electrically connected with the shortest distance.