JPH05143469A - Memory backup device - Google Patents

Abstract

PURPOSE:To surely save data of a non-volatile memory, whose power is not backed up, in another non-volatile memory, whose power is backed up, indepen dently of the data volume at the time of a power failure. CONSTITUTION:This device is provided with a main power source 13, a secondary battery 18, a power failure detecting circuit 14, first and second power switching circuits 15 and 16 which supply the power from the secondary battery 18 to a temporary backup block 2 provided with a cache memory 37 and a backup block 3 provided with a D-RAM 43 at the time of detecting a power failure by the power failure detecting circuit 14, and a data transfer control circuit 39 for power failure which saves all data of the cache memory 37 in the D-RAM 43 at the time of detecting a power failure by the power failure detecting circuit 14 and stops to supply power from the secondary battery 18 to the temporary backup block 2 through the first power switching circuit 15 at the time of completely saving all data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory backup device for backing up data by backing up a volatile memory with a secondary battery when the main power supply fails.

[0002]

2. Description of the Related Art Conventionally, a personal computer with a resume function has been known which allows a program to be re-executed when the power is turned on again without erasing the contents stored in the memory even when the main power of the main body is cut off. There is. When the main power supply of such a personal computer is cut off, the power supply of the volatile memory is switched from the main power supply to an auxiliary power supply such as a secondary battery so that the data is saved from the volatile memory that is not backed up in the volatile memory. Has become. For example, as shown in FIG. 3, in JP-A-3-42714, a display data storage status memory storing a CPU 1 constituting a control unit main body, a BIOSROM 2 storing a control program, and a status for realizing a resume function is shown. 3, system memory 4 for storing application programs, VRAM 5 for storing display data,
A display control circuit 7 for controlling the display device 6, a backup memory 8 used for saving display data of the VRAM 5, are provided, and the status memory 3, the system memory 4, and the backup memory 8 are backed up by a backup battery 9. It has become. Then, as shown in FIG. 4, when a power failure occurs, the display data in the VRAM 5 is saved in the backup memory 8.

[0003]

However, in this conventional device, since the display data of the VRAM 5 is saved in the backup memory 8 between the power failure of the main power supply and the power supply being cut off, the amount of data to be saved is reduced. However, if the number of the data increases, there is a problem that all the data cannot be saved in the backup memory 8 after the main power is cut off until the power supply voltage drops below the system operation guarantee voltage.

Therefore, according to the present invention, the data in the volatile memory which is not backed up by the secondary battery regardless of the amount of data is
An object of the present invention is to provide a memory backup device that can be reliably saved in a volatile memory backed up by a secondary battery.

[0005]

According to the present invention, a volatile memory backed up by a secondary battery when the main power supply is cut off, and a volatile memory not backed up by a secondary battery,
A power failure detecting means for detecting a power failure of the main power supply; and a volatile memory and a backup control means not backed up while switching the power supply of the volatile memory backed up by the power failure detection signal from the power failure detecting means to the secondary battery. Switching control means for switching the power source from the main power source to the secondary battery, and saving control of the data in the volatile memory that is not backed up when the power source is switched by this switching control means to the volatile memory that is backed up, When the evacuation is completed, the volatile memory that is not backed up and the evacuation control means for cutting off the power supply from the secondary battery to the evacuation control means are provided.

[0006]

In the present invention having such a configuration, when the main power supply fails, a power failure detection signal is output from the power failure detection means, and the volatile memory to be backed up, the volatile memory not to be backed up, and the power supply to the evacuation control means. The main battery is switched to the secondary battery. In this state, the data in the volatile memory that is not backed up is saved in the volatile memory that is backed up. When the saving of all data is completed, the power supply from the secondary battery to the volatile memory that is not backed up and the saving control means is cut off.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a system power supply block, 2 is a temporary backup block, and 3 is a backup block.

A main power supply 13 and a power failure detection circuit 14 are connected to an AC power supply 11 via a power switch 12. Then, the main power supply 13 supplies power directly to the system power supply block 1, and the temporary backup block 2 supplies power via one PNP transistor 15a of the first power supply switching circuit 15, and One PNP of the second power supply switching circuit 16 is provided in the backup block 3.
Power is supplied through the transistor 16a.

Power is supplied from the main power source 13 to the battery charge / discharge switching circuit 17. The battery charge / discharge switching circuit 17 charges the secondary battery 18 when the main power source 13 is in a steady state, and switches the secondary battery 18 from the charged state to the discharged state when the main power source 13 fails. Is becoming The output from the secondary battery 18 is subjected to constant voltage control by a constant voltage circuit 19, and then the other PNP transistor 15b of the first power supply switching circuit 15 is controlled.
PNP of the second power supply switching circuit 16 while being supplied to the temporary backup block 2 via
It is adapted to be supplied to the backup block 3 via a transistor 16b.

The power failure detection circuit 14 deactivates the power failure detection signal output when the main power supply 13 is in a steady state, and activates the power failure detection signal output when the main power supply 13 is in a power failure state. ing.

The system power supply block 1 includes a CPU
A bus 21 and a system bus 22 are provided, and the buses 21 and 22 are connected via a buffer 23.
Then, the CPU / bus 21 is provided with C which constitutes the control unit main body.
A PU (Central Processing Unit) 24 and an interrupt controller 25 are connected, and program data for the CPU 24 to control each part is stored in the system bus 22.
An OM (Read Only Memory) 26, a CRT controller 28 for controlling the CRT display 27, a keyboard controller 30 for controlling the keyboard 29, a disk controller 32 for controlling the floppy disk device 31, and a disk controller 34 for controlling the hard disk device 33. Each is connected.

A memory bus 35 is provided in the temporary backup block 2, and the memory bus 35 is connected to the CPU bus 21 of the system power supply block 1 via a buffer 36. Then, a cache memory 37 composed of a non-volatile memory that is not backed up to the memory bus 35, a D-RAM controller 38 for generating an address of a D-RAM described later, and all data of the cache memory 37 described later when a power failure is detected.
A data transfer control circuit 39 at the time of power failure for transferring to RAM and a cache controller 40 for performing write control to the cache memory 37 by a copy back method are respectively connected.

The backup block 3 has a memory
A bus 41 is provided, and the memory bus 41 is connected to the memory bus 35 of the temporary backup block 2 via a buffer 42. A D-RAM 43 composed of a non-volatile memory backed up to the memory bus 41 is connected. The D-RAM 4
3 is also connected to the D-RAM controller 38 via a buffer 44.

The backup block 3 is also provided with a battery charging voltage monitoring circuit 45. The charging voltage monitoring circuit 45 monitors the charging voltage to the secondary battery 18, and when the charging voltage is equal to or higher than a specified value, a low level monitoring signal is sent to the bases of the transistors 15a and 16a of the power supply switching circuits 15 and 16. When the charging voltage drops below a specified value, a high level monitoring signal is supplied to the bases of the transistors 15a, 16a of the power supply switching circuits 15, 16.

The interrupt controller 25 adjusts the interrupt request from the various input / output units and the interrupt request,
An interrupt request is output to U24. The data transfer control circuit 39 at the time of power failure is the power failure detection circuit 14
A power failure detection signal from the first power supply switching circuit 15
The low level signal is supplied to the base of the other transistor 15b of the D-RAM.
When the transfer of all data to 43 is completed, the transistor 15
A high level signal is supplied to the base of b. Next, the operation of this embodiment will be described with reference to FIG.

As shown in FIG. 2 (a), the power switch 12
When the power is turned on, the main power supply 13 rises and the supply of the power supply voltage to the system power supply block 1 is started as shown in FIG. 2 (b). Then, the battery charge / discharge switching circuit 17 is switched to the charging side, and the charging of the secondary battery 18 is started as shown in FIG. 2 (c).

In this state, when the charging voltage to the secondary battery 18 exceeds the specified value, the monitoring signal from the charging voltage monitoring circuit 45 switches from the high level to the low level as shown in FIG. 2 (d). As a result, the first and second power supply switching circuits 15,
16 transistors 15a and 16a are turned on, and
As shown in (f), the system power supply period to the temporary backup block 2 is started. Although the system power supply period to the backup block 3 is also started as shown in FIG. 2 (g), the secondary battery 18 is supplied to the backup block 3 via the transistor 16b of the second power switching circuit 16. The power supply from is continuing.

Then, the power failure detection signal from the power failure detection circuit 14 has a predetermined delay time after the charging of the secondary battery 18 is started, as shown in (e) of FIG. To inactive state. As a result, the transistor 16b of the second power supply switching circuit 16 is turned off, and the power supply from the secondary battery 18 to the backup block 3 is stopped.

Thus, as shown in (h), (i) and (j) of FIG. 2, the operating state of the CPU 24 and the peripheral I / O, the operating state of the temporary backup memory (cache memory 37),
The operation state of the backup memory (D-RAM 43) is all normal.

Next, when the power switch 12 is turned off in the normal operation state or when the AC power source 11 goes down and a power failure occurs, for example, the power switch 12 is turned off as shown in FIG. 2 (a). Then, the system power block 1
Then, as shown in (h) of FIG. 2, the power outage process is performed and the memory access is stopped.

In addition, the power failure detection circuit 14 detects a power failure and FIG.
As shown in (e), the power failure detection signal from the power failure detection circuit 14 switches from the high level to the low level, that is, the active state. The battery charge / discharge switching circuit 17 switches the secondary battery 18 from the charged state to the discharged state. As a result, the transistor 16b of the second power supply switching circuit 16 is turned on, and the power supply from the secondary battery 18 to the backup block 3 is started. Also, data transfer control circuit 3 at power failure
9, the transistor 15b of the first power supply switching circuit 15
Is turned on, and the power supply from the secondary battery 18 to the temporary backup block 2 is started. Further, the interrupt controller 25 outputs a power failure interrupt request to the CPU 24, whereby the power failure process is started and the memory access is stopped as shown in (h) of FIG.

In this state, when the charging voltage to the secondary battery 18 drops below a specified value, the monitoring signal from the charging voltage monitoring circuit 45 switches from low level to high level as shown in FIG. 2 (d). .. As a result, the transistors 15a and 16a of the first and second power supply switching circuits 15 and 16 are turned off.

The data transfer control circuit 39 at the time of power failure is CP
After confirming that U24 has canceled the memory access,
As shown in FIG. 2 (i), the data in the cache memory 37 is transferred to the D-RAM 43 as shown in FIG. 2 (j). That is, the data is saved.

After that, when the data transfer control circuit 39 at the time of power failure confirms that the data saving in the cache memory 37 is completed, the transistor 15b of the first power supply switching circuit 15 is
Turn off. Thus, the power supply from the secondary battery 18 to the temporary backup block 2 is stopped, and the power supply to the temporary backup block 2 is completely stopped.
Thus, the operation of the temporary backup block 2 is as shown in FIG.
As shown in (i), it is stopped.

On the other hand, the power supply from the secondary battery 18 to the backup block 3 is maintained by the ON state of the transistor 16b of the second power switching circuit 16. Thus, the D-RAM 43 of the backup block 3 is (j) in FIG.
The backup state is entered as shown in.

When the main power supply 13 goes into a power failure state in this way, first, the secondary battery 18 backs up both the temporary backup block 2 and the backup block 3, and in this state, all the data in the cache memory 37 is D-.
Since the backup by the secondary battery 18 to the temporary backup block 2 is stopped when the data is saved in the RAM 43 and the backup is completed, only the backup of the backup block 3 is performed thereafter. Surely D
-It can be saved in the RAM 43. After the evacuation is completed, only the original backup of the D-RAM 43 is performed, so that the power consumption of the secondary battery 18 is hardly affected.

[0027]

As described in detail above, according to the present invention, data in a volatile memory that is not backed up by a secondary battery is reliably saved in a volatile memory that is backed up by a secondary battery regardless of the amount of data. It is possible to provide a memory backup device capable of performing the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of each unit in the embodiment.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a flowchart showing an operation in the conventional example.

[Explanation of symbols]

1 ... System power supply block, 2 ... Temporary backup block, 3 ... Backup block, 13 ... Main power supply, 1
4 ... Blackout detection circuit, 15, 16 ... Power supply switching circuit, 18 ...
Secondary battery, 24 ... CPU, 37 ... Cache memory (volatile memory that is not backed up), 39 ... Data transfer control circuit at power failure, 43 ... D-RAM (volatile memory that is backed up).

Claims (1)

[Claims] 1. A volatile memory backed up by a secondary battery when the main power is cut off, a volatile memory not backed up by a secondary battery, a power failure detection means for detecting a power failure of the main power, and this power failure. Switching control means for switching the power supply of the volatile memory to be backed up from the main power supply to the secondary battery by the power failure detection signal from the detection means and for switching the power supply of the volatile memory and the evacuation control means not backed up from the main power supply to the secondary battery And when the power source is switched by the switching control means, the data in the volatile memory that is not backed up is controlled to be saved in the volatile memory that is backed up, and when the saving of all data is completed, the volatile memory that is not backed up and Evacuation control means for shutting off power supply from the secondary battery to the evacuation control means is provided. And a memory backup device.