JPH0513506A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the reliability and manufacturing yield of a chip carrier in which a semiconductor chip mounted on a package substrate is hermetically sealed with a cap. [Structure] The semiconductor chip 3 is provided with CCB bumps 6 and TAs.
Face down bonding is performed on the package substrate 2 via the lead 9 of B, and the cap 4 is soldered on the package substrate 2 to hermetically seal the semiconductor chip 3,
Further, it is a chip carrier in which the back surface of the semiconductor chip 3 is soldered to the lower surface of the cap 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to the high reliability of a chip carrier.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication Nos. 62-2449429 and 6
JP-A-3-310139 describes a chip carrier in which a semiconductor chip mounted on a package substrate is hermetically sealed with a cap.

The chip carriers described in the above documents are
It has a package structure in which a semiconductor chip is face-down bonded via a CCB bump on a package substrate made of a highly heat-conductive ceramic such as mullite, and the semiconductor chip is hermetically sealed with a cap. The cap is made of high thermal conductive ceramic such as aluminum nitride (AlN), and is joined on the package substrate by solder made of Pb / Sn alloy.

The back surface of the semiconductor chip sealed inside the cavity surrounded by the package substrate and the cap is soldered to the lower surface of the cap. This is because the heat generated from the semiconductor chip is transferred to the cap through the solder.

In the inner layer of the package substrate, for example, W
Internal wiring made of (tungsten) is formed,
Through this internal wiring, the upper surface side electrode and the lower surface side electrode of the package substrate are electrically connected. CCB bumps for mounting the chip carrier on the substrate are joined to the electrodes on the lower surface side of the package substrate.

[0006]

However, in the above-mentioned chip carrier, since the back surface of the semiconductor chip mounted on the package substrate via the CCB bumps is soldered to the lower surface of the cap, semiconductor chips made of different materials,
Due to the difference in coefficient of thermal expansion between the package substrate and the cap, stress and strain are easily applied to the CCB bumps, resulting in C
There is a problem that the life of the CB bump is shortened and the CCB bump may be broken in the worst case.

As a countermeasure, the thickness of the solder at the joint between the cap and the package substrate is increased to about several hundred μm,
It has been proposed that the thick solder absorbs and relaxes the thermal stress and strain applied to the CCB bump.

However, when a solder made of a Pb / Sn alloy is melted and then cooled, dendrites grow inside the solder, and shrink holes are formed along the growth direction of the dendrite. There is a characteristic that is done. Therefore, if the thickness of the solder at the joint between the cap and the package substrate is increased to about several hundreds of μm, through the contraction holes formed along the dendrites grown in the direction horizontal to the main surface of the package substrate. There arises a problem that external moisture enters the inside of the cavity.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of improving the reliability and manufacturing yield of the chip carrier having the above-mentioned package structure. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The typical ones of the inventions disclosed in the present application will be outlined below.

According to the chip carrier of the present invention, the semiconductor chip is face-down bonded onto the package substrate through the CCB bumps and the TAB, and the cap is soldered on the package substrate to hermetically seal the semiconductor chip. It has a package structure in which the back surface of the chip is soldered to the bottom surface of the cap.

[0013]

According to the above means, the CCB bump and the T
By face down bonding the semiconductor chip onto the package substrate via AB, some of the thermal stress and strain applied to the CCB bumps are absorbed and alleviated by the deformation of the TAB leads. The property is improved.

Further, since the thickness of the solder at the joint between the cap and the package substrate can be reduced to about 10 μm, the hermetic sealing of the semiconductor chip is improved.

[0015]

1 is a sectional view of a chip carrier according to an embodiment of the present invention. The chip carrier 1 has a package structure in which a semiconductor chip 3 is face-down bonded onto a package substrate 2 made of high thermal conductive ceramic such as mullite, and the semiconductor chip 3 is hermetically sealed with a cap 4.

The cap 4 is made of high thermal conductive ceramic such as aluminum nitride, and is bonded onto the package substrate 2 via the solder 5. The thickness of the solder 5 at the joint between the cap 4 and the package substrate 2 is, for example, about 10 μm. The solder 5 is, for example, 10
It is made of a Pb / Sn alloy containing about wt% Sn (melting temperature = about 275 to 300 ° C).

The semiconductor chip 3 is mounted on the package substrate 2 by both flip chip and TAB methods. That is, a large number of CCB bumps 6 are joined to the central portion of the element formation surface of the semiconductor chip 3, and a large number of TAB bumps 7 are joined to the peripheral portion.
One end (inner lead portion) of a lead 9 formed on one surface of the insulating film 8 is bonded to the AB bump 7.

The CCB bump 6 is a Pb / Sn alloy containing, for example, about 1 to 4% by weight of Sn (melting temperature = 3.
20 to 327 ° C.) and is electrically connected to the electrode 10 on the package substrate 2. In addition, the TAB
The bumps 7 are made of a composite metal film in which thin films of Cr, Cu, and Au are laminated in order from the lower layer, and are electrically connected to the electrodes 10 on the package substrate 2 via the other ends (outer lead portions) of the leads 9. Has been done.

The electrode 10 on the package substrate 2 is made of a refractory metal such as W (tungsten), and the electrode 1 on the lower surface of the package substrate 2 is connected through internal wiring (not shown).
1 is electrically connected. The electrode 11 has a CC that serves as an external terminal when the chip carrier 1 is mounted on a substrate.
B bumps (not shown) are joined.

A semiconductor chip 3 sealed in a cavity surrounded by the package substrate 2 and the cap 4.
The back surface of the cap is joined to the lower surface of the cap 4 by the solder 5. This is because the heat generated from the semiconductor chip 3 is transferred to the cap 4 through the solder 5.

Further, in order to improve the wettability of the solder 5, a metallized layer 12 is provided on the inner surface of the cap 4 and the peripheral portion of the package substrate 2. The metallized layer 12 is composed of a composite metal film in which thin films of Ti, Ni and Au are sequentially deposited by a vapor deposition method.

Next, an example of a method of assembling the chip carrier 1 will be described with reference to FIGS.

First, as shown in FIG. 2, the semiconductor chip 3
A part of the passivation film 13 on the surface of the is opened by etching, and the uppermost Al wiring (signal and power supply A
Part of (1 wiring) is exposed to form the TAB pad 14a and the CCB pad 14b.

Next, as shown in FIG. 3, a barrier metal layer 15 is formed on the TAB pad 14a and the CCB pad 14b. The barrier metal layer 15 is composed of a composite metal film in which thin films of Cr, Cu and Au are stacked in order from the bottom. The barrier metal layer 15 is formed by a vapor deposition method using a photoresist as a mask, for example.

At this time, A is placed on the CCB pad 14b.
By thickly depositing a thin film of u, the TAB bumps 7
To form. That is, the TAB bumps 7 are formed simultaneously with the barrier metal layer 15 in the same process.

Next, as shown in FIG. 4, the CCB bump 6 is formed on the barrier metal layer 15 of the TAB pad 14a. The CCB bumps 6 are, for example, barrier metal layers 15
A solder film is selectively vapor-deposited on the above by a lift-off method, and then the solder film is formed by wet-back in a reflow furnace.

Next, as shown in FIG. 5, the inner lead portions of the leads 9 are bonded onto the TAB bumps 7. Bonding of the leads 9 is performed using an inner lead bonder used for manufacturing TAB.

Next, as shown in FIG. 6, CCB bump 6
And the ends of the leads 9 (outer lead portions) are respectively positioned on the electrodes 10 on the package substrate 2. First, the CCB bumps 6 are heated and melted to be bonded to the electrodes 10, and then used for manufacturing the TAB. The outer lead portion of the lead 9 is joined to the electrode 10 using an outer lead bonder.

Next, as shown in FIG. 7, the solder 5 is placed on the center of the inner surface of the cap 4, and the solder 5 is heated and melted with the semiconductor chip 3 placed thereon. As a result, the back surface of the semiconductor chip 3 is bonded to the cap 4, and a part of the melted solder 5 travels along the surface of the metallization layer 12 provided on the inner surface of the cap 4 to form a gap between the cap 4 and the package substrate 2. It flows in and the semiconductor chip 3 is sealed.

According to the chip carrier 1 of this embodiment having the above structure, the following actions and effects can be obtained.

(1) Since the semiconductor chip 3 is face-down bonded onto the package substrate 2 via the CCB bump 6 and the TAB lead 9, part of the thermal stress and strain applied to the CCB bump 6 is deformed by the lead 9. Absorbed by,
It is alleviated, and the life of the CCB bump 6 and the connection reliability are improved.

(2) Particularly, in this embodiment, the CCB bump 6 is arranged in the central portion of the semiconductor chip 3 having a relatively small thermal stress, and the TAB bump 7 is provided in the peripheral portion where the thermal stress becomes relatively large. Is arranged, the life of the CCB bump 6 and the connection reliability can be further improved.

(3) By the above (1) and (2), the thickness of the solder 5 at the joint between the cap 4 and the package substrate 2 is set to 1
The thickness can be reduced to about 0 μm. As a result, it is possible to prevent external moisture from entering the inside of the cavity through the contraction holes generated when the solder 5 is cooled, so that the hermetic sealing of the semiconductor chip 3 is improved.

(4) By the above (1) to (3), the reliability and manufacturing yield of the chip carrier 1 can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-mentioned embodiment, the CCB bump is arranged in the central portion of the semiconductor chip and the TAB bump is arranged in the peripheral portion, but the present invention is not limited to this.

Further, the number of semiconductor chips to be sealed in the cavity is not limited to one, but may be plural.

[0038]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the life and connection reliability of the CCB bumps are improved and the hermetic sealing of the semiconductor chip is improved, so that the reliability of the chip carrier and the manufacturing yield can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a chip carrier according to an embodiment of the present invention.

FIG. 2 is a sectional view showing an assembling method of this chip carrier.

FIG. 3 is a cross-sectional view showing the method of assembling this chip carrier.

FIG. 4 is a cross-sectional view showing a method of assembling this chip carrier.

FIG. 5 is a cross-sectional view showing the method of assembling this chip carrier.

FIG. 6 is a sectional view showing an assembling method of this chip carrier.

FIG. 7 is a cross-sectional view showing the method of assembling this chip carrier.

[Explanation of symbols]

1 chip carrier 2 Package substrate 3 semiconductor chips 4 cap 5 solder 6 CCB bump 7 TAB bumps 8 insulating film 9 leads 10 electrodes 11 electrodes 12 Metallized layer 13 Passivation film 14a TAB pad 14b CCB pad 15 barrier metal layer

Claims (4)

[Claims] 1. A chip carrier formed by soldering a cap on a package substrate having a semiconductor chip face down bonded to hermetically seal the semiconductor chip, and soldering a back surface of the semiconductor chip to a lower surface of the cap. A semiconductor integrated circuit device comprising: a semiconductor chip, the semiconductor chip being face-down bonded onto the package substrate via CCB bumps and TAB bumps. 2. A C is formed in the central portion of the element forming surface of the semiconductor chip.
2. The semiconductor integrated circuit device according to claim 1, wherein CB bumps are arranged and TAB bumps are arranged in the peripheral portion. 3. A barrier metal layer and T under the CCB bump.
2. The semiconductor integrated circuit device according to claim 1, wherein the AB bump is made of the same metal film formed in the same process. 4. The semiconductor integrated circuit device according to claim 1, wherein the thickness of the sealing solder provided at the joint between the package substrate and the cap is about 10 μm.