JPH11330158A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH11330158A JPH11330158A JP13013798A JP13013798A JPH11330158A JP H11330158 A JPH11330158 A JP H11330158A JP 13013798 A JP13013798 A JP 13013798A JP 13013798 A JP13013798 A JP 13013798A JP H11330158 A JPH11330158 A JP H11330158A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- wiring board
- package
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【課題】 バンプ電極と基板の電極とが接触する部分の
接続信頼性が向上したパッケージを提供する。
【解決手段】 ボンディングパッドBP上に半田バンプ
3を形成した半導体チップ2をパッケージ基板1の主面
にフェイスダウン接続し、半導体チップ2とパッケージ
基板1との隙間にアンダフィル樹脂5を充填して応力の
緩和を図ると共に、半導体チップ2、パッケージ基板1
および半田バンプ3のそれぞれの表面を、アンダフィル
樹脂5よりも密着性がよい絶縁層6で被覆することによ
り、半導体チップ2に形成された素子や、半田バンプ2
と上部電極4との接続部を水分や汚染物から確実に保護
するようにしたパッケージである。
(57) [Problem] To provide a package with improved connection reliability at a portion where a bump electrode and an electrode of a substrate are in contact. SOLUTION: A semiconductor chip 2 having solder bumps 3 formed on bonding pads BP is face-down connected to a main surface of a package substrate 1, and a gap between the semiconductor chip 2 and the package substrate 1 is filled with an underfill resin 5. In addition to reducing stress, the semiconductor chip 2 and the package substrate 1
By coating the respective surfaces of the solder bumps 3 with an insulating layer 6 having better adhesion than the underfill resin 5, the elements formed on the semiconductor chip 2 and the solder bumps 2 are covered.
This is a package that reliably protects the connection between the electrode and the upper electrode 4 from moisture and contaminants.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造技術に関し、特に、バンプ電極を介して半導体
チップを配線基板にフリップチップ実装し、前記半導体
チップと前記配線基板との隙間にアンダフィル樹脂を充
填するパッケージに適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a semiconductor device mounted on a wiring board via a bump electrode by flip-chip mounting, and an underfill in a gap between the semiconductor chip and the wiring board. The present invention relates to a technology effective when applied to a package to be filled with a resin.
【0002】[0002]
【従来の技術】従来、半導体チップをパッケージ基板な
どの配線基板に実装する方法として、ボンディングパッ
ド上にバンプ電極を形成したチップを配線基板にフェイ
スダウン接続し、上記バンプ電極と配線基板の電極とを
電気的に接続するフリップチップ実装方式が広く用いら
れている。バンプ電極には、例えば半田バンプ(特開昭
62−249429号公報、特開昭63−310139
号公報)や、Auボール(特開平6−333982号公
報)などが使用されている。2. Description of the Related Art Conventionally, as a method of mounting a semiconductor chip on a wiring board such as a package board, a chip having bump electrodes formed on bonding pads is face-down connected to the wiring board, and the bump electrodes and the electrodes of the wiring board are connected to each other. Is widely used. The bump electrodes include, for example, solder bumps (JP-A-62-249429, JP-A-63-310139).
No. 3, pp. 157-64, and Au balls (Japanese Patent Laid-Open No. 6-333982).
【0003】ところで、チップが搭載されるパッケージ
基板を安価な合成樹脂で構成することによって製造コス
トの低減を図った樹脂パッケージにおいては、パッケー
ジ基板の熱膨張係数をチップに合わせて設計するセラミ
ックパッケージとは異なり、チップ−基板間の熱膨張係
数差に起因してバンプ電極に加わる応力が大きいため
に、チップとパッケージ基板との接続信頼性が問題とな
る。[0003] Meanwhile, in a resin package in which the package substrate on which the chip is mounted is made of inexpensive synthetic resin to reduce the manufacturing cost, a ceramic package in which the thermal expansion coefficient of the package substrate is designed according to the chip is used. However, since the stress applied to the bump electrode due to the difference in the coefficient of thermal expansion between the chip and the substrate is large, the connection reliability between the chip and the package substrate becomes a problem.
【0004】その対策の一つとして、チップとパッケー
ジ基板との隙間にアンダフィル樹脂を充填することによ
って、上記した応力を緩和することが行われている(例
えば、1990年4月、電子情報通信学会論文誌 C11
Vol.J73-C-II No.9 p516-524)。アンダフィル樹脂とし
ては、上記応力を緩和、吸収できるように熱膨張係数や
ヤング率を最適化したエポキシ樹脂などが使用される。
また、このアンダフィル樹脂は、チップの主面に形成さ
れた素子や、バンプ電極と基板の電極との接続部を水分
や汚染物から保護する保護膜としての機能も備えてい
る。As one of the countermeasures, the above-mentioned stress is relaxed by filling an underfill resin in a gap between the chip and the package substrate (for example, in April 1990, Electronic Information Communication). Academic Journal C11
Vol.J73-C-II No.9 p516-524). As the underfill resin, an epoxy resin or the like whose thermal expansion coefficient and Young's modulus are optimized so that the above-mentioned stress can be relaxed and absorbed is used.
The underfill resin also has a function as a protective film that protects elements formed on the main surface of the chip and the connection between the bump electrode and the electrode of the substrate from moisture and contaminants.
【0005】[0005]
【発明が解決しようとする課題】ところが、チップとパ
ッケージ基板との隙間にアンダフィル樹脂を充填した樹
脂パッケージの場合、チップの主面に形成された表面保
護膜(パッシベーション膜)やバンプ電極に対するアン
ダフィル樹脂の密着性が必ずしも十分に考慮されていな
いために、チップの主面に形成された素子や、バンプ電
極と基板の電極との接続部が水分や汚染物から十分に保
護され難い場合が生じる。However, in the case of a resin package in which an underfill resin is filled in a gap between a chip and a package substrate, an underfill for a surface protection film (passivation film) and a bump electrode formed on the main surface of the chip is provided. Because the adhesion of the fill resin is not always sufficiently considered, it may be difficult to protect the elements formed on the main surface of the chip and the connection between the bump electrode and the substrate electrode from moisture and contaminants. Occurs.
【0006】そこで、チップの主面を表面保護膜と密着
性のよいポリイミド樹脂で被覆することも行われている
が、この場合は、ボンディングパッドを形成する際にポ
リイミド樹脂をエッチングしてその下層の表面保護膜を
露出させた後、さらにこの表面保護膜をエッチングして
最上層配線を露出させなければならないので、ウエハプ
ロセスが煩雑になってしまう。Therefore, it has been practiced to coat the main surface of the chip with a polyimide resin having good adhesion to the surface protective film. In this case, when forming the bonding pad, the polyimide resin is etched to form a lower layer. After exposing the surface protective film, the surface protective film must be further etched to expose the uppermost layer wiring, which complicates the wafer process.
【0007】本発明の一つの目的は、基板とその主面に
実装されたチップとの隙間にアンダフィル樹脂を充填す
る半導体装置において、チップの主面やバンプ電極に対
するアンダフィル樹脂の密着性を向上させる技術を提供
することにある。An object of the present invention is to provide a semiconductor device in which a gap between a substrate and a chip mounted on the main surface thereof is filled with an underfill resin, the adhesion of the underfill resin to the main surface of the chip and the bump electrodes. It is to provide a technology for improving.
【0008】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【0009】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【0010】本発明の半導体装置は、ボンディングパッ
ド上にバンプ電極を形成した半導体チップを配線基板の
主面にフェイスダウン接続し、前記半導体チップと前記
配線基板との隙間にアンダフィル樹脂を充填した半導体
装置において、前記半導体チップ、前記配線基板および
前記バンプ電極のそれぞれの表面を、前記アンダフィル
樹脂よりも密着性がよい絶縁層で被覆したものである。In a semiconductor device according to the present invention, a semiconductor chip having bump electrodes formed on bonding pads is face-down connected to a main surface of a wiring board, and a gap between the semiconductor chip and the wiring board is filled with an underfill resin. In the semiconductor device, a surface of each of the semiconductor chip, the wiring board, and the bump electrode is covered with an insulating layer having better adhesion than the underfill resin.
【0011】本発明の半導体装置は、前記絶縁層をポリ
イミド樹脂を主体として構成することができるものであ
る。In the semiconductor device according to the present invention, the insulating layer can be mainly composed of a polyimide resin.
【0012】本発明の半導体装置は、前記配線基板を合
成樹脂を主体として構成することができるものである。In the semiconductor device according to the present invention, the wiring substrate can be constituted mainly of a synthetic resin.
【0013】本発明の半導体装置は、前記バンプ電極を
半田またはAuで構成することができるものである。In the semiconductor device according to the present invention, the bump electrodes can be made of solder or Au.
【0014】本発明の半導体装置は、ボンディングパッ
ド上にバンプ電極を形成した半導体チップを、セラミッ
クを主体として構成された配線基板の主面にフェイスダ
ウン接続した半導体装置において、前記半導体チップ、
前記配線基板および前記バンプ電極のそれぞれの表面
を、前記絶縁層で被覆したものとすることができる。A semiconductor device according to the present invention is a semiconductor device in which a semiconductor chip having bump electrodes formed on bonding pads is face-down connected to a main surface of a wiring board mainly composed of ceramic.
The surface of each of the wiring board and the bump electrode may be covered with the insulating layer.
【0015】本発明の半導体装置の製造方法は、以下の
工程(a)〜(d)を含んでいる。The method of manufacturing a semiconductor device according to the present invention includes the following steps (a) to (d).
【0016】(a)ボンディングパッド上にバンプ電極
を形成した半導体チップを配線基板の主面にフェイスダ
ウン接続する工程、(b)前記半導体チップと前記配線
基板との隙間に、前記半導体チップの主面、前記配線基
板の主面および前記バンプ電極との密着性がアンダフィ
ル樹脂よりもよい絶縁材料を充填する工程、(c)前記
半導体チップと前記配線基板との隙間に充填した前記絶
縁材料の一部を除去し、前記半導体チップ、前記配線基
板および前記バンプ電極のそれぞれの表面に前記絶縁材
料で構成された絶縁層を形成する工程、(d)前記半導
体チップと前記配線基板との隙間にアンダフィル樹脂を
充填する工程。(A) a step of connecting a semiconductor chip having bump electrodes formed on bonding pads face-down to a main surface of a wiring board; and (b) a step of connecting the semiconductor chip to the gap between the semiconductor chip and the wiring board. Filling an insulating material having better adhesion to the surface, the main surface of the wiring board and the bump electrode than an underfill resin, and (c) filling the gap between the semiconductor chip and the wiring board with the insulating material. Removing a part thereof and forming an insulating layer made of the insulating material on each surface of the semiconductor chip, the wiring substrate, and the bump electrode; (d) forming a gap between the semiconductor chip and the wiring substrate; A step of filling the underfill resin.
【0017】[0017]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【0018】(実施の形態1)図1は、本実施の形態の
半導体装置を示す断面図である。この半導体装置は、ガ
ラスエポキシ樹脂、BTレジンなどで構成されたパッケ
ージ基板1の主面上に半導体チップ2をフェイスダウン
接続した樹脂パッケージである。半導体チップ2は、そ
の主面のボンディングパッドBPに接続された半田バン
プ(バンプ電極)3をパッケージ基板1の上部電極4に
接続するフリップチップ実装方式によってパッケージ基
板1に実装されている。(First Embodiment) FIG. 1 is a sectional view showing a semiconductor device of the present embodiment. This semiconductor device is a resin package in which a semiconductor chip 2 is connected face down on a main surface of a package substrate 1 made of glass epoxy resin, BT resin or the like. The semiconductor chip 2 is mounted on the package substrate 1 by a flip-chip mounting method in which a solder bump (bump electrode) 3 connected to the bonding pad BP on the main surface is connected to the upper electrode 4 of the package substrate 1.
【0019】上記半導体チップ2とパッケージ基板1と
の隙間には、アンダフィル樹脂5が充填されている。こ
のアンダフィル樹脂5は、半導体チップ2とパッケージ
基板1との熱膨張係数差に起因して半田バンプ3に加わ
る応力を緩和するために設けられており、この応力を十
分に緩和、吸収できるように熱膨張係数やヤング率を最
適化したエポキシ樹脂などによって構成されている。The gap between the semiconductor chip 2 and the package substrate 1 is filled with an underfill resin 5. The underfill resin 5 is provided to alleviate the stress applied to the solder bumps 3 due to the difference in thermal expansion coefficient between the semiconductor chip 2 and the package substrate 1. The underfill resin 5 can sufficiently reduce and absorb this stress. It is made of an epoxy resin with optimized thermal expansion coefficient and Young's modulus.
【0020】また、上記アンダフィル樹脂5は、半導体
チップ2の主面に形成された素子や、半田バンプ3と上
部電極4との接続部を水分や汚染物から保護する保護膜
としての機能も兼ねている。しかし、このアンダフィル
樹脂5は、半田バンプ3に加わる応力を緩和するように
設計されているために、半導体チップ2の主面に形成さ
れた表面保護膜や金属(半田バンプ3、上部電極4)と
の密着性は必ずしもよくない。The underfill resin 5 also functions as a protective film for protecting the elements formed on the main surface of the semiconductor chip 2 and the connection between the solder bumps 3 and the upper electrode 4 from moisture and contaminants. Also serves as. However, since the underfill resin 5 is designed to relieve the stress applied to the solder bumps 3, the surface protection film formed on the main surface of the semiconductor chip 2 and the metal (the solder bumps 3, the upper electrode 4) ) Is not always good.
【0021】そこで、本実施の形態では、半導体チップ
2、パッケージ基板1および半田バンプ3のそれぞれの
表面を、上記アンダフィル樹脂5に比べて表面保護膜や
金属との密着性に優れた絶縁層6で被覆することによっ
て、水分や汚染物から保護している。この絶縁層6は、
例えば接着性を向上させたポリイミド樹脂やエポキシ樹
脂などで構成されている。Therefore, in the present embodiment, the surface of each of the semiconductor chip 2, the package substrate 1 and the solder bumps 3 is made to have a surface protective film and an insulating layer which is superior in adhesion to metal as compared with the underfill resin 5. By coating with 6, it is protected from moisture and contaminants. This insulating layer 6
For example, it is made of a polyimide resin or an epoxy resin having improved adhesiveness.
【0022】上記パッケージ基板1の下面には、図示し
ない配線とスルーホールとを通じて上部電極4と電気的
に接続された下部電極7が形成されている。また、これ
らの下部電極7には、樹脂パッケージの外部接続端子を
構成する半田バンプ8が接続されている。上部電極4お
よび下部電極7は、パッケージ基板1の両面に貼り合わ
せた圧延Cu箔(または電解Cu箔)をエッチングして
形成したもので、それらの表面にはNiとAuのメッキ
が施されている。On the lower surface of the package substrate 1, there is formed a lower electrode 7 which is electrically connected to the upper electrode 4 through a wiring (not shown) and a through hole. In addition, to these lower electrodes 7, solder bumps 8 constituting external connection terminals of the resin package are connected. The upper electrode 4 and the lower electrode 7 are formed by etching a rolled Cu foil (or an electrolytic Cu foil) bonded to both surfaces of the package substrate 1, and their surfaces are plated with Ni and Au. I have.
【0023】次に、上記樹脂パッケージの製造方法の一
例を説明すると、まず図2に示すように、ボンディング
パッドBP上に半田バンプ3を形成した半導体チップ2
をチップマウンタ(図示せず)を使ってパッケージ基板
1上に搭載した後、半田バンプ3をリフローさせて上部
電極4に接続する。Next, an example of a method of manufacturing the resin package will be described. First, as shown in FIG. 2, a semiconductor chip 2 having solder bumps 3 formed on bonding pads BP is formed.
Is mounted on the package substrate 1 using a chip mounter (not shown), and the solder bumps 3 are reflowed and connected to the upper electrode 4.
【0024】次に、図3に示すように、半導体チップ2
とパッケージ基板1との隙間に、接着性を向上させたポ
リイミド樹脂やエポキシ樹脂などの絶縁材料6aを充填
した後、図4に示すように、この絶縁材料6aの一部を
半導体チップ2とパッケージ基板1との隙間から除去
し、半導体チップ2、パッケージ基板1および半田バン
プ3のそれぞれの表面に絶縁材料6aで構成された絶縁
層6を形成する。絶縁材料6aの一部を半導体チップ2
とパッケージ基板1との隙間から除去するには、例えば
この隙間にエアーを吹き付けて行う。Next, as shown in FIG.
After filling a gap between the semiconductor substrate 2 and the package substrate 1 with an insulating material 6a such as polyimide resin or epoxy resin having improved adhesiveness, a part of the insulating material 6a is packaged with the semiconductor chip 2 and the package as shown in FIG. The insulating layer 6 made of an insulating material 6a is formed on the surface of each of the semiconductor chip 2, the package substrate 1 and the solder bumps 3 by removing from the gap with the substrate 1. A part of the insulating material 6a is replaced with the semiconductor chip 2.
For example, air is blown into this gap to remove the gap from the gap between the package substrate 1 and the package board 1.
【0025】その後、半導体チップ2とパッケージ基板
1との隙間にアンダフィル樹脂5を充填し、このアンダ
フィル樹脂5と絶縁層6を構成する樹脂とを加熱硬化さ
せた後、パッケージ基板1の下面の下部電極7に半田バ
ンプ8を接続することにより、前記図1に示す樹脂パッ
ケージが完成する。Thereafter, a gap between the semiconductor chip 2 and the package substrate 1 is filled with an underfill resin 5, and the underfill resin 5 and a resin constituting the insulating layer 6 are heated and cured. By connecting the solder bumps 8 to the lower electrodes 7, the resin package shown in FIG. 1 is completed.
【0026】上記のように構成された本実施の形態によ
れば、半導体チップ2、パッケージ基板1および半田バ
ンプ3のそれぞれの表面をそれらに対して密着性の高い
絶縁層6で被覆することにより、半導体チップ2に形成
された素子や、半田バンプ3と上部電極4との接続部を
水分や汚染物から確実に保護することができる。According to the present embodiment configured as described above, the respective surfaces of the semiconductor chip 2, the package substrate 1, and the solder bumps 3 are covered with the insulating layer 6 having high adhesion to them. In addition, the elements formed on the semiconductor chip 2 and the connection between the solder bump 3 and the upper electrode 4 can be reliably protected from moisture and contaminants.
【0027】また、半導体チップ2とパッケージ基板1
との隙間にアンダフィル樹脂5を充填することにより、
半導体チップ2とパッケージ基板1との熱膨張係数差に
起因して半田バンプ3に加わる応力を緩和することがで
きる。The semiconductor chip 2 and the package substrate 1
By filling the underfill resin 5 in the gap between
The stress applied to the solder bumps 3 due to the difference in thermal expansion coefficient between the semiconductor chip 2 and the package substrate 1 can be reduced.
【0028】さらに、本実施の形態によれば、ボンディ
ングパッドBPを形成する工程に先立って半導体チップ
2の表面保護膜をポリイミド樹脂で保護する工程が不要
となるので、ウエハプロセスを簡略化することができ
る。Further, according to the present embodiment, a step of protecting the surface protection film of the semiconductor chip 2 with a polyimide resin prior to the step of forming the bonding pad BP is not required, thereby simplifying the wafer process. Can be.
【0029】(実施の形態2)図5は、本実施の形態の
半導体装置を示す断面図である。前記実施の形態1では
パッケージ基板を樹脂で構成したパッケージについて説
明したが、本実施の形態は、熱膨張係数が半導体チップ
2のそれに近いムライトなどのセラミック材料でパッケ
ージ基板10を構成したセラミックパッケージである。(Embodiment 2) FIG. 5 is a sectional view showing a semiconductor device of the present embodiment. In the first embodiment, the package in which the package substrate is made of resin has been described. In the present embodiment, a ceramic package in which the package substrate 10 is made of a ceramic material such as mullite having a thermal expansion coefficient close to that of the semiconductor chip 2 is used. is there.
【0030】本実施の形態では、半導体チップ2とパッ
ケージ基板10との熱膨張係数差に起因して半田バンプ
3に加わる応力が小さいので、半導体チップ2とパッケ
ージ基板10との隙間にアンダフィル樹脂5を充填して
いないが、半導体チップ2に形成された素子や、半田バ
ンプ3と上部電極4との接続部を水分や汚染物から確実
に保護するために、それらの表面を前記実施の形態1で
用いた絶縁層6で被覆している。In this embodiment, since the stress applied to the solder bumps 3 due to the difference in the thermal expansion coefficient between the semiconductor chip 2 and the package substrate 10 is small, the underfill resin is formed in the gap between the semiconductor chip 2 and the package substrate 10. 5 are not filled, but in order to surely protect the elements formed on the semiconductor chip 2 and the connection between the solder bumps 3 and the upper electrode 4 from moisture and contaminants, the surfaces of the elements are the same as those of the above embodiment. It is covered with the insulating layer 6 used in 1.
【0031】上記のように構成された本実施の形態によ
れば、パッケージ基板10の主面に実装された半導体チ
ップ2をキャップなどで封止しなくとも、半田バンプ3
と上部電極4との接続部を水分や汚染物から確実に保護
することができるので、セラミックパッケージの製造コ
ストを低減することができる。According to the present embodiment configured as described above, the semiconductor bumps 2 mounted on the main surface of the package substrate 10 need not be sealed with a cap or the like.
It is possible to surely protect the connection between the electrode and the upper electrode 4 from moisture and contaminants, so that the manufacturing cost of the ceramic package can be reduced.
【0032】以上、本発明者によってなされた発明を前
記実施の形態に基づき具体的に説明したが、本発明は前
記実施の形態に限定されるものではなく、その要旨を逸
脱しない範囲で種々変更可能であることはいうまでもな
い。Although the invention made by the inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.
【0033】前記実施の形態では、バンプ電極を半田バ
ンプで構成したパッケージについて説明したが、バンプ
電極をAuボールで構成したパッケージに適用すること
もできる。In the above embodiment, the package in which the bump electrodes are formed by solder bumps has been described. However, the present invention can be applied to a package in which the bump electrodes are formed by Au balls.
【0034】前記実施の形態では、樹脂パッケージやセ
ラミックパッケージに適用した場合について説明した
が、例えばノート型パソコンや携帯端末機器に代表され
る薄形軽量電子機器に搭載するモジュール基板などに複
数個のベアチップをフリップチップ実装する場合に適用
することもできる。In the above-described embodiment, a case where the present invention is applied to a resin package or a ceramic package has been described. However, for example, a plurality of modules are mounted on a module substrate mounted on a thin and lightweight electronic device represented by a notebook personal computer or a portable terminal device. The present invention can also be applied to a case where a bare chip is flip-chip mounted.
【0035】[0035]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.
【0036】本発明によれば、半導体チップに形成され
た素子や、バンプ電極と電極との接続部を水分や汚染物
から確実に保護することができ、また、半導体チップと
配線基板との熱膨張係数差に起因してバンプ電極に加わ
る応力を緩和することができるので、バンプ電極と電極
とが接触する部分の接続信頼性が向上したパッケージを
得ることができる。According to the present invention, the elements formed on the semiconductor chip and the connection between the bump electrodes and the electrodes can be reliably protected from moisture and contaminants. Since the stress applied to the bump electrode due to the difference in expansion coefficient can be reduced, a package with improved connection reliability at the portion where the bump electrode and the electrode are in contact can be obtained.
【図1】本発明の一実施の形態である半導体装置を示す
断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
【図2】本発明の一実施の形態である半導体装置の製造
方法を示す断面図である。FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
【図3】本発明の一実施の形態である半導体装置の製造
方法を示す断面図である。FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
【図4】本発明の一実施の形態である半導体装置の製造
方法を示す断面図である。FIG. 4 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to one embodiment of the present invention;
【図5】本発明の他の実施の形態である半導体装置を示
す断面図である。FIG. 5 is a sectional view showing a semiconductor device according to another embodiment of the present invention;
1 パッケージ基板 2 半導体チップ 3 半田バンプ(バンプ電極) 4 上部電極 5 アンダフィル樹脂 6 絶縁層 6a 絶縁材料 7 下部電極 8 半田バンプ 10 パッケージ基板 BP ボンディングパッド REFERENCE SIGNS LIST 1 package substrate 2 semiconductor chip 3 solder bump (bump electrode) 4 upper electrode 5 underfill resin 6 insulating layer 6 a insulating material 7 lower electrode 8 solder bump 10 package substrate BP bonding pad
Claims (6)
成した半導体チップを配線基板の主面にフェイスダウン
接続し、前記半導体チップと前記配線基板との隙間にア
ンダフィル樹脂を充填した半導体装置であって、前記半
導体チップ、前記配線基板および前記バンプ電極のそれ
ぞれの表面を、前記アンダフィル樹脂よりも密着性がよ
い絶縁層で被覆したことを特徴とする半導体装置。1. A semiconductor device wherein a semiconductor chip having bump electrodes formed on bonding pads is face-down connected to a main surface of a wiring board, and a gap between the semiconductor chip and the wiring board is filled with an underfill resin. A semiconductor device, wherein the respective surfaces of the semiconductor chip, the wiring substrate and the bump electrode are covered with an insulating layer having better adhesion than the underfill resin.
記絶縁層は、ポリイミド樹脂を主体として構成されてい
ることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the insulating layer is mainly composed of a polyimide resin.
って、前記配線基板は、合成樹脂を主体として構成され
ていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the wiring substrate is mainly composed of a synthetic resin.
であって、前記バンプ電極は、半田またはAuで構成さ
れていることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the bump electrode is made of solder or Au.
成した半導体チップを、セラミックを主体として構成さ
れた配線基板の主面にフェイスダウン接続した半導体装
置であって、前記半導体チップ、前記配線基板および前
記バンプ電極のそれぞれの表面を、請求項1記載の絶縁
層で被覆したことを特徴とする半導体装置。5. A semiconductor device in which a semiconductor chip having bump electrodes formed on bonding pads is face-down connected to a main surface of a wiring board mainly composed of ceramic, wherein the semiconductor chip, the wiring board, and the A semiconductor device, wherein each surface of a bump electrode is covered with the insulating layer according to claim 1.
特徴とする半導体装置の製造方法; (a)ボンディングパッド上にバンプ電極を形成した半
導体チップを配線基板の主面にフェイスダウン接続する
工程、(b)前記半導体チップと前記配線基板との隙間
に、前記半導体チップの主面、前記配線基板の主面およ
び前記バンプ電極との密着性がアンダフィル樹脂よりも
よい絶縁材料を充填する工程、(c)前記半導体チップ
と前記配線基板との隙間に充填した前記絶縁材料の一部
を除去し、前記半導体チップ、前記配線基板および前記
バンプ電極のそれぞれの表面に前記絶縁材料で構成され
た絶縁層を形成する工程、(d)前記半導体チップと前
記配線基板との隙間にアンダフィル樹脂を充填する工
程。6. A method of manufacturing a semiconductor device, comprising the following steps (a) to (d): (a) placing a semiconductor chip having bump electrodes formed on bonding pads on a main surface of a wiring board; (B) an insulating material having better adhesion between the main surface of the semiconductor chip, the main surface of the wiring substrate, and the bump electrode than an underfill resin in a gap between the semiconductor chip and the wiring substrate; (C) removing a part of the insulating material filled in the gap between the semiconductor chip and the wiring board, and forming the insulating material on the respective surfaces of the semiconductor chip, the wiring board, and the bump electrodes. (D) filling the gap between the semiconductor chip and the wiring board with an underfill resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13013798A JPH11330158A (en) | 1998-05-13 | 1998-05-13 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13013798A JPH11330158A (en) | 1998-05-13 | 1998-05-13 | Semiconductor device and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11330158A true JPH11330158A (en) | 1999-11-30 |
Family
ID=15026853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13013798A Pending JPH11330158A (en) | 1998-05-13 | 1998-05-13 | Semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11330158A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
JP2006324271A (en) * | 2005-05-17 | 2006-11-30 | Renesas Technology Corp | Semiconductor device |
KR100665288B1 (en) | 2005-11-15 | 2007-01-09 | 삼성전기주식회사 | Flip chip package manufacturing method |
JP2011023619A (en) * | 2009-07-17 | 2011-02-03 | Kyocera Corp | Wiring board with bump, electronic component with bump, and mounting structure |
-
1998
- 1998-05-13 JP JP13013798A patent/JPH11330158A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002097877A1 (en) * | 2001-05-28 | 2002-12-05 | Infineon Technologies Ag | A method of packaging a semiconductor chip |
JP2006324271A (en) * | 2005-05-17 | 2006-11-30 | Renesas Technology Corp | Semiconductor device |
KR100665288B1 (en) | 2005-11-15 | 2007-01-09 | 삼성전기주식회사 | Flip chip package manufacturing method |
JP2011023619A (en) * | 2009-07-17 | 2011-02-03 | Kyocera Corp | Wiring board with bump, electronic component with bump, and mounting structure |
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