JPH05129525A - Semiconductor device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To suppress the current concentration at the edge of the drain diffusion region of the electrostatic discharge protection transistor and to improve the electrostatic breakdown voltage. In the protection transistor, an n ⁺ type embedded semiconductor region 11 is formed on a P type semiconductor substrate 10 by an ion implantation method, and a P type single crystal semiconductor layer 12 is formed by epitaxial growth. In the P-type single crystal semiconductor layer 12, n
P ⁺ type semiconductor region 1 for supplying potentials of n ⁺ type semiconductor region 13, P type semiconductor substrate 10 and P type single crystal semiconductor layer 12 electrically connected to ⁺ type buried semiconductor region 11
4. The n ⁺ type semiconductor regions 15 and 16 are formed on both ends of the silicon thermal oxide film 17, respectively. When a surge is applied to the n ⁺ type semiconductor regions 15 and 16, a snapback phenomenon occurs and the n ⁺ type semiconductor regions 15 and 16 move from the n ⁺ type semiconductor regions 15 and 16 to n ⁺ type semiconductor regions.
A surge current flows toward the mold-embedded semiconductor region 11. Since the surge current flows through the bottoms of the n ⁺ type semiconductor regions 15 and 16, thermal dissolution of silicon due to current concentration at the edges does not occur, and the electrostatic breakdown voltage can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for increasing the breakdown voltage of electrostatic breakdown caused by the application of surge.

[0002]

2. Description of the Related Art In recent years, the miniaturization of components in semiconductor integrated circuits has made great progress, and the minimum processing dimension has reached the so-called submicron region of 1 μm or less. However, on the other hand, the breakdown voltage of electrostatic breakdown has come to decrease. Although electrostatic breakdown occurs in an internal circuit or a protection circuit, in reality, the protection circuit is often destroyed, and improving reliability of the protection transistor against electrostatic breakdown has become a major problem.

A conventional electrostatic breakdown protection transistor will be described below with reference to the drawings.

FIG. 2 shows a conventional MOS type electrostatic breakdown protection transistor. In FIG. 2, 100 is P
Type semiconductor substrate. 1 is an n ⁺ type drain diffusion region,
2 is an n ⁺ type source diffusion region, 3 is a P type semiconductor substrate 10
A P ⁺ type diffusion region for taking a potential of 0 and 6 is a gate oxide film. A drain electrode 8 is connected to the pad. A source electrode 9 is also connected to the P ⁺ type diffusion region 3. Reference numeral 7 is a polysilicon serving as a gate electrode, which is electrically connected to the source electrode 9.

The operation of the electrostatic breakdown protection transistor having the above structure will be described below.

In the MOS type electrostatic breakdown protection transistor as shown in FIG. 2, the n ⁺ type drain diffusion region 1, the P type semiconductor substrate 100 and the n ⁺ type source diffusion region 2 are parasitic NPN bipolar transistors. Surge current I _s escapes by snapback phenomenon (IEEE Transactions on Electron Devices, Vol.35, N
o.12, December 1988 page 2140). When a surge voltage is applied from the pad to the drain diffusion region 1, an avalanche current due to a high electric field is generated near the drain diffusion region 1 under the gate oxide film 6. This avalanche current is P
The P-type semiconductor substrate 10 near the drain diffusion region 1 and the source diffusion region 2 flows toward the ⁺ type diffusion region 3.
The potential of 0 rises, the NPN bipolar transistor is turned on, and the surge current I _s flows from the drain diffusion region 1 to the source diffusion region 2. In this way, the protection transistor releases the surge current I _s so that the internal circuit is not loaded.

[0007]

However, in the above structure, when a surge voltage is applied, the edge portion at the bottom of the n ⁺ type drain diffusion region 1, particularly the edge portion at the side of the n ⁺ type source diffusion region 2, is formed. Electric field concentrates. Therefore, the surge current I _s concentrates on this edge portion, and heat concentration occurs, resulting in destruction such as thermal melting.

In view of the above problems, the present invention provides a semiconductor device having a high electrostatic breakdown voltage by suppressing the electric field concentration on the edge portion of the diffusion region.

[0009]

In order to solve the above problems, the present invention provides a high-concentration first-conductivity-type first semiconductor region and an upper surface of the first-conductivity-type first semiconductor region. A second conductivity type semiconductor layer in contact with the second conductivity type semiconductor layer, a high concentration second conductivity type semiconductor region formed in the second conductivity type semiconductor layer, and the first conductivity type first semiconductor region are connected. A high concentration first conductivity type second semiconductor region formed in the second conductivity type semiconductor layer, the second conductivity type semiconductor region and the first conductivity type second semiconductor region. Electrically connected to the first electrode, an insulating film formed in a predetermined region on the second conductive type semiconductor layer, and formed on the insulating film so as to be electrically connected to the first electrode. Second electrode and a high-concentration first conductivity formed at an end of the insulating film in the second-conductivity-type semiconductor layer. A third semiconductor region of, and having a third electrode connected said first to third semiconductor regions of the conductivity type electrically.

[0010]

According to the present invention, the following actions can be obtained. When a surge voltage is applied from the pad to the first conductivity type second semiconductor region, a high electric field is generated in the vicinity of the first conductivity type second semiconductor region of the second conductivity type semiconductor layer below the insulating film. .. Avalanche current is generated by this high electric field. Further, due to this avalanche current, a snapback phenomenon of bipolar operation occurs between the second semiconductor region of the first conductivity type, the semiconductor layer of the second conductivity type, and the semiconductor layer of the first conductivity type, and a surge current flows. At this time, surge current flows from the entire bottom of the first conductivity type second semiconductor region, and current concentration does not occur at the edge. This can improve the electrostatic breakdown voltage.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an electrostatic breakdown protection transistor according to an embodiment of the present invention. In the protection transistor shown in FIG. 1, a high-concentration N-type (hereinafter referred to as n ⁺ -type) buried semiconductor region 11 is formed on a single-crystal P-type semiconductor substrate 10 by an ion implantation method, and is further epitaxially grown thereon. The P-type single crystal semiconductor layer 12 is formed. In order to supply the potentials of the n ⁺ type semiconductor region 13, the P type semiconductor substrate 10 and the P type single crystal semiconductor layer 12 which are electrically connected to the n ⁺ type embedded semiconductor region 11, into the P type single crystal semiconductor layer 12. High concentration P type
N ⁺ type semiconductor regions 15 and 16 are formed at both ends of the semiconductor region 14 (hereinafter referred to as p ⁺ type) and the silicon thermal oxide film 17, respectively. Furthermore, on the n ⁺ type semiconductor region 13 and p ⁺
An electrode 21 formed of aluminum wiring on the type semiconductor region 14, a polysilicon electrode 18 electrically connected to the electrode 21 on the silicon thermal oxide film 17, and a pad on the n ⁺ type semiconductor regions 15 and 16, respectively. And aluminum electrodes 22 and 23 connected to.

In the protection transistor configured as described above, when a high voltage due to a surge is applied to the pad from the outside, the P-type single crystal semiconductor layer 1 under the silicon thermal oxide film 17 is applied.
A high electric field is generated in the vicinity of the n ⁺ type semiconductor regions 15 and 16 of 2 and the avalanche current starts to flow toward the p ⁺ type semiconductor region 14. This avalanche current raises the potential of the P-type single crystal semiconductor layer 12 in the vicinity of the n ⁺ type semiconductor regions 15 and 16, and a snapback phenomenon occurs to cause the n ⁺ type semiconductor regions 15 and 16 to move to the n ⁺ type buried semiconductor region 11. Surge current flows toward. At this time, the surge current is n ⁺
Since it flows through the bottoms of the type semiconductor regions 15 and 16, thermal melting of silicon due to current concentration at the edges does not occur,
Therefore, the electrostatic breakdown voltage can be improved.

Although the P-type single crystal semiconductor layer 12 is formed by epitaxial growth in the above embodiment, the P-type single crystal semiconductor layer 12 may be formed by ion implantation after the N-type single crystal semiconductor layer is epitaxially grown.

Further, in the above embodiment, the protection transistor for performing the NPN type bipolar operation is formed.
It goes without saying that a protection transistor that performs P-type bipolar operation may be formed.

[0016]

As described above, according to the present invention, a high-concentration first-conductivity-type semiconductor layer and a high-concentration first-conductivity-type second semiconductor region are formed with a second-conductivity-type semiconductor layer interposed therebetween. As a result, it is possible to suppress the concentration of the surge current to the edge portion of the second semiconductor region of the first conductivity type and realize the protection transistor having a high breakdown voltage.

[Brief description of drawings]

FIG. 1 is an element sectional view of an electrostatic breakdown protection transistor according to an embodiment of the present invention.

FIG. 2 is an element cross-sectional view of a conventional MOS type electrostatic breakdown protection transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 n ⁺ type drain diffusion region 2 n ⁺ type source diffusion region 8 drain electrode 9 source electrode 10 P type semiconductor substrate 11 n ⁺ type buried semiconductor region 12 P type semiconductor layer 13 n ⁺ type semiconductor region 14 P ⁺ type semiconductor Region 14 P ⁺ type diffusion region 15 n ⁺ type semiconductor region 16 n ⁺ type semiconductor region 17 Gate oxide film 18 Polysilicon electrode 19 Silicon thermal oxide film 20 Silicon oxide film 21 Aluminum electrode 22 Aluminum electrode 23 Aluminum electrode

Claims (1)

[Claims] 1. A high-concentration first-conductivity-type first semiconductor region, a second-conductivity-type semiconductor layer in contact with an upper surface of the first-conductivity-type first semiconductor region, and a second-conductivity-type semiconductor layer. A high-concentration second-conductivity-type semiconductor region formed in the semiconductor layer and a high-concentration high-concentration formed in the second-conductivity-type semiconductor layer so as to connect to the first-conductivity-type first semiconductor region A second semiconductor region of the first conductivity type, a first electrode electrically connecting the second conductivity type semiconductor region and the second semiconductor region of the first conductivity type, and a second electrode of the second conductivity type. An insulating film formed in a predetermined region on the semiconductor layer, a second electrode formed on the insulating film so as to be electrically connected to the first electrode, and a semiconductor layer of the second conductivity type. A high-concentration first-conductivity-type third semiconductor region formed at an end of the insulating film, and the first-conductivity-type third semiconductor Wherein a and a third electrode electrically connected to the band.