JP4029549B2

JP4029549B2 - Semiconductor device

Info

Publication number: JP4029549B2
Application number: JP2000223504A
Authority: JP
Inventors: 豊田島; 俊朗篠原; 良雄下井田; 輝儀三原; 星　　正勝
Original assignee: Nissan Motor Co Ltd
Current assignee: Nissan Motor Co Ltd
Priority date: 2000-07-25
Filing date: 2000-07-25
Publication date: 2008-01-09
Anticipated expiration: 2020-07-25
Also published as: JP2002043586A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体支持基板の表面（主面）上に誘電体を介して半導体領域が形成された半導体装置に関する。
【０００２】
【従来の技術】
一般に、半導体装置として、例えば半導体支持基板をなすシリコン基板上にシリコン酸化膜等の誘電体を介してｐ形シリコンまたはｎ形シリコンからなるシリコン領域を形成したものが知られている（例えば、特開平７−３１２４２４号公報等）。
【０００３】
このような従来技術の半導体装置にあっては、静電気やサージ電圧による過剰電流によってＭＯＳトランジスタが破壊されるのを防止するために大電流を流すことが可能なダイオードが形成されている。そして、このダイオードは、シリコン領域の表面にアノード側高濃度拡散領域とカソード側高濃度拡散領域とを形成したプレーナ構造を採用している。また、ダイオードのカソード側高濃度拡散領域は、例えばアノード側高濃度拡散領域の外周側を取り囲むように配置され、アノード側高濃度拡散領域とカソード側高濃度拡散領域との間には誘電体が設けられると共に、アノード側高濃度拡散領域とカソード側高濃度拡散領域とはこれらの底面側に設けられた多結晶シリコンを通じて電気的に接続されている。
【０００４】
【発明が解決しようとする課題】
ところで、上述した従来技術による半導体装置では、ダイオードのアノード側高濃度拡散領域とカソード側高濃度拡散領域とをいずれもシリコン領域の表面に形成したプレーナ構造を採用している。このため、サージ印加時には、サージ電流が抵抗が最小となる最短経路を流れるから、サージ電流はｐｎ接合の端部をなすアノード側高濃度拡散領域の外周端側に集中する。この結果、大電流となるサージ電流が微小なｐｎ接合の端部に集中して流れるから、ダイオードが損傷し易いという問題がある。
【０００５】
また、プレーナ構造のダイオードでは、破壊耐量を上げるためには、アノードとカソードとの間隔を広くし、抵抗成分を大きくする必要がある。しかし、このようにしてサージ電流の大きさを制限した場合には、サージ電流が内部回路に流れ込み、内部回路が損傷する虞れがある。
【０００６】
さらに、従来技術による半導体装置では、アノード側高濃度拡散領域とカソード側高濃度拡散領域との間には誘電体を設けるため、誘電体を形成するための工程を追加する必要があり、製造時間が長くなるという問題もある。
【０００７】
本発明は上述した従来技術の問題に鑑みなされたもので、本発明の目的は、サージ電流の集中を防ぎ、耐久性、信頼性を向上できるようにした半導体装置を提供することにある。
【０００８】
【課題を解決するための手段】
上述した課題を解決するために請求項１の発明による半導体装置は、半導体支持基板主面上に誘電体を介して第２導電形の半導体領域を形成すると共に、該第２導電形の半導体領域の底面に第２導電形の高濃度埋込み領域を形成し、前記第２導電形の半導体領域主面に第１導電形の半導体領域を該第２導電形の高濃度埋込み領域に面接触状態で接するように設け、該第１導電形の半導体領域主面に第１導電形の高濃度領域を設けると共に、前記第２導電形の半導体領域主面に第２導電形の高濃度領域を設け、前記第１導電形の半導体領域と第２導電形の半導体領域との間には第１のダイオードを形成すると共に、前記第１導電形の半導体領域と第２導電形の高濃度埋込み領域との間には第２のダイオードを形成し、かつ該第１導電形の高濃度領域と第２導電形の高濃度領域との間に位置し、第２導電形の半導体領域主面に設けられ、前記誘電体に接すると共に、前記第１，第２のダイオードのｐｎ接合箇所に接触しないようにトレンチ溝型絶縁領域を形成し、前記第１導電形の高濃度領域と第２導電形の高濃度領域とのうちいずれか一方を入力端子、出力端子、高電位端子、低電位端子のうちいずれかの端子に接続すると共に、他方を残余のいずれかの端子に接続し、前記第１のダイオードから第２導電形の半導体領域を通じて第２導電形の高濃度領域に至る第１の電流経路と、前記第２のダイオードから第２導電形の高濃度埋込み領域を通じて第２導電形の高濃度領域に至る第２の電流経路とは、いずれも前記トレンチ溝型絶縁領域を迂回する構成としている。
【０００９】
このように構成することにより、第１導電形の半導体領域と第２導電形の半導体領域との間には第１のダイオードを形成することができると共に、第１導電形の半導体領域と第２導電形の高濃度埋込み領域との間には第２のダイオードを形成することができ、これら２つのダイオードを保護ダイオードとして作用させることができる。このとき、第２導電形の高濃度埋込み領域は第２導電形の半導体領域よりも不純物濃度が高く、第１導電形の半導体領域と第２導電形の高濃度埋込み領域とは曲率の小さい面接触状態にできるから、第１のダイオードに比べて第２のダイオードのブレークダウン電圧を低くすることができる。
【００１０】
また、第１導電形の半導体領域と第２導電形の高濃度領域との間にはトレンチ溝型絶縁領域を形成したから、これらの間を流れる電流はトレンチ溝型絶縁領域を迂回して流れる。このため、第１のダイオードから第２導電形の半導体領域を通じて第２導電形の高濃度領域に至る第１の電流経路、第２のダイオードから第２導電形の高濃度埋込み領域を通じて第２導電形の高濃度領域に至る第２の電流経路は、いずれもトレンチ溝型絶縁領域を迂回する分だけ長くなる。また、第２導電形の高濃度埋込み領域は第２導電形の半導体領域よりも不純物濃度が高くなっているから、第１，第２の電流経路が長くなるほど第１の電流経路の寄生抵抗は第２の電流経路の寄生抵抗よりも顕著に大きくなる。
【００１１】
この結果、正負いずれの過電圧サージが印加されるときであっても、サージ電流の大部分を、ブレークダウン電圧が低く、かつ寄生抵抗が小さい第２のダイオードに流すことができる。そして、第２のダイオードは第１導電形の半導体領域と第２導電形の高濃度埋込み領域とを面接触させることによって形成できるから、サージ電流が微小な端部に集中するのを防ぐことができる。
また、トレンチ溝型絶縁領域が第１，第２のダイオードのｐｎ接合箇所に接触することがない。このため、ｐｎ接合がトレンチ溝型絶縁領域に接触したときにトレンチ溝型絶縁領域に沿って流れるリーク電流が発生することがないから、第１，第２のダイオードの整流特性等が劣化することがなく、高特性を維持することができる。
【００１２】
また、請求項２の発明は、前記第１導電形の高濃度領域主面上にパッド電極を設け、第１導電形の高濃度領域と該パッド電極とを接続したことにある。
【００１３】
これにより、パッド電極下に第２のダイオードを形成することができるから、半導体装置の集積度を損なうことなく、高集積度を保持することができる。また、サージ電流は互いに面接触するパッド電極と第１導電形の高濃度領域との間で流れるから、サージ電流を第１導電形の高濃度領域の全体に略均一に流すことができる。この結果、第１導電形の高濃度領域と第２導電形の高濃度埋込み領域との間に形成される第２のダイオードのｐｎ接合部分にも、電流密度がより均一な状態でサージ電流を流すことができ、第２のダイオードの耐量を高めることができる。
【００１４】
さらに、請求項３の発明は、前記第１導電形の高濃度領域を挟んで前記一の第２導電形の高濃度領域とは反対側に位置して第２導電形の半導体領域主面には他の第２導電形の高濃度領域を設け、かつ前記第１導電形の高濃度領域と他の第２導電形の高濃度領域との間に位置し、第２導電形の半導体領域主面に設けられ、前記誘電体に接すると共に、前記第１，第２のダイオードのｐｎ接合箇所に接触しないように他のトレンチ溝型絶縁領域を形成し、前記一のトレンチ溝型絶縁領域および他のトレンチ溝型絶縁領域は、いずれもコ字形状をなして互いに離間して配置し、前記他の第２導電形高濃度領域を前記一の第２導電形の高濃度領域に接続する構成としたことにある。
【００１５】
これにより、２つの第２導電形の高濃度領域を設けるから、単一の第２導電形の高濃度領域を設けたときに比べて第２導電形の高濃度領域全体の面積を大きくすることができる。このため、第１導電形の半導体領域と第２導電形の半導体領域との間に形成される第１のダイオード、第１導電形の半導体領域と第２導電形の高濃度埋込み領域との間に形成される第２のダイオードは、いずれも抵抗成分が小さくなる。従って、第１，第２のダイオード全体のインピーダンスが小さくなり、サージ印加時の入力端子電圧等の電位上昇をより確実に抑えることができ、内部回路に注入されるサージ電流を抑制することができる。
【００１６】
また、第１導電形の高濃度領域と２つの第２導電形の高濃度領域との間にはトレンチ溝型絶縁領域をそれぞれ設けると共に、これら２つのトレンチ溝型絶縁領域はいずれもコ字形状をなして互いに離間して配置したから、第１導電形の高濃度領域から第２導電形の半導体領域を通じて第２導電形の高濃度領域に至る第１の電流経路、第１導電形の高濃度領域から第２導電形の高濃度埋込み領域を通じて第２導電形の高濃度領域に至る第２の電流経路は、いずれもコ字形状のトレンチ溝型絶縁領域を迂回する分だけより一層長くなる。このため、第１の電流経路の寄生抵抗と第２の電流経路の寄生抵抗との抵抗差を大きくすることができ、第１の電流経路の寄生抵抗を第２の電流経路の寄生抵抗よりも一層大きくすることができる。従って、サージ電流のほとんどは第１導電形の高濃度領域と第２導電形の高濃度埋込み領域との間に形成される第２のダイオードを通じて流れるから、半導体装置の損傷を防ぐことができる。
【００１７】
【発明の実施の形態】
以下、本発明の実施の形態による半導体装置を図１ないし図８を参照して詳細に説明する。
【００１８】
まず、図１ないし図３は本発明の第１の実施の形態を示し、図において、１は例えばシリコン材料からなるシリコン支持基板で、該シリコン支持基板１の表面上には、シリコン酸化膜等の誘電体膜２が設けられると共に、該誘電体膜２を介してｎ形シリコンからなるｎ形領域３が形成されている。これにより、シリコン支持基板１、誘電体膜２、ｎ形領域３はＳＯＩ（ＳｉｌｉｃｏｎＯｎＩｎｓｕｌａｔｏｒ）構造をなすと共に、ｎ形領域３は、例えば単結晶シリコン材料に砒素等の不純物を低濃度（例えば１０¹⁵〜１０¹⁶ｃｍ^-3程度）に添加することによって形成されている。
【００１９】
４はｎ形領域３に設けられた枠状トレンチ溝型絶縁領域で、該枠状トレンチ溝型絶縁領域４は、略四角形の枠状に形成され、その底部は誘電体膜２に達している。そして、枠状トレンチ溝型絶縁領域４は、ｎ形領域３をその内側に位置する内側ｎ形領域３Ａと外側に位置する外側ｎ形領域３Ｂとに区切り、これらを絶縁状態に分離している。また、内側ｎ形領域３Ａには後述のｐ形領域６等からなる保護ダイオードが形成されると共に、外側ｎ形領域３Ｂには例えば各種の処理を行う内部回路（図示せず）等が形成されている。
【００２０】
５はｎ形領域３の底面全体に設けられたｎ形高濃度埋込み領域で、該ｎ形高濃度埋込み領域５は、ｎ形領域３と誘電体膜２との間に配設され、砒素等の不純物を高濃度（例えば１０¹⁸〜１０¹⁹ｃｍ^-3程度）に添加することによって形成されている。また、ｎ形高濃度埋込み領域５も枠状トレンチ溝型絶縁領域４に区切られ、枠状トレンチ溝型絶縁領域４の内側に位置する内側ｎ形高濃度埋込み領域５Ａと外側に位置する外側ｎ形高濃度埋込み領域５Ｂとは絶縁状態に分離されている。
【００２１】
６は内側ｎ形領域３Ａの表面に設けられたｐ形領域で、該ｐ形領域６は、略四角形状をなして内側ｎ形領域３Ａの中央に配置され、その底面が内側ｎ形高濃度埋め込み領域５Ａに面接触している。また、ｐ形領域６は、内側ｎ形領域３Ａの表面側から硼素等の不純物を低濃度（例えば１０¹⁵〜１０¹⁶ｃｍ^-3程度）に拡散することによって形成されている。
【００２２】
７はｐ形領域６の表面に設けられたｐ形高濃度領域で、該ｐ形高濃度領域７は、略四角形状をなしてｐ形領域６の中央に配置されている。また、ｐ形高濃度領域７は、ｐ形領域６に硼素等の不純物を高濃度に拡散することによって形成されている。そして、ｐ形高濃度領域７は、例えば接地端子等の低電位端子に接続されている。
【００２３】
８は内側ｎ形領域３Ａの表面に設けられたｎ形高濃度領域で、該ｎ形高濃度領域８は、略四角形状をなすｐ形領域６の一辺に対して略中央側に位置し、ｐ形領域６から離間してｐ形領域６と枠状トレンチ溝型絶縁領域４との間に配置されている。また、ｎ形高濃度領域８は、内側ｎ形領域３Ａに砒素等の不純物を高濃度に拡散することによって形成されている。そして、ｎ形高濃度領域８は、低電位端子とは異なる端子として例えば入力端子に接続されている。
【００２４】
９はｐ形領域６とｎ形高濃度領域８との間に位置して内側ｎ形領域３Ａの表面に設けられたトレンチ溝型絶縁領域で、該トレンチ溝型絶縁領域９は、ｐ形領域６の一辺に対して略平行に延びた直線状に形成され、その長さ寸法はｐ形領域６の一辺よりも長くなっている。また、トレンチ溝型絶縁領域９は、その底部が全長に亘って誘電体膜２に接するものの、直線状に延びる両端は枠状トレンチ溝型絶縁領域４に接触せず、枠状トレンチ溝型絶縁領域４との間に隙間が形成されている。
【００２５】
本実施の形態による半導体装置は上述の如き構成を有するもので、次にその作動について説明する。
【００２６】
まず、ｐ形領域６は内側ｎ形領域３Ａの中央側に設けられているから、その外周側にはｐｎ接合による第１のダイオード１０が形成されている。また、ｐ形領域６の底面は略全面に亘って内側ｎ形高濃度埋込み領域５Ａに接触しているから、ｐ形領域６の底面側にもｐｎ接合による第２のダイオード１１が形成されている。このため、これらのダイオード１０，１１は、半導体装置の保護ダイオードとして作用する。
【００２７】
ここで、内側ｎ形高濃度埋込み領域５Ａの不純物濃度は内側ｎ形領域３Ａよりも高く設定されている。このため、第１のダイオード１０に比べて第２のダイオード１１のブレークダウン電圧は、低く設定されている。
【００２８】
また、以下の理由によって第２のダイオード１１の抵抗成分は、第１のダイオード１０の抵抗成分よりも小さい値となる。即ち、ｐ形領域６とｎ形高濃度領域８との間には、第１のダイオード１０のカソード側にてｐｎ接合から内側ｎ形領域３Ａを通る第１の電流経路と第２のダイオード１０のカソード側にてｐｎ接合から内側ｎ形高濃度埋込み領域５Ａを通る第２の電流経路とが形成される。ここで、ｐ形領域６とｎ形高濃度領域８との間にはトレンチ溝型絶縁領域９を形成したから、これらの間を流れる電流は、トレンチ溝型絶縁領域９を迂回して、トレンチ溝型絶縁領域９の長さ方向の両端側を通じて流れる。このため、第１，第２の電流経路は、トレンチ溝型絶縁領域９を設けないときに比べてトレンチ溝型絶縁領域９の長さ寸法に応じた分だけ長くなる。また、内側ｎ形高濃度埋込み領域５Ａの不純物濃度は１０¹⁸〜１０¹⁹ｃｍ^-3に設定され内側ｎ形領域３Ａの不純物濃度である１０¹⁵〜１０¹⁶ｃｍ^-3よりも高くなっているから、第２の電流経路（第２のダイオード１１のカソード側）の寄生抵抗は、第１の電流経路（第１のダイオード１０のカソード側）の寄生抵抗と比較して１０^-3倍程度になる。このため、第１，第２の電流経路が長くなるほど第２のダイオード１１の寄生抵抗成分は、第１のダイオード１０の寄生抵抗成分よりも顕著に小さくなる。
【００２９】
この結果、入力端子に正の過電圧サージが印加された場合には、サージ電流の大部分は、ブレークダウン電圧が低く、寄生抵抗も小さい第２のダイオード１１を流れる。即ち、サージ電圧の立ち上がり時に第１のダイオード１０よりも先に第２のダイオード１１がブレークダウンし、その後も寄生抵抗の小さい第２のダイオード１１にほとんどの電流が流れることになる。
【００３０】
また、第２のダイオード１１のｐｎ接合はｐ形領域６と内側ｎ形高濃度埋込み領域５Ａとの間に形成されるから、ダイオード１１のｐｎ接合は平面接合とみなすことができる。また、内側ｎ形高濃度埋込み領域５Ａの抵抗は小さい値となっている。このため、ダイオード１１を流れる電流（ダイオード電流）は近似的に一元的に流れ、ｐｎ接合の全体に亘って略均一な電流密度となる。従って、ダイオード電流がｐｎ接合の一部に集中することがないから、ダイオードの損傷を防ぐことができる。
【００３１】
さらに、ダイオード１１自体の寄生抵抗成分が小さいので、サージによる入力端子電圧の上昇を抑えることができ、サージ電流が入力端子に接続された内部回路に流れ込むのを防ぐことができる。このため、内部回路の損傷も防ぐことができる。
【００３２】
また、ダイオード１１から内側ｎ形高濃度埋込み領域５Ａを通じて大部分のサージ電流を流すことができるから、サージ電流の上昇を抑制することができ、ｐ形領域６とｎ形高濃度領域８との間の間隔を拡げることによってダイオードの破壊耐量を大きくする必要がない。このため、半導体装置の集積度を損なうことがなく、高集積度を保持することができる。
【００３３】
さらに、トレンチ溝型絶縁領域９は枠状トレンチ溝型絶縁領域４と同様に誘電体膜２に接触する構成としたから、トレンチ溝型絶縁領域９を枠状トレンチ溝型絶縁領域４と同時に加工、形成することができる。このため、半導体装置の製造時にトレンチ溝型絶縁領域９を加工するための工程を独立して設ける必要がないから、追加の加工工程が必要となる従来技術に比べて製造時間を短縮でき、生産性を向上することができる。
【００３４】
また、トレンチ溝型絶縁領域９が第１，第２のダイオード１０，１１のｐｎ接合箇所に接触することがない。このため、ｐｎ接合がトレンチ溝型絶縁領域９に接触したときにトレンチ溝型絶縁領域９に沿って流れるリーク電流が発生することがないから、ダイオード１０，１１の整流特性等が劣化することがなく、高特性を維持することができる。
【００３５】
一方、入力端子に負の過電圧サージが印加された場合には、第１，第２のダイオード１０，１１は順バイアスされる。このとき、第１のダイオード１０に比べて第２のダイオード１１の方が抵抗成分が顕著に小さいから、正の過電圧サージが印加された場合と同様にサージ電流の大部分は、ダイオード１１を流れる。また、ダイオード１１を流れるダイオード電流は、近似的に一元的に流れ、ｐｎ接合の全体に亘って略均一な電流密度となるから、ダイオード電流の集中を防ぐことができる。このように、サージ電流が流れる方向以外は正の過電圧サージが印加された場合と変わることがないため、負の過電圧サージが印加された場合であっても前述と同様の作用効果を得ることができる。
【００３６】
かくして、本実施の形態では、ｐ形領域６を内側ｎ形高濃度埋込み領域５Ａに面接触状態で設けると共に、ｐ形領域６（ｐ形高濃度領域７）とｎ形高濃度領域８との間にはトレンチ溝型絶縁領域９を設けたから、正負いずれの過電圧サージが印加されるときであっても、サージ電流の大部分を、ブレークダウン電圧が低く、かつ寄生抵抗が小さい第２のダイオード１１に流すことができる。このとき、ダイオード電流がｐｎ接合の一部に集中することがないから、半導体装置の損傷を防ぐことができ、信頼性、耐久性を高めることができる。また、ｐ形領域６とｎ形高濃度領域８との間隔を狭くすることができるから、半導体装置の高集積度を維持できる。さらに、従来技術に比べて製造時間を短縮でき、生産性を向上できる等の種々の効果を奏する。
【００３７】
次に、図４は本発明の第２の実施の形態を示し、本実施の形態の特徴は、ｐ形高濃度領域の表面上にパッド電極を設け、ｐ形高濃度領域と該パッド電極とを接続したことにある。なお、本実施の形態では、前述した第１の実施の形態と同一の構成要素に同一の符号を付し、その説明を省略するものとする。
【００３８】
２１はｎ形領域３の表面に設けられた酸化膜で、該酸化膜２１はフィールド酸化膜をなし、ｐ形高濃度領域７の表面側が開口している。
【００３９】
２２はｐ形高濃度領域７の表面上に設けられたパッド電極で、該パッド電極は導電性金属材料からなり、ｐ形高濃度領域７に電気的に接続されると共に、低電圧端子に接続されている。
【００４０】
かくして、本実施の形態でも第１の実施の形態と同様の作用効果を得ることができる。しかし、本実施の形態では、パッド電極２２の直下にダイオード１１を形成することができるから、他の部位にパッド電極２２を設けた場合に比べて半導体装置の集積度を損なうことがなく、高集積度を保持することができる。
【００４１】
また、サージ電流はパッド電極２２から下方向（ｎ形領域３の厚さ方向）に均一に流れていくから、ｐ形領域６内部の電流も均一に分布し、ダイオード１１のｐｎ接合部分の電流密度もより一層均一化することができる。
【００４２】
然るに、サージ電流のような大きな電流が流れる場合、パッド電極２２等の金属配線領域の抵抗も大きく影響してくる。ここで、パッド電極２２がダイオード１１の上以外の位置に設けられていると、サージ電流は酸化膜２１上の配線領域を経てｐ形高濃度領域７に注入される。このとき、配線領域中の抵抗によって配線領域内部に電位分布が生じているため、サージ電流は最短経路として配線領域からｐ形高濃度領域７の端部（外周部）に流れ込む割合が多くなる。このため、ダイオード１１のｐｎ接合に流れる電流密度も完全に均一化することは難しい。
【００４３】
これに対し、本実施の形態では、ダイオード１１のｐｎ接合部分の電流密度をより一層完全に近い形で均一化することができるから、正負いずれの過電圧サージが印加されるときであってもダイオード１１等の損傷が生じにくくでき、ダイオード１１の耐圧を高め、信頼性、耐久性をさらに向上することができる。
【００４４】
次に、図５および図６は本発明の第３の実施の形態を示し、本実施の形態の特徴は、ｎ形領域の表面上にｐ形高濃度領域を挟んで２つのｎ形高濃度領域を設けると共に、ｐ形高濃度領域と各ｎ形高濃度領域との間にはコ字形状のトレンチ溝型絶縁領域をそれぞれ設けたことにある。なお、本実施の形態では、前述した第１の実施の形態と同一の構成要素に同一の符号を付し、その説明を省略するものとする。
【００４５】
３１は内側ｎ形領域３Ａの表面に設けられた第１のｎ形高濃度領域で、該ｎ形高濃度領域３１は、第１の実施の形態によるｎ形高濃度領域８と同様に内側ｎ形領域３Ａに砒素等の不純物を高濃度に拡散することによって形成されている。また、ｎ形高濃度領域３１は、略四角形状をなすｐ形領域６の一辺に対して略中央側に位置し、ｐ形領域６から離間してｐ形領域６と枠状トレンチ溝型絶縁領域４との間に配置されている。そして、ｎ形高濃度領域３１は、低電位端子とは異なる端子として例えば入力端子に接続されている。
【００４６】
３２は内側ｎ形領域３Ａの表面に設けられた第２のｎ形高濃度領域で、該ｎ形高濃度領域３２は、ｎ形高濃度領域８と同様に内側ｎ形領域３Ａに砒素等の不純物を高濃度に拡散することによって形成されている。また、ｎ形高濃度領域３２は、ｐ形高濃度領域７（ｐ形領域６）を挟んでｎ形高濃度領域８とは反対側に位置し、ｐ形領域６から離間してｐ形領域６と枠状トレンチ溝型絶縁領域４との間に配置されている。そして、ｎ形高濃度領域３２は、図６中に一点鎖線で示すように配線等によってｎ形高濃度領域３１に接続されている。
【００４７】
３３はｐ形領域６と第１のｎ形高濃度領域３１との間に位置して内側ｎ形領域３Ａの表面に設けられた第１のトレンチ溝型絶縁領域で、該トレンチ溝型絶縁領域３３は、ｐ形領域６の一辺に対して略平行な直線状に延びると共に、その両端がｐ形領域６に向けて屈曲したコ字形状に形成されている。これにより、トレンチ溝型絶縁領域３３は、ｐ形領域６の外周に沿って延び、ｐ形領域６を部分的に取り囲んでいる。また、トレンチ溝型絶縁領域３３は、その底部が全長に亘って誘電体膜２に接するものの、その両端は枠状トレンチ溝型絶縁領域４に接触せず、枠状トレンチ溝型絶縁領域４との間に隙間が形成されている。
【００４８】
３４はｐ形領域６と第２のｎ形高濃度領域３２との間に位置して内側ｎ形領域３Ａの表面に設けられた第２のトレンチ溝型絶縁領域で、該トレンチ溝型絶縁領域３４は、ｐ形領域６を挟んでトレンチ溝型絶縁領域３３と反対側の位置に配設され、その両端がｐ形領域６に向けて屈曲したコ字形状に形成されている。これにより、トレンチ溝型絶縁領域３４は、ｐ形領域６の外周に沿って延び、ｐ形領域６を部分的に取り囲んでいる。また、トレンチ溝型絶縁領域３４は、その底部が全長に亘って誘電体膜２に接するものの、その両端は枠状トレンチ溝型絶縁領域４、トレンチ溝型絶縁領域３３には接触せず、枠状トレンチ溝型絶縁領域４、トレンチ溝型絶縁領域３３との間に隙間が形成されている。
【００４９】
かくして、本実施の形態でも第１の実施の形態と同様の作用効果を得ることができる。しかし、本実施の形態では、内側ｎ形領域３Ａの表面上にｐ形高濃度領域７を挟んで２つのｎ形高濃度領域３１，３２を設けたから、第１の実施の形態のように単一のｎ形高濃度領域８を設けたときに比べてｎ形高濃度領域３１，３２全体の面積を大きくすることができる。このため、ｐ形領域６と内側ｎ形領域３Ａとの間に形成される第１のダイオード３５、ｐ形領域６と内側ｎ形高濃度埋込み領域５Ａとの間に形成される第２のダイオード３６は、いずれも抵抗成分が小さくなる。従って、第１，第２のダイオード３５，３６全体のインピーダンスが小さくなり、サージ印加時の入力端子電圧の電位上昇をより確実に抑えることができるから、内部回路に注入されるサージ電流をより一層抑制することができ、半導体装置の損傷を防ぎ、信頼性等を向上することができる。
【００５０】
また、トレンチ溝型絶縁領域３３，３４は両端が屈曲したコ字形状に形成したから、ｐ形高濃度領域７から内側ｎ形領域３Ａを通じてｎ形高濃度領域３１，３２に至る第１の電流経路、ｐ形高濃度領域７から内側ｎ形高濃度埋込み領域５Ａを通じてｎ形高濃度領域３１，３２の高濃度領域に至る第２の電流経路は、いずれも第１の実施の形態に比べてコ字形状のトレンチ溝型絶縁領域を迂回する分だけより一層長くなる。このため、第１の電流経路の寄生抵抗と第２の電流経路の寄生抵抗との抵抗差を大きくすることができ、第１の電流経路の寄生抵抗を第２の電流経路の寄生抵抗よりも一層大きくすることができる。従って、保護ダイオード全体の抵抗成分を小さくしつつ、サージ電流の大部分を内側ｎ形高濃度埋込み領域５Ａを通る第２のダイオード３６を通じて流すことができる。この結果、ｐ形高濃度領域７とｎ形高濃度領域３１，３２との間隔を拡げることなく、半導体装置の損傷をより確実に防ぐことができ、高集積度を保持しつつ信頼性等の向上を図ることができる。
【００５１】
なお、前記第３の実施の形態ではトレンチ溝型絶縁領域３３，３４の両端はｐ形領域６の外周に沿って屈曲させたコ字形状に形成するものとしたが、図７に示す第１の変形例のようにｎ形高濃度領域３１，３２を取り囲むようにｎ形高濃度領域３１，３２の外周に沿って屈曲したコ字形状のトレンチ溝型絶縁領域３３′，３４′としてもよい。
【００５２】
また、前記第１の実施の形態ではトレンチ溝型絶縁領域９は直線状の形成するものとしたが、図８に示す第２の変形例のように両端が屈曲したコ字形状のトレンチ溝型絶縁領域９′としてもよい。また、ｎ形高濃度領域８はトレンチ溝型絶縁領域９′と離間している必要はなく、図８中に二点鎖線で示すようにトレンチ溝型絶縁領域９′に接触した状態でｎ形高濃度領域８′を設ける構成としてもよい。
【００５３】
また、前記各実施の形態ではｎ形高濃度領域８，３１，３２は半導体装置の入力端子に接続するものとしたが、半導体装置の出力端子に接続する構成としてもよい。この場合、出力端子に印加されるサージに対して同様な作用効果を得ることができる。
【００５４】
また、ｐ形高濃度領域７を入力端子または出力端子に接続し、ｎ形高濃度領域８，３１，３２を高電位端子に接続してもよい。この場合、半導体装置に印加されたサージを高電位となる電源側等にバイパスすることができると共に、前述した各実施の形態と同様の作用効果を得ることができる。
【００５５】
さらに、ｐ形高濃度領域７を低電位端子（低電位電源端子）に接続し、ｎ形高濃度領域８，３１，３２を高電位端子（高電位電源端子）に接続してもよい。この場合には、電源端子に印加されたサージをすることができると共に、前述した各実施の形態と同様の作用効果を得ることができる。
【００５６】
また、前記各実施の形態では、誘電体膜２の表面にｎ形高濃度埋込み領域５とｎ形領域３とを形成するものとしたが、誘電体膜２の表面にｐ形高濃度埋込み領域とｎ形領域とを形成する構成としてもよい。この場合、各実施の形態中に記載したｎ形とｐ形とを入れ替え、かつ低電位端子（低電位電源端子）と高電位端子（高電位電源端子）とを入れ替えれば、前述と同様の作用効果を得ることができる。
【００５７】
【発明の効果】
以上詳述した通り、請求項１の発明によれば、第１導電形の半導体領域と第２導電形の半導体領域との間には第１のダイオードを形成することができると共に、第１導電形の半導体領域と第２導電形の高濃度埋込み領域との間には第２のダイオードを形成することができる。また、第１導電形の半導体領域を第２導電形の高濃度埋込み領域に面接触状態で接して設けると共に、第１導電形の高濃度領域と第２導電形の高濃度領域との間にはトレンチ溝型絶縁領域を設けたから、第１導電形の半導体領域を第２導電形の高濃度埋込み領域にはブレークダウン電圧が低く、かつ寄生抵抗が小さい第２のダイオードを形成することができる。
また、第１のダイオードから第２導電形の半導体領域を通じて第２導電形の高濃度領域に至る第１の電流経路と、第２のダイオードから第２導電形の高濃度埋込み領域を通じて第２導電形の高濃度領域に至る第２の電流経路とは、いずれもトレンチ溝型絶縁領域を迂回するから、第１，第２の電流経路はいずれもトレンチ溝型絶縁領域を迂回する分だけ長くなる。また、第２導電形の高濃度埋込み領域は第２導電形の半導体領域よりも不純物濃度が高くなっているから、第１，第２の電流経路が長くなるほど第１の電流経路の寄生抵抗は第２の電流経路の寄生抵抗よりも顕著に大きくなる。
このため、正負いずれの過電圧サージが印加されるときであっても、サージ電流の大部分をブレークダウン電圧が低く、かつ寄生抵抗が小さい第２のダイオードに流すことができる。このとき、ダイオード電流がｐｎ接合の一部に集中することがないから、半導体装置の損傷を防ぐことができ、信頼性、耐久性を高めることができる。
また、トレンチ溝型絶縁領域が第１，第２のダイオードのｐｎ接合箇所に接触することがないから、ｐｎ接合がトレンチ溝型絶縁領域に接触したときにトレンチ溝型絶縁領域に沿って流れるリーク電流が発生することがない。このため、第１，第２のダイオードの整流特性等が劣化することがなく、高特性を維持することができる。
また、第１導電形の半導体領域と第２導電形の高濃度領域との間隔を狭くすることができるから、半導体装置の高集積度を維持できる。さらに、従来技術に比べて製造時間を短縮でき、生産性を向上できる等の種々の効果を奏する。
【００５８】
また、請求項２の発明は、第１導電形の高濃度領域主面上にパッド電極を設け、第１導電形の高濃度領域と該パッド電極とを接続したから、半導体装置の高集積度を保持できると共に、サージ電流を第１導電形の高濃度領域の全体に略均一に流すことができる。これにより、第１導電形の高濃度領域と第２導電形の高濃度埋込み領域との間に形成される第２のダイオードのｐｎ接合部分にも、電流密度がより均一な状態でサージ電流を流すことができ、第２のダイオードの耐圧を高め、信頼性、耐久性をさらに向上することができる。
【００５９】
さらに、請求項３の発明は、第２導電形の半導体領域主面には第１導電形の高濃度領域を挟んで一の第２導電形の高濃度領域と反対側に他の第２導電形の高濃度領域を設け、かつ第１導電形の高濃度領域と他の第２導電形の高濃度領域との間には他のトレンチ溝型絶縁領域を形成したから、第２導電形の高濃度領域全体の面積を増加させることができる。このため、保護ダイオード全体のインピーダンスを減少させることができるから、内部回路等に注入させるサージ電流を小さく抑制でき、半導体装置の損傷を防止できる。
【００６０】
また、第１導電形の高濃度領域と２つの第２導電形の高濃度領域との間にはトレンチ溝型絶縁領域をそれぞれ設けると共に、これら２つのトレンチ溝型絶縁領域はいずれもコ字形状をなして互いに離間して配置したから、保護ダイオード全体の抵抗成分を小さくしつつ、サージ電流の大部分を第１導電形の高濃度領域と第２導電形の高濃度埋込み領域との間に形成される第２のダイオードを通じて流すことができる。これにより、半導体装置の第１導電形の高濃度領域と第２導電形の高濃度領域との間隔を拡げることなく、半導体装置の損傷をより確実に防ぐことができ、高集積度を保持しつつ信頼性等の向上を図ることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態による半導体装置を示す平面図である。
【図２】図１中の矢示II−II方向からみた断面図である。
【図３】図１中の矢示 III−III 方向からみた断面図である。
【図４】第２の実施の形態による半導体装置を図３と同様位置からみた断面図である。
【図５】第３の実施の形態による半導体装置を示す平面図である。
【図６】図５中の矢示VI−VI方向からみた断面図である。
【図７】第１の変形例による半導体装置を示す平面図である。
【図８】第２の変形例による半導体装置を示す平面図である。
【符号の説明】
１シリコン支持基板（半導体支持基板）
２誘電体膜（誘電体）
３ｎ形領域（第２導電形の半導体領域）
３Ａ内側ｎ形領域
５ｎ形高濃度埋込み領域（第２導電形の高濃度埋込み領域）
５Ａ内側ｎ形高濃度埋込み領域
６ｐ形領域（第１導電形の半導体領域）
７ｐ形高濃度領域（第１導電形の高濃度領域）
８，８′ ｎ形高濃度領域（第２導電形の高濃度領域）
９，９′ トレンチ溝型絶縁領域
３１第１のｎ形高濃度領域（一の第２導電形の高濃度領域）
３２第２のｎ形高濃度領域（他の第２導電形の高濃度領域）
３３，３３′ 第１のトレンチ溝型絶縁領域（一のトレンチ溝型絶縁領域）
３４，３４′ 第２のトレンチ溝型絶縁領域（他のトレンチ溝型絶縁領域）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor region is formed on a surface (main surface) of a semiconductor support substrate via a dielectric.
[0002]
[Prior art]
In general, a semiconductor device is known in which a silicon region made of p-type silicon or n-type silicon is formed on a silicon substrate serving as a semiconductor support substrate via a dielectric such as a silicon oxide film (for example, a special device). (Kaihei 7-31424).
[0003]
In such a conventional semiconductor device, a diode capable of flowing a large current is formed in order to prevent the MOS transistor from being destroyed by an excessive current due to static electricity or a surge voltage. This diode employs a planar structure in which an anode side high concentration diffusion region and a cathode side high concentration diffusion region are formed on the surface of the silicon region. Further, the cathode side high concentration diffusion region of the diode is disposed so as to surround the outer peripheral side of the anode side high concentration diffusion region, for example, and a dielectric is interposed between the anode side high concentration diffusion region and the cathode side high concentration diffusion region. The anode side high concentration diffusion region and the cathode side high concentration diffusion region are electrically connected through polycrystalline silicon provided on the bottom side thereof.
[0004]
[Problems to be solved by the invention]
By the way, the above-described conventional semiconductor device employs a planar structure in which both the anode side high concentration diffusion region and the cathode side high concentration diffusion region of the diode are formed on the surface of the silicon region. For this reason, when a surge is applied, the surge current flows through the shortest path where the resistance is minimized, so that the surge current is concentrated on the outer peripheral end side of the anode-side high-concentration diffusion region forming the end of the pn junction. As a result, a surge current, which is a large current, flows in a concentrated manner at the end of a small pn junction, which causes a problem that the diode is easily damaged.
[0005]
In a planar structure diode, it is necessary to increase the resistance component by increasing the distance between the anode and the cathode in order to increase the breakdown resistance. However, when the magnitude of the surge current is limited in this way, the surge current may flow into the internal circuit and damage the internal circuit.
[0006]
Furthermore, in the semiconductor device according to the prior art, since a dielectric is provided between the anode-side high concentration diffusion region and the cathode-side high concentration diffusion region, it is necessary to add a process for forming the dielectric, and the manufacturing time There is also a problem that becomes longer.
[0007]
The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a semiconductor device capable of preventing concentration of surge current and improving durability and reliability.
[0008]
[Means for Solving the Problems]
  In order to solve the above-described problems, a semiconductor device according to the invention of claim 1 forms a semiconductor region of the second conductivity type on the main surface of the semiconductor support substrate via a dielectric, and the semiconductor region of the second conductivity type. A second conductivity type high concentration buried region is formed on the bottom surface of the first conductivity type semiconductor region, and the first conductivity type semiconductor region is formed on the main surface of the second conductivity type semiconductor region.In surface contactProviding a high concentration region of the first conductivity type on the main surface of the semiconductor region of the first conductivity type, and providing a high concentration region of the second conductivity type on the main surface of the semiconductor region of the second conductivity type;A first diode is formed between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, and the semiconductor region of the first conductivity type and the high concentration buried region of the second conductivity type A second diode is formed between them,And located between the high concentration region of the first conductivity type and the high concentration region of the second conductivity type.,On the main surface of the semiconductor region of the second conductivity typeProvided,In contact with the dielectricAt the same time, it does not contact the pn junction of the first and second diodes.A trench groove type insulating region is formed, and either one of the first conductivity type high concentration region and the second conductivity type high concentration region is defined as an input terminal, an output terminal, a high potential terminal, or a low potential terminal. Connect to one of the terminals and connect the other to the remaining terminalThe first current path from the first diode to the second conductivity type high concentration region through the second conductivity type semiconductor region, and the second diode through the second conductivity type high concentration buried region. Both of the second current paths reaching the high conductivity region of two conductivity types bypass the trench groove type insulating region.It is configured to do.
[0009]
With this configuration, the first diode can be formed between the first conductivity type semiconductor region and the second conductivity type semiconductor region, and the first conductivity type semiconductor region and the second conductivity type can be formed. A second diode can be formed between the conductive type high-concentration buried region, and these two diodes can act as a protective diode. At this time, the second conductivity type high concentration buried region has a higher impurity concentration than the second conductivity type semiconductor region, and the first conductivity type semiconductor region and the second conductivity type high concentration buried region have a small curvature. Since the contact state can be obtained, the breakdown voltage of the second diode can be made lower than that of the first diode.
[0010]
In addition, since the trench groove type insulating region is formed between the semiconductor region of the first conductivity type and the high concentration region of the second conductivity type, the current flowing between them flows around the trench groove type insulating region. . Therefore, the first current path from the first diode through the second conductivity type semiconductor region to the second conductivity type high concentration region, and the second diode from the second diode through the second conductivity type high concentration buried region. Each of the second current paths leading to the high-concentration region of the shape is longer by an amount that bypasses the trench groove type insulating region. In addition, since the second conductivity type high-concentration buried region has a higher impurity concentration than the second conductivity type semiconductor region, the parasitic resistance of the first current path becomes longer as the first and second current paths become longer. This is significantly larger than the parasitic resistance of the second current path.
[0011]
  As a result, even when a positive or negative overvoltage surge is applied, most of the surge current can be passed through the second diode having a low breakdown voltage and a low parasitic resistance. Since the second diode can be formed by bringing the first conductivity type semiconductor region and the second conductivity type high-concentration buried region into surface contact, it is possible to prevent the surge current from concentrating on a minute end. it can.
  Further, the trench groove type insulating region does not contact the pn junction portion of the first and second diodes. For this reason, when the pn junction comes into contact with the trench groove type insulating region, a leak current flowing along the trench groove type insulating region does not occur, so that the rectifying characteristics of the first and second diodes are deteriorated. And high characteristics can be maintained.
[0012]
According to a second aspect of the present invention, a pad electrode is provided on the main surface of the high-concentration region of the first conductivity type, and the high-concentration region of the first conductivity type is connected to the pad electrode.
[0013]
  As a result, under the pad electrodeSecondSince a diode can be formed, a high degree of integration can be maintained without impairing the degree of integration of the semiconductor device. Further, since the surge current flows between the pad electrode and the first conductivity type high concentration region that are in surface contact with each other, the surge current can be made to flow substantially uniformly throughout the high concentration region of the first conductivity type. As a result, it is formed between the high concentration region of the first conductivity type and the high concentration buried region of the second conductivity type.SecondA surge current can also flow in the pn junction part of the diode with a more uniform current density,SecondThe withstand capacity of the diode can be increased.
[0014]
  Furthermore, the invention of claim 3 is located on the main surface of the semiconductor region of the second conductivity type located on the opposite side of the high concentration region of the second conductivity type with the high concentration region of the first conductivity type interposed therebetween. Is provided with a high concentration region of another second conductivity type and is located between the high concentration region of the first conductivity type and the high concentration region of the other second conductivity type.,On the main surface of the semiconductor region of the second conductivity typeProvided,In contact with the dielectricIn addition, another trench groove type insulating region is formed so as not to contact the pn junctions of the first and second diodes, and the one trench groove type insulating region and the other trench groove type insulating region are bothMake a U shapeSpaced apart from each other,The other second conductivity type high concentration region is connected to the one second conductivity type high concentration region.
[0015]
As a result, two high-concentration regions of the second conductivity type are provided, so that the entire area of the high-concentration region of the second conductivity type is made larger than when a single high-concentration region of the second conductivity type is provided. Can do. Therefore, the first diode formed between the first conductivity type semiconductor region and the second conductivity type semiconductor region, and between the first conductivity type semiconductor region and the second conductivity type high concentration buried region. Each of the second diodes formed in the structure has a small resistance component. Accordingly, the impedance of the entire first and second diodes is reduced, and the potential increase such as the input terminal voltage at the time of applying the surge can be suppressed more reliably, and the surge current injected into the internal circuit can be suppressed. .
[0016]
  Further, between the high concentration region of the first conductivity type and the two high concentration regions of the second conductivity type.HWrench groove type insulation area is providedIn addition, these two trench groove type insulating regions are both U-shaped and spaced apart from each other.Therefore, the first current path from the high concentration region of the first conductivity type to the high concentration region of the second conductivity type through the semiconductor region of the second conductivity type, and the high concentration of the second conductivity type from the high concentration region of the first conductivity type. The second current path that reaches the high concentration region of the second conductivity type through the concentration buried region is longer than the second current path because it bypasses the U-shaped trench groove type insulating region. For this reason, the resistance difference between the parasitic resistance of the first current path and the parasitic resistance of the second current path can be increased, and the parasitic resistance of the first current path can be made larger than the parasitic resistance of the second current path. It can be made even larger. Therefore, most of the surge current is formed between the high concentration region of the first conductivity type and the high concentration buried region of the second conductivity type.SecondSince the current flows through the diode, damage to the semiconductor device can be prevented.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS.
[0018]
1 to 3 show a first embodiment of the present invention. In the figure, reference numeral 1 denotes a silicon support substrate made of, for example, a silicon material, and a silicon oxide film or the like is formed on the surface of the silicon support substrate 1. The dielectric film 2 is provided, and an n-type region 3 made of n-type silicon is formed through the dielectric film 2. As a result, the silicon support substrate 1, the dielectric film 2, and the n-type region 3 form an SOI (Silicon On Insulator) structure, and the n-type region 3 has a low concentration of impurities such as arsenic (for example, single crystal silicon material) 10¹⁵-10¹⁶cm^-3Degree).
[0019]
Reference numeral 4 denotes a frame-shaped trench groove type insulating region provided in the n-type region 3, and the frame-shaped trench groove type insulating region 4 is formed in a substantially rectangular frame shape, and its bottom reaches the dielectric film 2. . The frame-shaped trench-type insulating region 4 divides the n-type region 3 into an inner n-type region 3A located inside and an outer n-type region 3B located outside, and separates them into an insulating state. . In addition, a protective diode including a p-type region 6 and the like to be described later is formed in the inner n-type region 3A, and an internal circuit (not shown) for performing various processes is formed in the outer n-type region 3B. ing.
[0020]
Reference numeral 5 denotes an n-type high-concentration buried region provided on the entire bottom surface of the n-type region 3, and the n-type high-concentration buried region 5 is disposed between the n-type region 3 and the dielectric film 2 and is made of arsenic or the like. The impurity of a high concentration (for example, 10¹⁸-10¹⁹cm^-3Degree). Further, the n-type high concentration buried region 5 is also divided into the frame-like trench groove type insulating region 4, and the inner n-type high concentration buried region 5A located inside the frame-like trench groove type insulating region 4 and the outer n located outside. It is isolated from the high concentration buried region 5B.
[0021]
Reference numeral 6 denotes a p-type region provided on the surface of the inner n-type region 3A. The p-type region 6 has a substantially square shape and is arranged at the center of the inner n-type region 3A. It is in surface contact with the embedded region 5A. Further, the p-type region 6 has a low concentration of impurities such as boron (for example, 10%) from the surface side of the inner n-type region 3A.¹⁵-10¹⁶cm^-3It is formed by diffusing to the extent.
[0022]
Reference numeral 7 denotes a p-type high concentration region provided on the surface of the p-type region 6, and the p-type high concentration region 7 is arranged in the center of the p-type region 6 in a substantially square shape. The p-type high concentration region 7 is formed by diffusing impurities such as boron in the p-type region 6 at a high concentration. The p-type high concentration region 7 is connected to a low potential terminal such as a ground terminal.
[0023]
Reference numeral 8 denotes an n-type high concentration region provided on the surface of the inner n-type region 3A, and the n-type high concentration region 8 is located on the substantially central side with respect to one side of the p-type region 6 having a substantially square shape. The p-type region 6 is disposed between the p-type region 6 and the frame-shaped trench groove type insulating region 4 so as to be separated from the p-type region 6. The n-type high concentration region 8 is formed by diffusing impurities such as arsenic at a high concentration in the inner n-type region 3A. The n-type high concentration region 8 is connected to, for example, an input terminal as a terminal different from the low potential terminal.
[0024]
9 is a trench groove type insulating region located between the p type region 6 and the n type high concentration region 8 and provided on the surface of the inner n type region 3A. The trench groove type insulating region 9 is a p type region. 6 is formed in a straight line extending substantially parallel to one side, and its length dimension is longer than one side of the p-type region 6. Further, although the trench groove type insulating region 9 is in contact with the dielectric film 2 over its entire length, both ends extending linearly do not come into contact with the frame shape trench groove type insulating region 4, and the frame shape trench groove type insulating region 9. A gap is formed between the region 4 and the region 4.
[0025]
The semiconductor device according to the present embodiment has the above-described configuration, and the operation thereof will be described next.
[0026]
First, since the p-type region 6 is provided on the center side of the inner n-type region 3A, a first diode 10 having a pn junction is formed on the outer peripheral side thereof. In addition, since the bottom surface of the p-type region 6 is in contact with the inner n-type high concentration buried region 5A over almost the entire surface, the second diode 11 by the pn junction is also formed on the bottom surface side of the p-type region 6. Yes. For this reason, these diodes 10 and 11 act as protective diodes for the semiconductor device.
[0027]
Here, the impurity concentration of the inner n-type high concentration buried region 5A is set higher than that of the inner n-type region 3A. For this reason, the breakdown voltage of the second diode 11 is set lower than that of the first diode 10.
[0028]
For the following reason, the resistance component of the second diode 11 is smaller than the resistance component of the first diode 10. That is, between the p-type region 6 and the n-type high concentration region 8, the first current path passing through the inner n-type region 3 </ b> A from the pn junction to the cathode side of the first diode 10 and the second diode 10. A second current path is formed on the cathode side from the pn junction through the inner n-type high concentration buried region 5A. Here, since the trench groove type insulating region 9 is formed between the p-type region 6 and the n-type high concentration region 8, the current flowing between them bypasses the trench groove type insulating region 9, and the trench It flows through both end sides in the length direction of the groove type insulating region 9. For this reason, the first and second current paths become longer by an amount corresponding to the length dimension of the trench groove type insulating region 9 than when the trench groove type insulating region 9 is not provided. The impurity concentration of the inner n-type high concentration buried region 5A is 10¹⁸-10¹⁹cm^-310 which is the impurity concentration of the inner n-type region 3A¹⁵-10¹⁶cm^-3Therefore, the parasitic resistance of the second current path (cathode side of the second diode 11) is compared with the parasitic resistance of the first current path (cathode side of the first diode 10). 10^-3Doubled. For this reason, as the first and second current paths become longer, the parasitic resistance component of the second diode 11 becomes significantly smaller than the parasitic resistance component of the first diode 10.
[0029]
As a result, when a positive overvoltage surge is applied to the input terminal, most of the surge current flows through the second diode 11 having a low breakdown voltage and a low parasitic resistance. That is, the second diode 11 breaks down before the first diode 10 when the surge voltage rises, and most of the current flows through the second diode 11 having a small parasitic resistance thereafter.
[0030]
Further, since the pn junction of the second diode 11 is formed between the p-type region 6 and the inner n-type high concentration buried region 5A, the pn junction of the diode 11 can be regarded as a planar junction. Further, the resistance of the inner n-type high concentration buried region 5A has a small value. For this reason, the current flowing through the diode 11 (diode current) flows approximately uniformly and has a substantially uniform current density over the entire pn junction. Therefore, the diode current is not concentrated on a part of the pn junction, and the diode can be prevented from being damaged.
[0031]
Furthermore, since the parasitic resistance component of the diode 11 itself is small, an increase in input terminal voltage due to a surge can be suppressed, and a surge current can be prevented from flowing into an internal circuit connected to the input terminal. For this reason, damage to the internal circuit can also be prevented.
[0032]
Also, most of the surge current can flow from the diode 11 through the inner n-type high concentration buried region 5A, so that an increase in surge current can be suppressed, and the p-type region 6 and the n-type high concentration region 8 It is not necessary to increase the breakdown tolerance of the diode by increasing the interval between them. For this reason, the high degree of integration can be maintained without impairing the degree of integration of the semiconductor device.
[0033]
Further, since the trench groove type insulating region 9 is configured to be in contact with the dielectric film 2 similarly to the frame-shaped trench groove type insulating region 4, the trench groove type insulating region 9 is processed simultaneously with the frame-shaped trench groove type insulating region 4. Can be formed. For this reason, it is not necessary to provide a separate process for processing the trench groove type insulating region 9 when manufacturing the semiconductor device, so that the manufacturing time can be shortened compared with the conventional technique that requires an additional processing process, Can be improved.
[0034]
Further, the trench groove type insulating region 9 does not contact the pn junctions of the first and second diodes 10 and 11. For this reason, when the pn junction comes into contact with the trench groove type insulating region 9, there is no leakage current flowing along the trench groove type insulating region 9, so that the rectification characteristics of the diodes 10 and 11 may deteriorate. And high characteristics can be maintained.
[0035]
On the other hand, when a negative overvoltage surge is applied to the input terminal, the first and second diodes 10 and 11 are forward biased. At this time, since the resistance component of the second diode 11 is significantly smaller than that of the first diode 10, most of the surge current flows through the diode 11 as in the case where a positive overvoltage surge is applied. . Further, the diode current flowing through the diode 11 flows approximately uniformly and has a substantially uniform current density over the entire pn junction, so that concentration of the diode current can be prevented. In this way, since there is no difference from the case where a positive overvoltage surge is applied except in the direction in which the surge current flows, the same effect as described above can be obtained even when a negative overvoltage surge is applied. it can.
[0036]
Thus, in the present embodiment, the p-type region 6 is provided in surface contact with the inner n-type high concentration buried region 5A, and the p-type region 6 (p-type high concentration region 7) and the n-type high concentration region 8 are provided. Since the trench groove type insulating region 9 is provided between them, the second diode having a low breakdown voltage and a small parasitic resistance is obtained even when a positive or negative overvoltage surge is applied. 11 can flow. At this time, since the diode current does not concentrate on a part of the pn junction, damage to the semiconductor device can be prevented, and reliability and durability can be improved. Further, since the distance between the p-type region 6 and the n-type high concentration region 8 can be reduced, the high degree of integration of the semiconductor device can be maintained. Furthermore, various effects such as a reduction in manufacturing time and an improvement in productivity can be achieved compared to the prior art.
[0037]
Next, FIG. 4 shows a second embodiment of the present invention. The feature of this embodiment is that a pad electrode is provided on the surface of the p-type high concentration region, and the p-type high concentration region, the pad electrode, Is connected. In the present embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.
[0038]
Reference numeral 21 denotes an oxide film provided on the surface of the n-type region 3. The oxide film 21 forms a field oxide film, and the surface side of the p-type high concentration region 7 is opened.
[0039]
Reference numeral 22 denotes a pad electrode provided on the surface of the p-type high concentration region 7. The pad electrode is made of a conductive metal material and is electrically connected to the p-type high concentration region 7 and connected to a low voltage terminal. Has been.
[0040]
Thus, the present embodiment can provide the same operational effects as those of the first embodiment. However, in this embodiment, since the diode 11 can be formed immediately below the pad electrode 22, the integration degree of the semiconductor device is not impaired as compared with the case where the pad electrode 22 is provided in another part. The degree of integration can be maintained.
[0041]
Further, since the surge current flows uniformly downward from the pad electrode 22 (thickness direction of the n-type region 3), the current inside the p-type region 6 is also uniformly distributed, and the current in the pn junction portion of the diode 11 The density can be made even more uniform.
[0042]
However, when a large current such as a surge current flows, the resistance of the metal wiring region such as the pad electrode 22 also greatly affects. Here, when the pad electrode 22 is provided at a position other than on the diode 11, the surge current is injected into the p-type high concentration region 7 through the wiring region on the oxide film 21. At this time, since the potential distribution is generated inside the wiring region due to the resistance in the wiring region, the surge current flows more frequently from the wiring region into the end portion (outer peripheral portion) of the p-type high concentration region 7 as the shortest path. For this reason, it is difficult to make the current density flowing through the pn junction of the diode 11 completely uniform.
[0043]
On the other hand, in the present embodiment, the current density at the pn junction portion of the diode 11 can be made even more complete, so that the diode can be applied even when a positive or negative overvoltage surge is applied. 11 or the like can be hardly generated, the breakdown voltage of the diode 11 can be increased, and the reliability and durability can be further improved.
[0044]
Next, FIGS. 5 and 6 show a third embodiment of the present invention. The feature of this embodiment is that two n-type high concentrations are sandwiched between a p-type high concentration region on the surface of the n-type region. In addition to providing a region, a U-shaped trench groove type insulating region is provided between the p-type high concentration region and each n-type high concentration region. In the present embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.
[0045]
Reference numeral 31 denotes a first n-type high concentration region provided on the surface of the inner n-type region 3A. The n-type high concentration region 31 is formed on the inner n-type similarly to the n-type high concentration region 8 according to the first embodiment. The region 3A is formed by diffusing impurities such as arsenic at a high concentration. The n-type high-concentration region 31 is located substantially on the center side with respect to one side of the p-type region 6 having a substantially rectangular shape, and is separated from the p-type region 6 and frame-shaped trench groove type insulation. It is arranged between the region 4. The n-type high concentration region 31 is connected to, for example, an input terminal as a terminal different from the low potential terminal.
[0046]
32 is a second n-type high-concentration region provided on the surface of the inner n-type region 3A. The n-type high-concentration region 32 is formed in the inner n-type region 3A by arsenic or the like in the same manner as the n-type high-concentration region 8. It is formed by diffusing impurities at a high concentration. The n-type high concentration region 32 is located on the opposite side of the n-type high concentration region 8 with the p-type high concentration region 7 (p-type region 6) interposed therebetween, and is separated from the p-type region 6 and is a p-type region. 6 and the frame-shaped trench trench insulating region 4. The n-type high concentration region 32 is connected to the n-type high concentration region 31 by wiring or the like as shown by a one-dot chain line in FIG.
[0047]
Reference numeral 33 denotes a first trench groove type insulating region located between the p type region 6 and the first n type high concentration region 31 and provided on the surface of the inner n type region 3A. 33 extends in a straight line substantially parallel to one side of the p-type region 6 and is formed in a U-shape in which both ends are bent toward the p-type region 6. Thereby, the trench groove type insulating region 33 extends along the outer periphery of the p-type region 6 and partially surrounds the p-type region 6. Further, the trench groove type insulating region 33 has a bottom portion that is in contact with the dielectric film 2 over its entire length, but both ends thereof are not in contact with the frame shape trench groove type insulating region 4. A gap is formed between the two.
[0048]
Reference numeral 34 denotes a second trench groove type insulating region located between the p type region 6 and the second n type high concentration region 32 and provided on the surface of the inner n type region 3A. 34 is disposed at a position opposite to the trench groove type insulating region 33 across the p-type region 6, and is formed in a U-shape in which both ends are bent toward the p-type region 6. Thereby, the trench groove type insulating region 34 extends along the outer periphery of the p-type region 6 and partially surrounds the p-type region 6. Further, the trench groove type insulating region 34 is in contact with the dielectric film 2 over its entire length, but both ends thereof are not in contact with the frame-like trench groove type insulating region 4 and the trench groove type insulating region 33, A gap is formed between the trench trench insulating region 4 and the trench trench insulating region 33.
[0049]
Thus, the present embodiment can provide the same operational effects as those of the first embodiment. However, in the present embodiment, since the two n-type high concentration regions 31 and 32 are provided on the surface of the inner n-type region 3A with the p-type high concentration region 7 interposed therebetween, the single n-type region 3A is provided as in the first embodiment. Compared with the case where one n-type high concentration region 8 is provided, the entire area of the n-type high concentration regions 31 and 32 can be increased. Therefore, the first diode 35 formed between the p-type region 6 and the inner n-type region 3A, and the second diode formed between the p-type region 6 and the inner n-type heavily doped region 5A. In each case, the resistance component is small. Accordingly, the impedance of the entire first and second diodes 35 and 36 is reduced, and an increase in the potential of the input terminal voltage when a surge is applied can be more reliably suppressed, so that the surge current injected into the internal circuit can be further reduced. Therefore, damage to the semiconductor device can be prevented, and reliability and the like can be improved.
[0050]
Further, since the trench groove type insulating regions 33 and 34 are formed in a U-shape with both ends bent, the first current from the p-type high concentration region 7 to the n-type high concentration regions 31 and 32 through the inner n-type region 3A. The second current path from the p-type high-concentration region 7 to the high-concentration regions of the n-type high-concentration regions 31 and 32 through the inner n-type high-concentration buried region 5A is higher than that of the first embodiment. The length is further increased by detouring the U-shaped trench groove type insulating region. For this reason, the resistance difference between the parasitic resistance of the first current path and the parasitic resistance of the second current path can be increased, and the parasitic resistance of the first current path can be made larger than the parasitic resistance of the second current path. It can be made even larger. Therefore, most of the surge current can be passed through the second diode 36 passing through the inner n-type high concentration buried region 5A while reducing the resistance component of the entire protection diode. As a result, the semiconductor device can be more reliably prevented from being damaged without increasing the distance between the p-type high-concentration region 7 and the n-type high-concentration regions 31 and 32, and the reliability and the like can be maintained while maintaining a high degree of integration. Improvements can be made.
[0051]
In the third embodiment, both ends of the trench-groove insulating regions 33 and 34 are formed in a U-shape bent along the outer periphery of the p-type region 6, but the first shape shown in FIG. As in the modified example, U-shaped trench groove type insulating regions 33 ′ and 34 ′ bent along the outer periphery of the n-type high concentration regions 31 and 32 so as to surround the n-type high concentration regions 31 and 32 may be used. .
[0052]
In the first embodiment, the trench groove type insulating region 9 is formed in a straight line. However, a U-shaped trench groove type in which both ends are bent as in the second modification shown in FIG. The insulating region 9 ′ may be used. Further, the n-type high concentration region 8 does not need to be separated from the trench groove type insulating region 9 ', and is in contact with the trench groove type insulating region 9' as shown by a two-dot chain line in FIG. It is good also as a structure which provides high concentration area | region 8 '.
[0053]
In each of the above embodiments, the n-type high concentration regions 8, 31, and 32 are connected to the input terminal of the semiconductor device, but may be configured to be connected to the output terminal of the semiconductor device. In this case, a similar effect can be obtained for the surge applied to the output terminal.
[0054]
Further, the p-type high concentration region 7 may be connected to the input terminal or the output terminal, and the n-type high concentration regions 8, 31, 32 may be connected to the high potential terminal. In this case, the surge applied to the semiconductor device can be bypassed to the power supply side or the like having a high potential, and the same effects as those of the above-described embodiments can be obtained.
[0055]
Furthermore, the p-type high concentration region 7 may be connected to a low potential terminal (low potential power supply terminal), and the n type high concentration regions 8, 31, 32 may be connected to a high potential terminal (high potential power supply terminal). In this case, it is possible to perform a surge applied to the power supply terminal and obtain the same operational effects as those of the above-described embodiments.
[0056]
In each of the above embodiments, the n-type high concentration buried region 5 and the n-type region 3 are formed on the surface of the dielectric film 2, but the p-type high concentration buried region is formed on the surface of the dielectric film 2. And an n-type region may be formed. In this case, if the n-type and the p-type described in each embodiment are interchanged, and the low-potential terminal (low-potential power supply terminal) and the high-potential terminal (high-potential power supply terminal) are interchanged, the same action as described above. An effect can be obtained.
[0057]
【The invention's effect】
  As detailed above, according to the invention of claim 1,A first diode can be formed between the first conductivity type semiconductor region and the second conductivity type semiconductor region, and the first conductivity type semiconductor region and the second conductivity type high concentration buried region; A second diode can be formed in between. Also,The semiconductor region of the first conductivity type is changed to a high concentration buried region of the second conductivity type.In surface contactSince the trench groove type insulating region is provided between the high-concentration region of the first conductivity type and the high-concentration region of the second conductivity type. The concentration buried region has low breakdown voltage and low parasitic resistanceSecondDiodes can be formed.
  Also, a first current path from the first diode through the second conductivity type semiconductor region to the second conductivity type high concentration region, and a second current from the second diode through the second conductivity type high concentration buried region. Since the second current path reaching the high concentration region of the shape bypasses the trench groove type insulating region, both the first and second current paths become longer by the amount of bypassing the trench groove type insulating region. . In addition, since the second conductivity type high-concentration buried region has a higher impurity concentration than the second conductivity type semiconductor region, the parasitic resistance of the first current path becomes longer as the first and second current paths become longer. This is significantly larger than the parasitic resistance of the second current path.
  ThisTherefore, even if a positive or negative overvoltage surge is applied, most of the surge currentA second voltage with low breakdown voltage and low parasitic resistanceCan flow through a diode. At this time, since the diode current does not concentrate on a part of the pn junction, damage to the semiconductor device can be prevented, and reliability and durability can be improved..
  In addition, since the trench groove type insulating region does not contact the pn junction portion of the first and second diodes, a leak that flows along the trench groove type insulating region when the pn junction contacts the trench groove type insulating region. No current is generated. For this reason, the rectifying characteristics and the like of the first and second diodes are not deteriorated, and high characteristics can be maintained.
  MaIn addition, since the distance between the semiconductor region of the first conductivity type and the high concentration region of the second conductivity type can be reduced, the high degree of integration of the semiconductor device can be maintained. Furthermore, various effects such as a reduction in manufacturing time and an improvement in productivity can be achieved compared to the prior art.
[0058]
  According to the second aspect of the present invention, since the pad electrode is provided on the main surface of the high-concentration region of the first conductivity type, and the high-concentration region of the first conductivity type is connected to the pad electrode, the degree of integration of the semiconductor device is high. And a surge current can be made to flow substantially uniformly throughout the high concentration region of the first conductivity type. As a result, a high concentration region of the first conductivity type and a high concentration buried region of the second conductivity type are formed.SecondA surge current can also flow in the pn junction part of the diode with a more uniform current density,SecondThe breakdown voltage of the diode can be increased, and the reliability and durability can be further improved.
[0059]
  Furthermore, the invention of claim 3 is characterized in that the second conductivity type semiconductor region main surface has the first conductivity type high concentration region sandwiched between one second conductivity type high concentration region and the other second conductivity type. And a high concentration region of the first conductivity typeotherBetween the high concentration region of the second conductivity typeotherTrench trench insulation regionShapeAs a result, the entire area of the second conductivity type high concentration region can be increased. For this reason, since the impedance of the entire protective diode can be reduced, the surge current injected into the internal circuit or the like can be suppressed to a small level, and damage to the semiconductor device can be prevented.
[0060]
  Further, between the high concentration region of the first conductivity type and the two high concentration regions of the second conductivity type.HWrench groove type insulation area is providedIn addition, these two trench groove type insulating regions are both U-shaped and spaced apart from each other.Therefore, most of the surge current is formed between the high concentration region of the first conductivity type and the high concentration buried region of the second conductivity type while reducing the resistance component of the entire protection diode.SecondIt can flow through a diode. As a result, the semiconductor device can be more reliably prevented from being damaged without increasing the distance between the first conductivity type high concentration region and the second conductivity type high concentration region of the semiconductor device, and high integration can be maintained. In addition, reliability and the like can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
2 is a cross-sectional view seen from the direction of arrows II-II in FIG.
3 is a cross-sectional view taken from the direction of arrows III-III in FIG.
4 is a cross-sectional view of the semiconductor device according to the second embodiment as viewed from the same position as in FIG. 3;
FIG. 5 is a plan view showing a semiconductor device according to a third embodiment.
6 is a cross-sectional view seen from the direction of arrows VI-VI in FIG.
FIG. 7 is a plan view showing a semiconductor device according to a first modification.
FIG. 8 is a plan view showing a semiconductor device according to a second modification.
[Explanation of symbols]
1 Silicon support substrate (semiconductor support substrate)
2 Dielectric film (dielectric)
3 n-type region (second conductivity type semiconductor region)
3A Inside n-type region
5 n-type high concentration buried region (second conductivity type high concentration buried region)
5A Inner n-type high concentration buried region
6 p-type region (first conductivity type semiconductor region)
7 p-type high concentration region (high concentration region of the first conductivity type)
8,8 'n-type high concentration region (second conductivity type high concentration region)
9, 9 'Trench trench insulation region
31 1st n-type high concentration area | region (High concentration area | region of one 2nd conductivity type)
32 Second n-type high concentration region (high concentration region of other second conductivity type)
33, 33 'first trench groove type insulating region (one trench groove type insulating region)
34, 34 'second trench groove type insulating region (other trench groove type insulating region)

Claims

Forming a second conductivity type semiconductor region on the main surface of the semiconductor support substrate via a dielectric, and forming a second conductivity type high-concentration buried region on the bottom surface of the second conductivity type semiconductor region;
A first conductivity type semiconductor region is provided on the main surface of the second conductivity type semiconductor region so as to be in surface contact with the second conductivity type high concentration buried region;
Providing a first conductivity type high concentration region on the first conductivity type semiconductor region main surface, and providing a second conductivity type high concentration region on the second conductivity type semiconductor region main surface;
A first diode is formed between the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, and the semiconductor region of the first conductivity type and the high concentration buried region of the second conductivity type A second diode is formed between them,
And located between the first conductivity type high concentration region and a high concentration region of the second conductivity type, provided in the semiconductor region the main surface of the second conductivity type, the contact with the dielectric, the first, Forming a trench groove type insulating region so as not to contact the pn junction of the second diode ;
One of the high-concentration region of the first conductivity type and the high-concentration region of the second conductivity type is connected to any one of the input terminal, the output terminal, the high potential terminal, and the low potential terminal, and the other Connect to one of the remaining terminals ,
A first current path from the first diode through a second conductivity type semiconductor region to a second conductivity type high concentration region; and a second current conductivity from the second diode through a second conductivity type high concentration buried region. The second current path reaching the high concentration region of the semiconductor device is a semiconductor device configured to bypass the trench groove type insulating region .

2. The semiconductor device according to claim 1, wherein a pad electrode is provided on a main surface of the first conductivity type high concentration region, and the first conductivity type high concentration region is connected to the pad electrode.

The second conductivity type semiconductor region main surface is located on the opposite side of the one second conductivity type high concentration region across the first conductivity type high concentration region, and the second conductivity type has a high concentration region. A concentration area,
And located between the high-concentration region and another second conductive high-concentration region in the form of a first conductivity type, provided in the semiconductor region the main surface of the second conductivity type, the contact with the dielectric, the first 1. Form another trench groove type insulating region so as not to contact the pn junction of the second diode,
The one trench groove type insulating region and the other trench groove type insulating region are both arranged in a U shape and spaced apart from each other,
3. The semiconductor device according to claim 1, wherein the other second conductivity type high concentration region is connected to the one second conductivity type high concentration region.