JP2522350B2 - Semiconductor integrated circuit protection device - Google Patents
Semiconductor integrated circuit protection deviceInfo
- Publication number
- JP2522350B2 JP2522350B2 JP63114585A JP11458588A JP2522350B2 JP 2522350 B2 JP2522350 B2 JP 2522350B2 JP 63114585 A JP63114585 A JP 63114585A JP 11458588 A JP11458588 A JP 11458588A JP 2522350 B2 JP2522350 B2 JP 2522350B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- insulating film
- type
- integrated circuit
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 30
- 230000001681 protective effect Effects 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 18
- 230000015556 catabolic process Effects 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の保護装置に関し、特に静電
破壊耐圧の向上を図った保護抵抗の構成に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit protection device, and more particularly to a structure of a protection resistor for improving electrostatic breakdown voltage.
〔従来の技術〕 従来、この種の保護抵抗は、第６図のように、例えば
Ｎ型半導体基板１の表面の厚いフィールド絶縁膜３の上
に、ポリシリコン等からなる抵抗体５を形成し、これを
被覆する層間絶縁膜４のコンタクトを通してその一端を
集積回路の端子に繋がる配線6aに接続し、他端を集積回
路の保護ダイオード及び内部回路に繋がる配線6bに接続
している。[Prior Art] Conventionally, as shown in FIG. 6, this type of protective resistor has a resistor 5 made of polysilicon or the like formed on a thick field insulating film 3 on the surface of an N-type semiconductor substrate 1, for example. , One end thereof is connected to the wiring 6a connected to the terminal of the integrated circuit through the contact of the interlayer insulating film 4 covering the same, and the other end is connected to the wiring 6b connected to the protection diode and the internal circuit of the integrated circuit.
この構成では、端子に静電気が印加されると、その電
荷は配線6aから抵抗体５に至り、この抵抗体５で減衰さ
れ、かつ配線6b及び保護ダイオード（図示せず）を経由
して基板１へと放電され、内部回路を保護することは言
うまでもない。In this configuration, when static electricity is applied to the terminal, the electric charge reaches the resistor 5 from the wiring 6a, is attenuated by the resistor 5, and passes through the wiring 6b and the protection diode (not shown) to the substrate 1 It goes without saying that the internal circuit is protected by being discharged to.
上述した従来の保護抵抗は、電流モードによる熱的な
破壊に対しては設計上その抵抗値，面積等により対応で
きるが、電圧（電界）モードによる破壊は抵抗下のフィ
ールド絶縁膜３の破壊強度により決定されるため（通常
350V〜600V）設計上対応ができないという問題がある。The conventional protection resistance described above can cope with thermal breakdown due to the current mode by designing its resistance value, area, etc., but breakdown due to the voltage (electric field) mode has a breakdown strength of the field insulating film 3 under the resistance. As determined by (usually
(350V to 600V) There is a problem that it cannot be designed.
即ち、第６図の例では、抵抗体５の下側はフィールド
絶縁膜３を介してＮ型基板１となっているため、正の電
荷が抵抗体５に印加されると表面は蓄積状態となり、加
わった電圧は全てフィールド絶縁膜３に印加される。そ
して、この高電圧の印加によってフィールド絶縁膜３が
絶縁破壊され、抵抗体５が基板１と短絡することにな
る。That is, in the example of FIG. 6, since the lower side of the resistor 5 is the N-type substrate 1 via the field insulating film 3, when the positive charge is applied to the resistor 5, the surface becomes the accumulation state. The applied voltage is all applied to the field insulating film 3. Then, the application of this high voltage causes dielectric breakdown of the field insulating film 3, and the resistor 5 is short-circuited with the substrate 1.
この絶縁破壊に対しては、フィールド絶縁膜３を厚く
形成すればよいが、これは素子の微細化と相反するた
め、近年の微細化を目的とする半導体集積回路には適用
することができない。For this dielectric breakdown, the field insulating film 3 may be formed thick, but this conflicts with the miniaturization of the element, and therefore cannot be applied to a semiconductor integrated circuit aiming at miniaturization in recent years.
本発明は絶縁破壊耐圧を向上させた半導体集積回路の
保護装置を提供することを目的としている。An object of the present invention is to provide a semiconductor integrated circuit protection device having an improved breakdown voltage.
本発明の半導体集積回路の保護装置は、一導電型の半
導体基板表面の絶縁膜上に、一端を集積回路の端子に接
続し、他端を内部回路に接続した保護抵抗を形成し、か
つこの保護抵抗の下側の基板の前記絶縁膜の直下に保護
抵抗の領域にわたって半導体基板と逆導電型の低濃度不
純物層を形成するとともに、この低濃度不純物層には保
護抵抗の端子側接点以外の部分を接続し、この保護抵抗
を通して前記低濃度不純物層に電位を供給するように構
成している。A protective device for a semiconductor integrated circuit according to the present invention forms a protective resistance having one end connected to a terminal of an integrated circuit and the other end connected to an internal circuit on an insulating film on the surface of a semiconductor substrate of one conductivity type, and A low-concentration impurity layer having a conductivity type opposite to that of the semiconductor substrate is formed immediately below the insulating film of the substrate on the lower side of the protective resistor over the region of the protective resistor. The portions are connected to each other, and a potential is supplied to the low-concentration impurity layer through the protective resistance.
上述した構成では、低濃度不純物層と基板との接合に
おける逆方向耐圧と直列抵抗で決定される電圧だけ保護
抵抗と基板との間の絶縁膜に印加される電界を緩和し、
絶縁膜の破壊電圧を向上させる。In the above configuration, the electric field applied to the insulating film between the protective resistance and the substrate is relaxed by a voltage determined by the reverse breakdown voltage and the series resistance at the junction between the low-concentration impurity layer and the substrate,
The breakdown voltage of the insulating film is improved.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１実施例の平面図であり、第２図
は第１図のＡ−Ａ線に沿う断面図である。FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA of FIG.
これらの図において、シリコン等のＰ型基板１の上に
は、通常5000〜8000Åの熱酸化膜からなるフィールド絶
縁膜３を形成している。このフィールド絶縁膜３は中間
部で厚さが低減されており、かつその両側の部分にはポ
リシリコンで構成した２つの抵抗体5a,5bを離間した状
態で直列に配列している。そして、この抵抗体5a,5bをC
VD法等により形成した層間絶縁膜４で被覆し、この層間
絶縁膜４に開設したコンタクト4aを通して抵抗体5aの一
端に配線6aを、コンタクト4bを通して抵抗体5bの他端に
配線6bを夫々接続している。また、抵抗体5aの他端と抵
抗体5bの一端は、コンタクト4c,4dを通して夫々フィー
ルド絶縁膜３の中間部に設けた配線6cによって相互に接
続している。なお、前記配線6aは集積回路の端子（電極
パッド）へ接続し、配線6bは保護ダイオード，及び内部
回路へ接続している。In these figures, a field insulating film 3 usually made of a thermal oxide film of 5000 to 8000 Å is formed on a P-type substrate 1 made of silicon or the like. The field insulating film 3 has a reduced thickness in the middle, and two resistors 5a and 5b made of polysilicon are arranged in series on both sides of the field insulating film 3 in a separated state. Then, connect these resistors 5a and 5b to C
The wiring 6a is covered with the interlayer insulating film 4 formed by the VD method or the like, and the wiring 6a is connected to one end of the resistor 5a through the contact 4a formed in the interlayer insulating film 4 and the wiring 6b is connected to the other end of the resistor 5b through the contact 4b. are doing. Further, the other end of the resistor 5a and one end of the resistor 5b are connected to each other through a contact 4c, 4d by a wire 6c provided in an intermediate portion of the field insulating film 3, respectively. The wiring 6a is connected to the terminal (electrode pad) of the integrated circuit, and the wiring 6b is connected to the protection diode and the internal circuit.
更に、前記Ｐ型基板１には、前記抵抗体5a,5bの領域
を全て包含する形でＮ型不純物を低濃度に導入させたＮ
型ウエル２を形成している。そして、前記フィールド絶
縁膜３の中間部に開設したコンタクト3aに対応して高濃
度にＮ型不純物を導入したＮ型拡散層2aを形成し、前記
抵抗体5a,5bを相互接続する配線6cをこのＮ型拡散層2a
を通して前記Ｎ型ウェル２に電気接続し、Ｎ型ウェル２
にバイアス電圧を加えている。換言すれば、直列接続さ
れた抵抗体5a,5bで構成される保護抵抗５の1/2の部分の
電圧でＮ型ウェル２をバイアスしている。Further, the P-type substrate 1 has an N-type impurity introduced at a low concentration so as to include all the regions of the resistors 5a and 5b.
The mold well 2 is formed. Then, an N-type diffusion layer 2a having a high concentration of N-type impurities introduced is formed corresponding to the contact 3a opened in the middle portion of the field insulating film 3, and a wiring 6c for interconnecting the resistors 5a, 5b is formed. This N type diffusion layer 2a
Electrically connected to the N-type well 2 through
Bias voltage is applied to. In other words, the N-type well 2 is biased by the voltage of the half of the protection resistor 5 composed of the resistors 5a and 5b connected in series.
この構成によれば、端子に印加された正の静電気が配
線6aを通して保護抵抗５の一端、即ち抵抗体5aの一端に
印加されたときには、その電荷は抵抗体5a,5bを通して
減衰され、抵抗体5bの他端から配線6bを通して図外の保
護ダイオードに至り、ここで基板へと放電されることは
言うまでもない。According to this configuration, when the positive static electricity applied to the terminal is applied to one end of the protective resistor 5, that is, one end of the resistor 5a through the wiring 6a, the charge is attenuated through the resistors 5a and 5b, It goes without saying that the other end of 5b reaches the protection diode (not shown) through the wiring 6b and is discharged to the substrate there.
そしてこの時、第３図に示すように、端子及び抵抗体
5aの一端の配線6aに印加された電圧をVINとすると、抵
抗体5aと5bを接続する配線6cの点の電圧がBV2、抵抗体5
bの他端の配線6bの電圧がBV1となる。BV1は保護ダイオ
ードの逆方向耐圧と直列抵抗で決定され、BV2は保護抵
抗５の下のＮ型ウエル２及びＰ型基板１のダイオードの
逆方向耐圧と直列抵抗で決定される。通常BV2は100V以
上あり、フィールド絶縁膜３に印加される最大電圧は、
VIN−BV2となり、第６図に示した従来の構造に比較し
て、BV2分緩和される。なお、この場合、Ｎ型ウエル２
とＰ型基板１とのPNダイオードの逆方向ブレークダウン
時の直列抵抗は保護ダイオードのそれと比較して１〜２
桁大きいので、抵抗体5aと5bの抵抗値の関係は、R5a≪R
5bが望ましい。Then, at this time, as shown in FIG.
If the voltage applied to the wire 6a at one end of 5a is V IN , the voltage at the point of the wire 6c connecting the resistors 5a and 5b is BV 2 and the resistance 5
The voltage of the wiring 6b at the other end of b becomes BV 1 . BV 1 is determined by the reverse breakdown voltage and series resistance of the protection diode, and BV 2 is determined by the reverse breakdown voltage and series resistance of the N-type well 2 and the P-type substrate 1 below the protection resistor 5. Normally, BV 2 is 100V or more, and the maximum voltage applied to the field insulating film 3 is
It becomes V IN −BV 2 , which is relaxed by BV 2 as compared with the conventional structure shown in FIG. In this case, the N-type well 2
The series resistance at the time of reverse breakdown of the PN diode between the P type substrate 1 and the P type substrate 1 is 1 to 2 compared with that of the protection diode.
Since it is a digit larger, the relation between the resistance values of the resistors 5a and 5b is R 5a << R
5b is preferred.
次に、端子に基板に対して負の静電気が印加された場
合には、Ｎ型ウエル２とＰ型基板１とのダイオードは順
方向バイアスとなり、抵抗体5a,5bを接続する配線6cの
電位V6cは基板を基準として、V6c＝VF1＋IRS1となる。Next, when negative static electricity is applied to the substrate at the terminals, the diodes of the N-type well 2 and the P-type substrate 1 are forward biased, and the potential of the wiring 6c connecting the resistors 5a and 5b. V 6c is V 6c = V F1 + IR S1 with reference to the substrate.
ここで、VF1はＮ型ウエルとＰ型基板の順方向電圧、R
S1はダイオードの順方向直列抵抗である。Where V F1 is the forward voltage of the N-type well and the P-type substrate, R
S1 is the forward series resistance of the diode.
したがって、VIN−V6cが保護抵抗５とＮ型ウエル２と
の間に加わる最大電圧である。また、印加されている電
圧は負であるため、抵抗体5a下のＮ型ウエル２の表面は
反転しており、かつその程度は配線6aに接続される側程
強くなっている。このため、この最大電圧は抵抗体5aの
下側のフィールド絶縁膜３とＮ型ウエル２表面の反転
層，空乏層に分配され、フィールド絶縁膜３の破壊強度
が向上する。Therefore, V IN -V 6c is the maximum voltage applied between the protection resistor 5 and the N-type well 2. Further, since the applied voltage is negative, the surface of the N-type well 2 below the resistor 5a is inverted, and the degree thereof is stronger on the side connected to the wiring 6a. Therefore, this maximum voltage is distributed to the field insulating film 3 below the resistor 5a, the inversion layer and the depletion layer on the surface of the N-type well 2, and the breakdown strength of the field insulating film 3 is improved.
なお、この場合Ｎ型ウエル２とＰ型基板１がダイオー
ド動作をするので、その接合を保護するためには、R5a
≫R5bが望ましい。In this case, since the N-type well 2 and the P-type substrate 1 operate as a diode, in order to protect the junction, R 5a
>> R 5b is preferred.
以上、正，負の電圧が印加された場合について述べた
が、夫々の場合においてR5a,R5bの関係が逆の関係とな
るため、保護ダイオード,N型ウエルとＰ型基板のダイオ
ードの特性，保護抵抗の抵抗値等からＮ型ウェル２のバ
イアス点を決める必要がある。The case where positive and negative voltages are applied has been described above. However, since the relationship between R 5a and R 5b is opposite in each case, the characteristics of the protection diode, the N-type well and the diode of the P-type substrate It is necessary to determine the bias point of the N-type well 2 from the resistance value of the protective resistance and the like.
更に、この構成では、保護抵抗５の下側のＮ型ウエル
２はＰ型基板１に対してPN接合にて分離されているた
め、仮に端子側の抵抗体5a下のフィールド絶縁膜３が破
壊してＮ型ウエルと短絡しても、リーク，動作等に影響
を与えず、不良となることはない。Further, in this configuration, since the N-type well 2 below the protective resistor 5 is separated from the P-type substrate 1 by the PN junction, the field insulating film 3 below the resistor 5a on the terminal side is destroyed. Even if a short circuit is made with the N-type well, there is no influence on leakage, operation, etc., and no failure occurs.
第４図は第１実施例の平面配置を変えた例である。即
ち、抵抗体5a,5bを並列配置し、その一方の端部におい
て配線6cで両抵抗体を接続し、かつここでＮ型ウェル２
への電気接続を行っている。なお、第１実施例と同一部
分には同一符号を付してある。FIG. 4 is an example in which the plane arrangement of the first embodiment is changed. That is, the resistors 5a and 5b are arranged in parallel, and at one end thereof, the resistors 6a and 5b are connected by the wiring 6c.
Have an electrical connection to. The same parts as those in the first embodiment are denoted by the same reference numerals.
この実施例においても前記実施例と同じ効果が得られ
ることは言うまでもない。更に、この実施例ではＮ型ウ
エル２をバイアスするためのＮ型拡散層2aがＮ型ウエル
２のほぼ中央にあるため、Ｎ型ウエル２とＰ型基板１と
のダイオードの強度が向上するという利点がある。It is needless to say that the same effect as the above embodiment can be obtained in this embodiment. Further, in this embodiment, since the N-type diffusion layer 2a for biasing the N-type well 2 is located almost at the center of the N-type well 2, the strength of the diode between the N-type well 2 and the P-type substrate 1 is improved. There are advantages.
第５図は本発明の第２実施例の断面図であり、この実
施例はバイポーラ集積回路等のように、エピタキシャル
層を用いる半導体集積回路に本発明を適用した例であ
る。図において、第１図と同一部分には同一符号を付し
てある。FIG. 5 is a sectional view of a second embodiment of the present invention, which is an example in which the present invention is applied to a semiconductor integrated circuit using an epitaxial layer such as a bipolar integrated circuit. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals.
この実施例では、シリコン等のＰ型基板７の表面にＰ
型或いはＮ型エピタキシャル層を成長させ、ここに各種
素子を形成しているが、フィールド絶縁膜３上に形成し
た抵抗体5a,5bの下側には絶縁用Ｐ型拡散層９によって
画成されたＮ型エピタキシャル層８を形成している。In this embodiment, P is formed on the surface of the P-type substrate 7 such as silicon.
Type or N type epitaxial layer is grown and various elements are formed therein. Below the resistors 5a and 5b formed on the field insulating film 3, an insulating P type diffusion layer 9 is formed. The N-type epitaxial layer 8 is formed.
したがって、このＮ型エピタキシャル層８は第１実施
例のＮ型ウェル２と等価な働きをし、フィールド絶縁膜
３の破壊電圧を向上する。Therefore, the N-type epitaxial layer 8 functions equivalently to the N-type well 2 of the first embodiment and improves the breakdown voltage of the field insulating film 3.
なお、本発明では保護抵抗を３個以上の抵抗体で構成
してもよく、かつ各抵抗体の任意の接続点で逆導電型不
純物層をバイアスしてもよい。In the present invention, the protective resistor may be composed of three or more resistors, and the opposite conductivity type impurity layer may be biased at an arbitrary connection point of each resistor.
以上説明したように本発明は、保護抵抗下に基板とは
逆導電型の低濃度不純物層を設け、この不純物層の電位
を保護抵抗の端子側接点以外の部分から供給するように
構成しているので、保護抵抗下の絶縁膜の破壊強度を向
上させ、信頼度の高い保護装置を提供できる効果があ
る。As described above, the present invention is configured such that a low-concentration impurity layer having a conductivity type opposite to that of the substrate is provided under the protective resistance, and the potential of the impurity layer is supplied from a portion other than the terminal side contact of the protective resistance. Therefore, there is an effect that the breakdown strength of the insulating film under the protective resistance is improved and a highly reliable protective device can be provided.
第１図は本発明の第１実施例の平面図、第２図は第１図
のＡ−Ａ線に沿う断面図、第３図は本発明の効果を説明
するための電位分布図、第４図は第１実施例の変形例の
平面図、第５図は本発明の第２実施例の断面図、第６図
は従来構造の断面図である。 １……Ｐ型基板、２……Ｎ型ウェル、３……フィールド
絶縁膜、3a……コンタクト、４……層間絶縁膜、4a〜4d
……コンタクト、５……保護抵抗、5a,5b……抵抗体、6
a,6b,6c……配線、７……Ｐ型基板、８……Ｎ型エピタ
キシャル層、９……絶縁用Ｐ型拡散層。1 is a plan view of the first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG. 1, FIG. 3 is a potential distribution diagram for explaining the effect of the present invention, and FIG. FIG. 4 is a plan view of a modification of the first embodiment, FIG. 5 is a sectional view of a second embodiment of the present invention, and FIG. 6 is a sectional view of a conventional structure. 1 ... P-type substrate, 2 ... N-type well, 3 ... field insulating film, 3a ... contact, 4 ... interlayer insulating film, 4a-4d
...... Contact, 5 …… Protection resistance, 5a, 5b …… Resistance body, 6
a, 6b, 6c ... Wiring, 7 ... P-type substrate, 8 ... N-type epitaxial layer, 9 ... Insulating P-type diffusion layer.
Claims (1)
第１及び第２の保護抵抗を分離して形成し前記第１の抵
抗の一端側を集積回路の端子に接続し、前記第２の抵抗
の一端側を内部回路に接続し、これら第１及び第２の抵
抗の他端側どうしを配線によって接続し、かつ前記第１
及び第２の保護抵抗の直下に対応する半導体基板には該
半導体基板と逆導電型の低濃度不純物層を形成するとと
もに、この低濃度不純物層と前記配線とを電気的に接続
したことを特徴とする半導体集積回路の保護装置。1. An insulating film on the surface of a semiconductor substrate of one conductivity type,
First and second protective resistors are separately formed, one end side of the first resistor is connected to a terminal of an integrated circuit, one end side of the second resistor is connected to an internal circuit, and the first and second protective resistors are formed. The other ends of the second resistors are connected to each other by wiring, and the first resistor is connected.
And a low-concentration impurity layer having a conductivity type opposite to that of the semiconductor substrate is formed on the semiconductor substrate immediately below the second protective resistor, and the low-concentration impurity layer and the wiring are electrically connected. And a semiconductor integrated circuit protection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63114585A JP2522350B2 (en) | 1988-05-13 | 1988-05-13 | Semiconductor integrated circuit protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63114585A JP2522350B2 (en) | 1988-05-13 | 1988-05-13 | Semiconductor integrated circuit protection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01286460A JPH01286460A (en) | 1989-11-17 |
| JP2522350B2 true JP2522350B2 (en) | 1996-08-07 |
Family
ID=14641533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63114585A Expired - Lifetime JP2522350B2 (en) | 1988-05-13 | 1988-05-13 | Semiconductor integrated circuit protection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522350B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115428150A (en) * | 2020-04-08 | 2022-12-02 | 罗姆股份有限公司 | Semiconductor device with a plurality of transistors |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63258056A (en) * | 1987-04-15 | 1988-10-25 | Seiko Instr & Electronics Ltd | semiconductor equipment |
-
1988
- 1988-05-13 JP JP63114585A patent/JP2522350B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01286460A (en) | 1989-11-17 |
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