JPH05129318A - Manufacture of bipolar transistor - Google Patents

Abstract

(57) [Summary] (Modified) [Objective] To provide a bipolar transistor capable of protecting a polysilicon layer during wet etching of a nitride film and suppressing generation of defects in electrical characteristics of a semiconductor device. A thin oxide film 13 which is an erosion preventive layer for a poly layer is provided on the first nitride film 12, and then a first poly layer 14,
A step of sequentially providing the second nitride film 15 and the second poly layer 16, a step of patterning the photoresist to selectively etch the second poly layer, and ion implantation of impurities,
An annealing step, an etching step of etching the second poly layer and the second nitride film, and a poly layer doped and an undoped poly layer of the first poly layer during the ion implantation step. It comprises a step of selectively etching, a step of implanting boron nitride into the poly layer, a step of partially oxidizing the poly layer to form an oxide film, and a step of selectively etching the first nitride film. Manufacturing method of bipolar transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is self-aligning (self).
A high-speed and highly integrated bipolar transistor manufacturing method using the (align) technology, in particular, P generated during the manufacturing process.
The present invention relates to a method for manufacturing a bipolar transistor in which structural defects due to non-uniform etching of type polysilicon are eliminated.

[0002]

BACKGROUND OF THE INVENTION Bipolar transistors are becoming finer devices as the speed and integration become higher, and the junction depth becomes shallower and the base becomes thinner. Due to such a tendency, the degree of integration is inferior to that of the MOS transistor and the unit cost per bit is high, but the bipolar transistor is widely used in a department requiring a high operation speed because of its short transmission delay time. Has been done. In particular, polycrystalline silicon self-aligned (poly)
Since the development of silicon self-aligned technology, the shallow junction depth of 0.1-0.2 μm is adjusted by self-aligning the base and emitter with P-type and N-type doped polycrystalline silicon. It becomes easy and there are many possibilities in terms of integration.

The manufacturing process of a conventional NPN bipolar ton radiator using such a self-alignment technique is as follows. First, as shown in FIG. 5A, a pad oxide film 1 is formed on a silicon substrate, and a first nitride film 2, a first polysilicon layer 3, a second nitride film 4 and a second polysilicon film are formed on the pad oxide film 1. After sequentially depositing layers 5, photoresist 6 is applied over the entire surface. The photoresist 6 is then patterned to form an emitter / base region, and a second
After the polysilicon layer 5 is selectively etched, the photoresist 6 is removed.

Subsequently, as shown in FIG. 5B, impurities are ion-implanted by a double ion implantation method, and an annealing treatment is performed at a high temperature. After that, as shown in FIG. 5C, the second polysilicon 5 and the second nitride film 4 are sequentially removed. Next, as shown in FIG. 5D, the doped polysilicon layer 8 of the polysilicon layer 3 is left, and the undoped polysilicon layer 7 is selectively wet-etched using potassium hydroxide.

Subsequently, as shown in FIG. 5E, boron nitride (BN) is implanted into the entire surface of the polysilicon layer 8 to partially thermally oxidize the polysilicon layer 8 to form a thermal oxide film 9.
As shown in FIG. 5F, the first nitride film 2 is wet-etched using a phosphoric acid (H ₃ PO ₄ ) compound. Meanwhile, in the conventional NPN bipolar transistor, during the wet etching process of the nitride film 2, if the doped polysilicon layer 8 is exposed to phosphoric acid for a long time, corrosion 10 of the polysilicon layer 8 occurs. The occurrence of such defects cannot be completely eliminated only by appropriately adjusting the temperature, the composition ratio of the chemicals used, the pressure, etc., which are variable factors in the process, and the optimum process obtained by optimizing the process. Even in the state, it is difficult to maintain the optimum process state in which the erosion 10 of the polysilicon layer is minimized due to each external factor.

Further, structural defects in the extrinsic base region are generated due to incomplete polyrefill of the polysilicon layer due to erosion of the polysilicon layer, and the increase in resistance due to the defects increases the operating speed of the device. A fatal problem such as a decrease has occurred.

[0007]

DISCLOSURE OF THE INVENTION An object of the present invention is to deposit an oxide film between a nitride film and a polysilicon layer in order to prevent erosion of the polysilicon layer and to protect the polysilicon layer during wet etching of the nitride film. Another object of the present invention is to provide a bipolar transistor capable of suppressing the occurrence of defects in the electrical characteristics of semiconductor elements.

An object of the present invention is a method for manufacturing a bipolar transistor, which comprises sequentially depositing a pad oxide layer and a first nitride film on a silicon substrate, and then depositing the first oxide film on the first nitride film. A step of depositing a thin oxide film which is an erosion preventive layer of the polysilicon layer, and then a first polysilicon layer, a second nitride film and a second polysilicon layer in this order; and a step of applying a photoresist. Patterning the photoresist to selectively etch the second polysilicon layer; removing the photoresist, ion-implanting impurities, and then performing an annealing treatment; and the second polysilicon layer. Etching the second nitride film, and a polysilicon layer doped in the ion implantation step in the first polysilicon layer and a dope. A step of selectively etching a polysilicon layer which is not formed; a step of implanting boron nitride into the polysilicon layer; a step of partially thermally oxidizing the poly layer to form an oxide film; And a step of selectively etching the nitride film.

Further, in the method of manufacturing a bipolar transistor, a nitride film is formed between a nitride film defining an extrinsic base region and a polysilicon layer located above the nitride film as an erosion preventing layer for the polysilicon layer. It is achieved by a method for manufacturing a bipolar transistor, which is characterized in that a medium having an etching ratio smaller than that of the method described above is deposited. In this bipolar transistor manufacturing method, it is preferable to deposit a thin oxide film as the erosion preventive layer of the polysilicon layer, and the lower part of the polysilicon layer is oxidized to be used as the erosion preventive layer of the polysilicon layer. Preferably, a wet etching method, a chemical dry etching method or a dry etching method can be adopted as the etching method of the nitride film.

Hereinafter, the present invention will be specifically described with reference to examples.

[0011]

1A to 1D are explanatory views of a manufacturing process of a bipolar transistor according to the present invention. In the present invention, a pad oxide film 11 having a thickness of about 400 to 600 Å is formed on a silicon substrate.
After the formation, the first nitride film 12 is formed on the top of the
Deposit a thickness of 0 to 1500Å, and deposit a thin oxide film 13 on the surface of the thin oxide film 13 to form an erosion preventive layer for the poly layer (polysilicon layer).
After forming a thickness of 0Å, a first poly layer 14 having a thickness of about 5000 to 6000Å and a second poly layer 14 having a thickness of about 1000 to 1500Å
Of the nitride film 15 are sequentially deposited, and the second poly layer 1 is formed on the nitride film 15.
6 is laminated to a thickness of about 6000 to 7000Å, then a photoresist is applied on the entire surface, the photoresist is patterned, and the second poly layer 16 is selectively etched.
The photoresist is removed and impurities are ion-implanted,
An anneal process is performed, the second poly layer 16 and the second nitride film 15 are subsequently etched, and a poly layer 18 of the first poly layer 14 that is doped during the ion implantation process is used.
And a step of selectively etching the undoped poly layer 17, implanting boron nitride (BN) into the poly layer 18, partially thermally oxidizing the poly layer 18, and further etching the first nitride film 12. It is equipped with.

2A-4I show an NPN using the present invention.
It is explanatory drawing which shows the manufacturing process of a bipolar transistor. First, as shown in FIG. 2A, after depositing a first oxide film 103 on a P-type single crystal silicon substrate 101, a photoresist is applied on the entire surface, and a photoresist is formed to form a barried layer 102. After patterning and selective etching of the first oxide film 103, the photoresist is removed. Then, impurities are ion-implanted by an ion implantation method, and drive-in diffusion is performed to form the N ⁺ beried layer 102, and then the N ⁻ epi layer 104 is epitaxially grown.

Then, a first pad oxide film and a silicon nitride film (Si ₃ N ₄ ) are sequentially deposited on the entire surface of the N ⁻ epi layer 104, and then a photoresist is applied on the entire surface to form a first LOCOS film. After patterning to form a separation layer and selectively etching the silicon nitride film, the photoresist is removed, and impurities are ion-implanted using the silicon nitride film as a mask to form a first LOCOS separation layer. Next, after etching the residual silicon nitride film and the first pad oxide film, the first LOCOS isolation layer is washed.

Subsequently, a second pad oxide film and a silicon nitride film are sequentially deposited on the first LOCOS isolation layer, and then the silicon nitride film is selectively etched by a reactive ion etching (reactive ion etching) method. Then
Photoresist is applied and patterned for channel formation. Impurities are ion-implanted here, the photoresist is removed, and then annealing is performed at a high temperature.

After that, a silicon oxide film and a silicon nitride film are vapor-deposited, a photoresist is applied thereon, and patterning is performed for forming the second LOCOS isolation layer 105. Then, the silicon nitride film is selectively formed. The second LOCOS isolation layer 1 is formed by etching, ion-implanting impurities, and then oxidizing.
Then, the photoresist, the silicon nitride film, and the silicon oxide film are sequentially removed.

Then, as shown in FIG. 2B, the second LOC
A thickness of about 40 on the OS isolation layer 105 and the N ^- epi layer 104.
A third pad oxide layer 106 having a thickness of 0 to 600Å is formed, and a thickness of about 1000 to 1500Å is formed on the pad oxide layer 106.
After the silicon nitride film 107 is deposited, a thin oxide film 108 having a thickness of about 200Å is deposited to prevent corrosion of the poly layer.

Next, a photoresist 109 is applied on the entire surface of the oxide film 108 and patterned so as to have an opening on the N ⁻ type epi layer 104 which is a collector formation region, and the photoresist 109 is masked. As a result, after the thin oxide film 108 and the silicon nitride film 107 are etched through the formed opening, impurities are implanted by an ion implantation method.

Thereafter, as shown in FIG. 2C, the oxide film 106 is etched by a wet etching method to remove the photoresist 109, and then the polysilicon layers 110, 1 are formed.
11 is vapor-deposited to a thickness of about 5000 to 6000Å. A silicon nitride film 112 is vapor-deposited here, and a photoresist is applied thereon to form a pattern on the polysilicon layers 110 and 111 to have openings for forming LOCOS isolation regions, and the resist film is masked. As a result, the silicon nitride film 112 is etched. Next, the polysilicon layers 110 and 111 are selectively oxidized to form a poly LOCOS oxide layer 113, and then the photoresist and the silicon nitride film 112 are etched.

Subsequently, as shown in FIG. 3D, a silicon nitride film 114 is deposited to a thickness of about 1000 to 1500 Å, a polysilicon layer 115 is deposited to a thickness of about 6000 to 7000 Å, and then the polysilicon layer 115 is deposited. After applying a photoresist and patterning so that only the polysilicon layer 115 on the emitter formation region and the collector formation region remains, the polysilicon layer 115 is selectively etched. Then, the photoresist is removed, for example, 100 to 12
After further implanting boron ions (B ⁺ ) with an acceleration voltage of 0 KeV and a dose amount of 1.6E16 / cm ² , further 7
Dose amount 1.4E16 / c at accelerating voltage of 0 to 90 KeV
Double ion implantation of boron ions (B ⁺ ) is performed under the condition of m ² . Then, after performing heat treatment (annealing treatment) at 900 ° C. for 30 minutes in a nitrogen atmosphere, the thickness of 6000 to 70
Remove the 00Å polysilicon layer 115 to a thickness of 1000
The silicon nitride film 114 of about 1500 Å is removed.

Then, as shown in FIG. 3E, poly-LOCO
A silicon nitride film 116 for an emitter window is deposited on the S oxide layer 113 and the polysilicon layers 110 and 111, a polysilicon layer 117 for an emitter window is deposited on the silicon nitride film 116, and then a photoresist is formed on the entire surface. Is applied and patterned to form an emitter window, the polysilicon layer 117 and the silicon nitride film 116 are etched, and then the photoresist is removed.

Subsequently, as shown in FIG. 3F, the polysilicon layer 117 and the silicon nitride film 116 are completely etched, and then the polysilicon layers 110 and 111 having a thickness of 5000 to 6000 Å are selectively etched. Then, on the extrinsic base electrode doped polysilicon layer 110, boron trioxide glass (B ₂ O ₃ gl) was used.
The boron nitride (BN), which is a solid state source surrounded by (ass), has a sheet resistance of 50Ω at 950 ° C. for 40 minutes.
And then depositing the polysilicon layer 110 from 2000 to
A thickness of 3000 Å is oxidized to form a polysilicon oxide film 118, and a thin oxide film 108 in the emitter region and a thickness of 90 are formed.
After wet etching the silicon nitride film 107 of about 00Å with a phosphoric acid compound at 170 ° C., the extrinsic base region formed in the next step and the doped polysilicon layer 110 which is the extrinsic base electrode are connected to each other, Thickness 40
The pad oxide film 106 of 0 to 600 Å is wet-etched.

Then, as shown in FIG. 4G, the thickness 2000
After filling the Å polysilicon layer 119, at 900 ℃ 3
When the drive-in diffusion is performed in a nitrogen atmosphere for 0 minutes, the boron ions contained in the doped polysilicon layer 110 are diffused into the filled polysilicon layer 119 and the extrinsic base region of the silicon substrate. Thereafter, as shown in FIG. 4H, the polysilicon layer 119 in which boron ions are not diffused is selectively etched using potassium hydroxide, and the polysilicon layer 110 and the single crystal silicon substrate doped by an oxidation process are etched. And are simultaneously oxidized to form an oxide film 120 having a thickness of 700 to 1000 Å, and then impurities are implanted into the extrinsic base region by an ion implantation method.

Next, as shown in FIG. 4I, an insulating LTO (Low Tempe) is provided between the emitter and the extrinsic base.
(rature oxide) film 121 to 1000-20
Polysilicon layer 1 for emitter electrode, deposited to a thickness of 00Å
After depositing 22 to a thickness of 2000 to 3000 Å, dry etching is performed to form spacers of the polysilicon layer 122.

Next, the oxide film 120 is etched by a reactive ion etching method so as to leave only a thickness of 500 .ANG., And further wet-etched to completely etch the upper portion of the intrinsic base. Subsequently, the emitter polysilicon layer 122 is vapor-deposited to a thickness of about 3000 Å, impurities are ion-implanted, and an annealing process is performed at a high temperature. Then, a photoresist is applied and patterned to form a polysilicon layer 122 for the emitter electrode, and the polysilicon layer 122 is subjected to reactive ion etching (reactive ion etching).
After selective etching by the method, the photoresist is removed.

Next, a photoresist is further applied to the entire surface, patterned to form a first base electrode, the oxide film 118 in the first base electrode forming portion is etched, and then the photoresist is removed. Subsequently, an oxide film 124 which is an interlayer insulating film is vapor-deposited, a polysilicon layer is vapor-deposited, impurities are implanted by an ion implantation method, an annealing treatment is performed, and then a photoresist is applied to form a high resistance region. Pattern, etch, and remove photoresist.

After that, an oxide film 124 is vapor-deposited, and a photoresist is further applied. Then, the oxide film is patterned to contact the emitter (E) -base (B) -collector (C) regions, and the oxide film is partially etched. After removing the photoresist, the metal is sputtered, then the photoresist is applied and patterned, and the metal film outside the emitter-base-collector region is etched before removing the photoresist and alloying.

The NPN bipolar transistor is completed by these steps. The bipolar transistor manufacturing method described above can be used not only in the NPN bipolar transistor but also in the PNP bipolar transistor manufacturing process. Further, in the above-mentioned process, the thin oxide film deposition process prevents corrosion of the poly layer. As the layer, a medium having an etching ratio of a phosphoric acid (H ₃ PO ₄ ) compound smaller than that of a silicon nitride film can be vapor-deposited and used.
The lower part of the poly layer can be oxidized to be used as an anticorrosion layer for the poly layer, and the etching method of the silicon nitride film is not limited to the wet method, but CDE (chemical dry etching) in which chemicals are evaporated and gasified for etching. It is also possible to use isotropic dry etching.

[0028]

According to the present invention, a doped polysilicon layer used as an extrinsic base during wet etching of a silicon nitride film is exposed to a phosphoric acid compound for a long time and corroded to form a wet-etched silicon nitride film. The undoped polysilicon filled in the oxide film is incompletely filled and structural defects occur, which cause defects in the electrical characteristics of the device between the silicon nitride film and the polysilicon. Oxide film can be minimized by applying a thin film, and structural defects due to non-uniform etching of the polysilicon layer and electrical property defects such as a decrease in the operating speed of bipolar transistors can be suppressed. In addition, it has a process condition that facilitates wet etching of the silicon nitride film, which greatly contributes to stabilization of the semiconductor device. Features of the like are achieved.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a manufacturing process of a bipolar transistor of the present invention.

FIG. 2 is an explanatory view showing a manufacturing process of an NPN bipolar transistor using the present invention.

FIG. 3 is an explanatory view showing a manufacturing process of an NPN bipolar transistor using the present invention.

FIG. 4 is an explanatory view showing a manufacturing process of an NPN bipolar transistor using the present invention.

FIG. 5 is an explanatory view showing a manufacturing process of a conventional NPN bipolar ton transistor.

[Explanation of symbols]

 11 Pat Oxide Film 12 First Nitride Film 13 Oxide Film 14 First Poly Layer 15 Second Nitride Film 16 Second Poly Layer

Claims (5)

[Claims] 1. A method of manufacturing a bipolar transistor, comprising depositing a pad oxide film and a first nitride film on a silicon substrate in order, and then forming a thin oxide film which is an erosion preventive layer of a poly layer on the first nitride film. Providing a film, and then providing a first poly layer, a second nitride film, and a second poly layer in this order, applying a photoresist, and patterning the photoresist to select a second poly layer Etching, removing the photoresist, ion-implanting impurities, and then annealing, etching the second poly layer and the second nitride film, and the first poly layer Among them, a step of selectively etching a doped poly layer and an undoped poly layer during the ion implantation step, a step of implanting boron nitride into the poly layer, and a portion of the poly layer Process and method for producing a bipolar transistor, characterized by comprising comprises a step of selective etching the first nitride film is oxidized to form an oxide film on the. 2. A method of manufacturing a bipolar transistor, comprising: a nitride film defining an extrinsic base region and a poly layer located above the nitride film, which is used as an erosion preventive layer for the poly layer compared to the nitride film. And a medium having a small etching ratio is provided. 3. A method of manufacturing a bipolar transistor according to claim 2, wherein a thin oxide film is provided as an erosion preventive layer for the poly layer. 4. The method for manufacturing a bipolar transistor according to claim 2, wherein the lower portion of the poly layer is oxidized to form an erosion preventing layer for the poly layer. 5. The method of manufacturing a bipolar transistor according to claim 2, wherein a wet etching method, a chemical dry etching method or a dry etching method is used as the etching means for the nitride film.