JPH01112770A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to convert to reactive plasma etching by hot phosphoric acid water solution by providing a secondary insulation film between an oxidation resistant insulation film on a primary insulation film and a primary conductor film when forming an overhung section by side-etching the oxidation resistant insulation film to form an external base region. CONSTITUTION:An oxide film 6 is formed over the entire surface of a silicon substrate and a silicon nitride film 7 is deposited as an oxidation resistant insulation film all over there including a trench region and an insulation film region for separation. Then a CVD silicon oxide film 8 is accumulated as a secondary insulation film thereover. After a polycrystalline silicon film 9 is grown all over as a primary conductor film, boron is ion-implanted thereover and the silicon film 9 is eliminated by etching. The secondary oxide film 8 for surface treatment is successively eliminated thereafter until the silicon nitride film 7 for surface treatment of the secondary oxide film is exposed. Then the silicon nitride film 7 of the opening is eliminated by using thermal oxide films 19, 29 formed on the upper and side surface of the film 9 as masks until the primary oxide film 6 is exposed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a high-performance bipolar device in which a base region and an emitter region are formed in a self-aligned manner with good controllability. The present invention relates to a method for manufacturing a transistor.

(Prior Art) High-performance bipolar transistor devices are required in various application fields such as g-son computers, optical communications, and various analog circuits. Recently, several self-alignment techniques for base and emitter regions have been proposed, and the cutoff frequency of prototype bipolar transistors is about to reach 30 GHz. (For example, ■IEEE Trans.

on Electron Device, vol.
HD-33, No, 4. Apr.

1986, p. 526. ■Unexamined Japanese Patent Publication No. 58-7862, ■IEDM'86.1986. p. 420)
A typical conventional technique will be explained below and its problems will be clarified. 6. FIGS. 3(a) to 3(d) are sectional views showing the manufacturing process of the conventional example in order of process. A wafer is used in which an n-type epitaxial layer 103 is formed on a p-type silicon substrate 101 with an n-type buried layer 102 interposed therebetween. A p-type layer 1104 serving as a channel stopper is formed in the element isolation region of this wafer, and an oxide film 105 is formed by selective oxidation. After forming a thin thermal oxide film 106 on the surface of the element region of the second wafer, a nitride film (Si2N3 film) 107 serving as an oxidation-resistant mask is deposited on the entire surface, and then a first polycrystalline silicon film 108 is deposited. . An unnecessary portion of the first polycrystalline silicon film 108 on the element isolation region is converted into an oxide film 109 by thermal oxidation. Next, boron is added to the first polycrystalline silicon v4108 by ion implantation, and the first polycrystalline silicon film 108 on the emitter formation region is etched by photoetching to form an opening. (Figure 3(a)).

Thereafter, an oxide film 110 is formed on the surface of the polycrystalline silicon film 108 by heat treatment in an oxidizing atmosphere, and this oxide film 11
Using 0 as a mask, the nitride film 107 in the opening is removed by etching with a heated phosphoric acid aqueous solution. And the exposed oxide film 10
6 is removed with an NH4F aqueous solution to expose the wafer surface. At this time, by intentionally over-etching the nitride film 107 in the opening, an overhang part 111 is formed, and the first polycrystalline silicon film 108 is
(Fig. 3(b)).

Next, a second polycrystalline silicon film 112 is deposited on the entire surface to fill the cavity under the overhang part 111, and then the second polycrystalline silicon film is etched to form an oxide film 10.
6 and expose the wafer surface of the opening (Figure 3(c)
)).

Next, when forming an oxide film 113 by thermal oxidation on the exposed wafer surface and side surfaces of the polycrystalline silicon film, boron, which has been doped in advance into the first polycrystalline silicon film 108, is added to the overhang portion 111. is diffused into the wafer through the second polycrystalline silicon film 112 to form a p-type extrinsic base Jim 114. Thereafter, a p-type internal base 115 is formed by boron ion implantation. Next, a CVD insulating film 116 and a third polycrystalline silicon film 117 are deposited, and these are etched by reactive ion etching, leaving them only on the side walls of the opening, and the opening is opened using the third polycrystalline silicon film 117 as a mask. Remove the oxide film on the wafer surface. Then, a fourth polycrystalline silicon film 118 into which arsenic is ion-implanted at a high concentration is deposited, and the arsenic is diffused by heat treatment to form an n-type emitter layer 119, thereby completing the process (FIG. 3(d)).

The first and second polycrystalline silicon films 108 and 112 are used as base electrodes, and the fourth polycrystalline silicon film 118 is used as an emitter electrode.

According to the conventional method, the base and emitter are formed in self-alignment, and the width is 0.35μ from the emitter diffusion window.
A fine structure of m is possible. As a result, a bipolar transistor capable of high-speed operation is obtained. However, this method has the disadvantage that it is difficult to control the size of the overhang shown in FIG. 3(b). As mentioned above, the process of forming this overhang is a process of etching the nitride film with a heated aqueous phosphoric acid solution.

It is difficult to control temperature, phosphoric acid concentration, stirring conditions, etc.

Therefore, the size of the overhang varies between wafers and within a wafer, which causes variations in device characteristics.

(Problems to be Solved by the Invention) As mentioned above, in the conventional manufacturing method of high-performance bipolar transistors, the over-etching which determines the structural dimensions depends on the amount of etching by the heated aqueous phosphoric acid solution. In this etching with a heated aqueous phosphoric acid solution, the etching rate varies greatly depending on the temperature and also varies depending on the concentration, so it is extremely difficult to control the size of etching by over-etching in terms of reproducibility. For this reason, there has been a serious problem that a bipolar transistor that stably exhibits high-speed performance cannot be obtained.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that provides an improved bipolar transistor.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a first insulating film, an oxidation-resistant a step of sequentially laminating and depositing an insulating film, a second insulating film, and a first conductive film;
A step of adding impurity atoms of a second conductivity type to the first conductive film at a high concentration and removing the first conductive film in the area where the emitter region is to be formed until the second insulating film is exposed to form an opening. a step of removing the second insulating film in the opening to expose the oxidation-resistant insulating film; a step of changing the exposed portion of the first conductive film to a third insulating film; The oxidation-resistant insulating film exposed using the insulating film as a mask is removed by etching until the first insulating film is exposed, and then further over-etched in the area where the base region is to be formed, leaving the first conductive film and therebelow. forming a cavity under the second insulating film, etching away the exposed first insulating film until the semiconductor substrate is exposed, and at the same time etching the second insulating film exposed above the cavity into a first conductor. a step of etching away the film until it is exposed; a step of selectively embedding a second conductor film that will become a part of the base electrode in the cavity; and a step of removing the semiconductor substrate exposed to the opening and the second conductor film. forming a thermally oxidized film on the side wall portion of the conductor film, and at the same time, diffusing impurity atoms of a second conductivity type added in advance to the first conductor film into the collector layer to form an external base layer of a second conductivity type; , adding impurity atoms of a second conductivity type to the exposed portion of the opening of the semiconductor substrate to form an internal base layer of the second conductivity type; and placing the semiconductor substrate in the opening in which the internal base layer is formed. A step of exposing and depositing a third conductor film thereon to become a part of the emitter electrode, and diffusing impurity atoms into the semiconductor substrate through the third conductor film to form an emitter layer of the first conductivity type. The method is characterized in that the oxidation-resistant insulating film is etched away by reactive plasma etching using the first insulating film and the second insulating film as masks.

(Function) This invention provides a second insulating film between the oxidation-resistant insulating film on the first insulating film and the first conductor film. As a result, side etching of the oxidation-resistant insulating film can be performed as long as it is selective between the insulating film and the oxidation-resistant insulating film, reactive plasma etching can be used, and conventional heating is not required. It is no longer necessary to use an aqueous phosphoric acid solution.

In etching using a heated aqueous phosphoric acid solution, the etching rate varies greatly depending on the temperature and also on the concentration of the aqueous solution, making it extremely difficult to control the magnitude of overetching. Etching using phosphoric acid aqueous solution can be changed to reactive plasma etching with good controllability.

(Example) An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing a method for manufacturing a bipolar transistor according to an embodiment in the order of steps.

First, for device isolation of bipolar transistors, an n-type high concentration impurity layer 2 is formed on a p-type silicon substrate, and an n-type relatively lightly doped layer (~1×10"an"'3) epitaxial layer 3 is formed. After forming by a vapor phase growth method, an insulating oxide film 5 is formed in a trench region 4 as an element isolation and in an electrode isolation region separating a base emitter region and a collector contact portion using a trench technique and a selective oxidation technique. . Further, the n-type highly impurity layer 2 is connected to a collector contact (not shown), so the epitaxial layer 3 made of a lightly doped epitaxial layer forms a part of the collector. Thermal oxidation is applied to the entire surface of the silicon substrate to a thickness of 50 mm.
A silicon oxide film 6 is formed on the silicon nitride film 7 (Si, N, film) as an oxidation-resistant insulating film over the entire surface including the trench region and isolation insulating film region.
00 people deposited. Furthermore, 500 CvD silicon oxide films 8 are deposited thereon as a second insulating film. Then,
Polycrystalline silicon [9 is a thickness of 4] is used as the first conductor film on the entire surface.
000 people (Figure 1(a)).

Next, boron was applied to the polycrystalline silicon film 9 at 50 KeV.
Ion implantation is performed under the condition of 5 x 101 scs-''.

Subsequently, the polycrystalline silicon film 9 on the region that will later correspond to the emitter diffusion region is removed by photolithography and etching. Thereafter, the underlying second oxide film 8 is also successively removed until the silicon nitride film 7 underlying the second oxide film is exposed (FIG. 1(b)).

Thereafter, wet oxidation at 900° C. is performed to form a thermal oxide film 19.29 on the top and side surfaces of the polycrystalline silicon film 9 by about 4,000 layers. Next, using the thermal oxidation [19, 29 as a mask, the silicon nitride film 7 in the opening is removed by reactive plasma etching until the underlying first oxidation B'Js is exposed. After the underlying first oxide film 6 is exposed, this etching is further intentionally over-etched, and the silicon nitride film 7 is side-etched by about 2000 steps to form a cavity 10 directly under the polycrystalline silicon film 9. do. Thereafter, the exposed first silicon oxide film 6 and second silicon oxide film 8 are removed by etching with an NH4'F solution or the like (FIG. 1(c)).

Next, a polycrystalline silicon film 11 is applied to the entire surface as a second conductor film, and the cavity 10 directly under the polycrystalline silicon (Fig. 1 (C)) exposed in the ring part is completely covered. The embedded second polycrystalline silicon film is removed by reactive plasma etching until the oxide film 9 and the surface of the silicon substrate are exposed, leaving the polycrystalline silicon film 11 in the overhang part (see FIG. 1(d)). )).

Next, wet oxidation is performed on the exposed surface of the silicon substrate and the side wall portion of the polycrystalline silicon film 11 to form a silicon oxide [31] with a thickness of 700 nm. At this time, boron is added to the first conductive material in advance and diffused into the underlying silicon substrate through the polycrystalline silicon film 11 in the overhang portion to form a p-type external base region 12.

And boron at 20KeV.

Perform ion implantation under the condition of 2×10"am'"2-? ju
An M,p-type internal base region 13 is formed in the silicon substrate.

Subsequently, the thermal oxide film 19 formed in the opening is removed by directional etching to expose the silicon substrate surface and form an emitter opening 14. After that, a polycrystalline silicon film 15 was deposited on the entire surface to a thickness of about 2000 as a third conductive film, and then arsenic was heated at 50 KeV, lX1()"a.
Ion implantation is performed under conditions of n-'', and a polycrystalline silicon film 15, which is a third conductive film, is formed by photolithography and etching so as to cover the opening.

Furthermore, by performing a desired heat treatment, arsenic added to the polysilicon, which is the third conductor film, is diffused into the silicon substrate.
At the same time as forming the emitter region 1'6 of the mold, the final external base region 12 and internal base region 13 are formed (FIG. 1(e)).

Thereafter, a base contact is formed on the first polycrystalline silicon using photolithography and etching, and aluminum electrode wiring is further formed to form a bipolar transistor (not shown).

In the above embodiment, the internal base layer is formed using a silicon nitride film 7. Although the silicon oxide film 6 was removed by etching and a thin thermal oxide film was formed again, it is also possible to form it by implanting sulfur after removing the silicon nitride film 7 or after removing the silicon oxide film 6. can.

When you want to control the relationship between the size of the external base layer diffusion region and the emitter layer diffusion region for the purpose of improving the emitter breakdown voltage, etc., or to further reduce the emitter junction capacitance or the emitter crowding effect, use emitter diffusion. To reduce the width, do the following: That is, after forming the internal base layer 13 as shown in FIG. 2, a polycrystalline silicon film 17 is formed on the side wall of the opening.
selectively remain to narrow the aperture. This state can be obtained by performing ion implantation to form the internal base layer 13, depositing a polycrystalline silicon film of a predetermined thickness, and etching the entire surface using reactive ion etching. This provides a narrow emitter diffusion opening. Furthermore, by selecting a material with a low dielectric constant as the material left on the side wall of the opening, the parasitic capacitance between the emitter and the base can be reduced.

Further, in the above embodiment, the emitter layer was formed by solid phase diffusion from the polycrystalline silicon film which is the third conductor film.
It can also be formed by direct ion implantation. In that case, the silicon oxide film used as a buffer layer for ion implantation when forming the internal base layer may be used as is, and ions may be implanted to form the emitter layer through this oxide film. The ion implantation may be performed after removing the . Alternatively, the acceleration voltage for ion implantation may be adjusted to perform ion implantation through a polycrystalline silicon film serving as a third conductor film for forming an emitter.

In the above embodiments, polycrystalline silicon films were used as the first to third conductor films. Other materials can be used as long as these materials are not used as in-phase diffusion sources for impurities. However, in the structure of the above embodiment, the first and second conductive films must be made of a material that can form a thermal oxide film on the surface by thermal oxidation, such as molybdenum silicide,
Refractory metal silicides such as tungsten silicide are useful.

The pond water invention can be implemented with various modifications without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, when side-etching an oxidation-resistant insulating film to form an overhang portion in order to form an external base region, it is possible to perform extremely controllable processing using heated phosphoric acid treatment as in the conventional method.

It has become possible to use reactive plasma etching, a process that can be easily and precisely controlled, without using processes with poor reproducibility. Therefore, a high-performance bipolar transistor with excellent characteristics such as junction breakdown voltage and cut-off frequency, and with little variation in these characteristics can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention in order of process, and FIG. 2 is a process of forming an opening in an emitter region of another embodiment. 3(a) to (3) are cross-sectional views for explaining the
d) is a cross-sectional view showing the manufacturing process of a conventional bipolar transistor in order of process. 1...p-type silicon substrate 2...n-type buried layer 3...n-type epitaxial layer (collector layer) 4.5.
...Trench region, insulating oxide film (silicon oxide film for isolation) 6, ... silicon oxide film (first insulating film) 7... silicon nitride film (oxidation-resistant insulating film) 8... CvD. Silicon oxide film (second insulating film) 9... Polycrystalline silicon film (first conductor film) 19, 29... Thermal oxide film (third insulating film) 10... Cavity (overhang part) ) 11... Polycrystalline silicon film (second conductor film) 31, 4
1... Silicon oxide film (thermal oxide film) 12, 22...
External base region 13...inner base region 15...polycrystalline silicon layer (third conductor film) 16...
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Claims (2)

[Claims] (1) A first insulating film, an oxidation-resistant insulating film, a second insulating film, and a first conductive film are sequentially laminated on a semiconductor substrate having a first conductivity type collector layer separated by an element isolation region. adding impurity atoms of a second conductivity type to the first conductive film at a high concentration, and removing the first conductive film in the area where the emitter region is to be formed until the second insulating film is exposed. forming an opening, removing the second insulating film in the opening to expose the oxidation-resistant insulating film, and converting the exposed portion of the first conductive film into a third insulating film. The third insulating film is used as a mask to remove the oxidation-resistant insulating film exposed by etching until the first insulating film is exposed, and then over-etching the region where the base region is to be formed to form a first conductor film. forming a cavity below the second insulating film remaining thereunder; etching away the exposed first insulating film until the semiconductor substrate is exposed; and simultaneously forming a second insulating film exposed above the cavity. a step of etching away the insulating film until the first conductor film is exposed; a step of selectively embedding a second conductor film that will become a part of the base electrode in the cavity; and a step of removing the semiconductor substrate exposed in the opening. , and at the same time forming a thermal oxide film on the side wall portion of the second conductor film, impurity atoms of the second conductivity type added in advance to the first conductor film are diffused into the collector layer to form an external layer of the second conductivity type. a step of forming a base layer; a step of adding impurity atoms of a second conductivity type to an exposed portion of the opening of the semiconductor substrate to form an internal base layer of a second conductivity type; and forming the internal base layer. exposing the semiconductor substrate through the opening and depositing thereon a third conductor film that will become a part of the emitter electrode; and diffusing impurity atoms into the semiconductor substrate through the third conductor film. A method for manufacturing a semiconductor device including a step of forming a conductive emitter layer. (2) The semiconductor device according to claim 1, wherein the oxidation-resistant insulating film is etched away by reactive plasma etching using the first insulating film and the second insulating film as masks. manufacturing method.